1 /*
2  *  Copyright (C) 1995  Linus Torvalds
3  *  Adapted from 'alpha' version by Gary Thomas
4  *  Modified by Cort Dougan (cort@cs.nmt.edu)
5  */
6 
7 /*
8  * bootup setup stuff..
9  */
10 
11 #include <linux/errno.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
14 #include <linux/mm.h>
15 #include <linux/stddef.h>
16 #include <linux/unistd.h>
17 #include <linux/ptrace.h>
18 #include <linux/user.h>
19 #include <linux/tty.h>
20 #include <linux/major.h>
21 #include <linux/interrupt.h>
22 #include <linux/reboot.h>
23 #include <linux/init.h>
24 #include <linux/pci.h>
25 #include <generated/utsrelease.h>
26 #include <linux/adb.h>
27 #include <linux/module.h>
28 #include <linux/delay.h>
29 #include <linux/console.h>
30 #include <linux/seq_file.h>
31 #include <linux/root_dev.h>
32 #include <linux/initrd.h>
33 #include <linux/timer.h>
34 
35 #include <asm/io.h>
36 #include <asm/pgtable.h>
37 #include <asm/prom.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/dma.h>
40 #include <asm/machdep.h>
41 #include <asm/irq.h>
42 #include <asm/hydra.h>
43 #include <asm/sections.h>
44 #include <asm/time.h>
45 #include <asm/i8259.h>
46 #include <asm/mpic.h>
47 #include <asm/rtas.h>
48 #include <asm/xmon.h>
49 
50 #include "chrp.h"
51 #include "gg2.h"
52 
53 void rtas_indicator_progress(char *, unsigned short);
54 
55 int _chrp_type;
56 EXPORT_SYMBOL(_chrp_type);
57 
58 static struct mpic *chrp_mpic;
59 
60 /* Used for doing CHRP event-scans */
61 DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
62 unsigned long event_scan_interval;
63 
64 extern unsigned long loops_per_jiffy;
65 
66 /* To be replaced by RTAS when available */
67 static unsigned int __iomem *briq_SPOR;
68 
69 #ifdef CONFIG_SMP
70 extern struct smp_ops_t chrp_smp_ops;
71 #endif
72 
73 static const char *gg2_memtypes[4] = {
74 	"FPM", "SDRAM", "EDO", "BEDO"
75 };
76 static const char *gg2_cachesizes[4] = {
77 	"256 KB", "512 KB", "1 MB", "Reserved"
78 };
79 static const char *gg2_cachetypes[4] = {
80 	"Asynchronous", "Reserved", "Flow-Through Synchronous",
81 	"Pipelined Synchronous"
82 };
83 static const char *gg2_cachemodes[4] = {
84 	"Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
85 };
86 
87 static const char *chrp_names[] = {
88 	"Unknown",
89 	"","","",
90 	"Motorola",
91 	"IBM or Longtrail",
92 	"Genesi Pegasos",
93 	"Total Impact Briq"
94 };
95 
96 void chrp_show_cpuinfo(struct seq_file *m)
97 {
98 	int i, sdramen;
99 	unsigned int t;
100 	struct device_node *root;
101 	const char *model = "";
102 
103 	root = of_find_node_by_path("/");
104 	if (root)
105 		model = of_get_property(root, "model", NULL);
106 	seq_printf(m, "machine\t\t: CHRP %s\n", model);
107 
108 	/* longtrail (goldengate) stuff */
109 	if (model && !strncmp(model, "IBM,LongTrail", 13)) {
110 		/* VLSI VAS96011/12 `Golden Gate 2' */
111 		/* Memory banks */
112 		sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
113 			   >>31) & 1;
114 		for (i = 0; i < (sdramen ? 4 : 6); i++) {
115 			t = in_le32(gg2_pci_config_base+
116 						 GG2_PCI_DRAM_BANK0+
117 						 i*4);
118 			if (!(t & 1))
119 				continue;
120 			switch ((t>>8) & 0x1f) {
121 			case 0x1f:
122 				model = "4 MB";
123 				break;
124 			case 0x1e:
125 				model = "8 MB";
126 				break;
127 			case 0x1c:
128 				model = "16 MB";
129 				break;
130 			case 0x18:
131 				model = "32 MB";
132 				break;
133 			case 0x10:
134 				model = "64 MB";
135 				break;
136 			case 0x00:
137 				model = "128 MB";
138 				break;
139 			default:
140 				model = "Reserved";
141 				break;
142 			}
143 			seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
144 				   gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
145 		}
146 		/* L2 cache */
147 		t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
148 		seq_printf(m, "board l2\t: %s %s (%s)\n",
149 			   gg2_cachesizes[(t>>7) & 3],
150 			   gg2_cachetypes[(t>>2) & 3],
151 			   gg2_cachemodes[t & 3]);
152 	}
153 	of_node_put(root);
154 }
155 
156 /*
157  *  Fixes for the National Semiconductor PC78308VUL SuperI/O
158  *
159  *  Some versions of Open Firmware incorrectly initialize the IRQ settings
160  *  for keyboard and mouse
161  */
162 static inline void __init sio_write(u8 val, u8 index)
163 {
164 	outb(index, 0x15c);
165 	outb(val, 0x15d);
166 }
167 
168 static inline u8 __init sio_read(u8 index)
169 {
170 	outb(index, 0x15c);
171 	return inb(0x15d);
172 }
173 
174 static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
175 				     u8 type)
176 {
177 	u8 level0, type0, active;
178 
179 	/* select logical device */
180 	sio_write(device, 0x07);
181 	active = sio_read(0x30);
182 	level0 = sio_read(0x70);
183 	type0 = sio_read(0x71);
184 	if (level0 != level || type0 != type || !active) {
185 		printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
186 		       "remapping to level %d, type %d, active\n",
187 		       name, level0, type0, !active ? "in" : "", level, type);
188 		sio_write(0x01, 0x30);
189 		sio_write(level, 0x70);
190 		sio_write(type, 0x71);
191 	}
192 }
193 
194 static void __init sio_init(void)
195 {
196 	struct device_node *root;
197 	const char *model;
198 
199 	root = of_find_node_by_path("/");
200 	if (!root)
201 		return;
202 
203 	model = of_get_property(root, "model", NULL);
204 	if (model && !strncmp(model, "IBM,LongTrail", 13)) {
205 		/* logical device 0 (KBC/Keyboard) */
206 		sio_fixup_irq("keyboard", 0, 1, 2);
207 		/* select logical device 1 (KBC/Mouse) */
208 		sio_fixup_irq("mouse", 1, 12, 2);
209 	}
210 
211 	of_node_put(root);
212 }
213 
214 
215 static void __init pegasos_set_l2cr(void)
216 {
217 	struct device_node *np;
218 
219 	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
220 	if (_chrp_type != _CHRP_Pegasos)
221 		return;
222 
223 	/* Enable L2 cache if needed */
224 	np = of_find_node_by_type(NULL, "cpu");
225 	if (np != NULL) {
226 		const unsigned int *l2cr = of_get_property(np, "l2cr", NULL);
227 		if (l2cr == NULL) {
228 			printk ("Pegasos l2cr : no cpu l2cr property found\n");
229 			goto out;
230 		}
231 		if (!((*l2cr) & 0x80000000)) {
232 			printk ("Pegasos l2cr : L2 cache was not active, "
233 				"activating\n");
234 			_set_L2CR(0);
235 			_set_L2CR((*l2cr) | 0x80000000);
236 		}
237 	}
238 out:
239 	of_node_put(np);
240 }
241 
242 static void __noreturn briq_restart(char *cmd)
243 {
244 	local_irq_disable();
245 	if (briq_SPOR)
246 		out_be32(briq_SPOR, 0);
247 	for(;;);
248 }
249 
250 /*
251  * Per default, input/output-device points to the keyboard/screen
252  * If no card is installed, the built-in serial port is used as a fallback.
253  * But unfortunately, the firmware does not connect /chosen/{stdin,stdout}
254  * the the built-in serial node. Instead, a /failsafe node is created.
255  */
256 static __init void chrp_init(void)
257 {
258 	struct device_node *node;
259 	const char *property;
260 
261 	if (strstr(boot_command_line, "console="))
262 		return;
263 	/* find the boot console from /chosen/stdout */
264 	if (!of_chosen)
265 		return;
266 	node = of_find_node_by_path("/");
267 	if (!node)
268 		return;
269 	property = of_get_property(node, "model", NULL);
270 	if (!property)
271 		goto out_put;
272 	if (strcmp(property, "Pegasos2"))
273 		goto out_put;
274 	/* this is a Pegasos2 */
275 	property = of_get_property(of_chosen, "linux,stdout-path", NULL);
276 	if (!property)
277 		goto out_put;
278 	of_node_put(node);
279 	node = of_find_node_by_path(property);
280 	if (!node)
281 		return;
282 	property = of_get_property(node, "device_type", NULL);
283 	if (!property)
284 		goto out_put;
285 	if (strcmp(property, "serial"))
286 		goto out_put;
287 	/*
288 	 * The 9pin connector is either /failsafe
289 	 * or /pci@80000000/isa@C/serial@i2F8
290 	 * The optional graphics card has also type 'serial' in VGA mode.
291 	 */
292 	property = of_get_property(node, "name", NULL);
293 	if (!property)
294 		goto out_put;
295 	if (!strcmp(property, "failsafe") || !strcmp(property, "serial"))
296 		add_preferred_console("ttyS", 0, NULL);
297 out_put:
298 	of_node_put(node);
299 }
300 
301 void __init chrp_setup_arch(void)
302 {
303 	struct device_node *root = of_find_node_by_path("/");
304 	const char *machine = NULL;
305 
306 	/* init to some ~sane value until calibrate_delay() runs */
307 	loops_per_jiffy = 50000000/HZ;
308 
309 	if (root)
310 		machine = of_get_property(root, "model", NULL);
311 	if (machine && strncmp(machine, "Pegasos", 7) == 0) {
312 		_chrp_type = _CHRP_Pegasos;
313 	} else if (machine && strncmp(machine, "IBM", 3) == 0) {
314 		_chrp_type = _CHRP_IBM;
315 	} else if (machine && strncmp(machine, "MOT", 3) == 0) {
316 		_chrp_type = _CHRP_Motorola;
317 	} else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
318 		_chrp_type = _CHRP_briq;
319 		/* Map the SPOR register on briq and change the restart hook */
320 		briq_SPOR = ioremap(0xff0000e8, 4);
321 		ppc_md.restart = briq_restart;
322 	} else {
323 		/* Let's assume it is an IBM chrp if all else fails */
324 		_chrp_type = _CHRP_IBM;
325 	}
326 	of_node_put(root);
327 	printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);
328 
329 	rtas_initialize();
330 	if (rtas_token("display-character") >= 0)
331 		ppc_md.progress = rtas_progress;
332 
333 	/* use RTAS time-of-day routines if available */
334 	if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
335 		ppc_md.get_boot_time	= rtas_get_boot_time;
336 		ppc_md.get_rtc_time	= rtas_get_rtc_time;
337 		ppc_md.set_rtc_time	= rtas_set_rtc_time;
338 	}
339 
340 	/* On pegasos, enable the L2 cache if not already done by OF */
341 	pegasos_set_l2cr();
342 
343 	/* Lookup PCI host bridges */
344 	chrp_find_bridges();
345 
346 	/*
347 	 *  Temporary fixes for PCI devices.
348 	 *  -- Geert
349 	 */
350 	hydra_init();		/* Mac I/O */
351 
352 	/*
353 	 *  Fix the Super I/O configuration
354 	 */
355 	sio_init();
356 
357 	pci_create_OF_bus_map();
358 
359 	/*
360 	 * Print the banner, then scroll down so boot progress
361 	 * can be printed.  -- Cort
362 	 */
363 	if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
364 }
365 
366 static void chrp_8259_cascade(struct irq_desc *desc)
367 {
368 	struct irq_chip *chip = irq_desc_get_chip(desc);
369 	unsigned int cascade_irq = i8259_irq();
370 
371 	if (cascade_irq)
372 		generic_handle_irq(cascade_irq);
373 
374 	chip->irq_eoi(&desc->irq_data);
375 }
376 
377 /*
378  * Finds the open-pic node and sets up the mpic driver.
379  */
380 static void __init chrp_find_openpic(void)
381 {
382 	struct device_node *np, *root;
383 	int len, i, j;
384 	int isu_size, idu_size;
385 	const unsigned int *iranges, *opprop = NULL;
386 	int oplen = 0;
387 	unsigned long opaddr;
388 	int na = 1;
389 
390 	np = of_find_node_by_type(NULL, "open-pic");
391 	if (np == NULL)
392 		return;
393 	root = of_find_node_by_path("/");
394 	if (root) {
395 		opprop = of_get_property(root, "platform-open-pic", &oplen);
396 		na = of_n_addr_cells(root);
397 	}
398 	if (opprop && oplen >= na * sizeof(unsigned int)) {
399 		opaddr = opprop[na-1];	/* assume 32-bit */
400 		oplen /= na * sizeof(unsigned int);
401 	} else {
402 		struct resource r;
403 		if (of_address_to_resource(np, 0, &r)) {
404 			goto bail;
405 		}
406 		opaddr = r.start;
407 		oplen = 0;
408 	}
409 
410 	printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
411 
412 	iranges = of_get_property(np, "interrupt-ranges", &len);
413 	if (iranges == NULL)
414 		len = 0;	/* non-distributed mpic */
415 	else
416 		len /= 2 * sizeof(unsigned int);
417 
418 	/*
419 	 * The first pair of cells in interrupt-ranges refers to the
420 	 * IDU; subsequent pairs refer to the ISUs.
421 	 */
422 	if (oplen < len) {
423 		printk(KERN_ERR "Insufficient addresses for distributed"
424 		       " OpenPIC (%d < %d)\n", oplen, len);
425 		len = oplen;
426 	}
427 
428 	isu_size = 0;
429 	idu_size = 0;
430 	if (len > 0 && iranges[1] != 0) {
431 		printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
432 		       iranges[0], iranges[0] + iranges[1] - 1);
433 		idu_size = iranges[1];
434 	}
435 	if (len > 1)
436 		isu_size = iranges[3];
437 
438 	chrp_mpic = mpic_alloc(np, opaddr, MPIC_NO_RESET,
439 			isu_size, 0, " MPIC    ");
440 	if (chrp_mpic == NULL) {
441 		printk(KERN_ERR "Failed to allocate MPIC structure\n");
442 		goto bail;
443 	}
444 	j = na - 1;
445 	for (i = 1; i < len; ++i) {
446 		iranges += 2;
447 		j += na;
448 		printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
449 		       iranges[0], iranges[0] + iranges[1] - 1,
450 		       opprop[j]);
451 		mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
452 	}
453 
454 	mpic_init(chrp_mpic);
455 	ppc_md.get_irq = mpic_get_irq;
456  bail:
457 	of_node_put(root);
458 	of_node_put(np);
459 }
460 
461 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
462 static struct irqaction xmon_irqaction = {
463 	.handler = xmon_irq,
464 	.name = "XMON break",
465 };
466 #endif
467 
468 static void __init chrp_find_8259(void)
469 {
470 	struct device_node *np, *pic = NULL;
471 	unsigned long chrp_int_ack = 0;
472 	unsigned int cascade_irq;
473 
474 	/* Look for cascade */
475 	for_each_node_by_type(np, "interrupt-controller")
476 		if (of_device_is_compatible(np, "chrp,iic")) {
477 			pic = np;
478 			break;
479 		}
480 	/* Ok, 8259 wasn't found. We need to handle the case where
481 	 * we have a pegasos that claims to be chrp but doesn't have
482 	 * a proper interrupt tree
483 	 */
484 	if (pic == NULL && chrp_mpic != NULL) {
485 		printk(KERN_ERR "i8259: Not found in device-tree"
486 		       " assuming no legacy interrupts\n");
487 		return;
488 	}
489 
490 	/* Look for intack. In a perfect world, we would look for it on
491 	 * the ISA bus that holds the 8259 but heh... Works that way. If
492 	 * we ever see a problem, we can try to re-use the pSeries code here.
493 	 * Also, Pegasos-type platforms don't have a proper node to start
494 	 * from anyway
495 	 */
496 	for_each_node_by_name(np, "pci") {
497 		const unsigned int *addrp = of_get_property(np,
498 				"8259-interrupt-acknowledge", NULL);
499 
500 		if (addrp == NULL)
501 			continue;
502 		chrp_int_ack = addrp[of_n_addr_cells(np)-1];
503 		break;
504 	}
505 	of_node_put(np);
506 	if (np == NULL)
507 		printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
508 		       " address, polling\n");
509 
510 	i8259_init(pic, chrp_int_ack);
511 	if (ppc_md.get_irq == NULL) {
512 		ppc_md.get_irq = i8259_irq;
513 		irq_set_default_host(i8259_get_host());
514 	}
515 	if (chrp_mpic != NULL) {
516 		cascade_irq = irq_of_parse_and_map(pic, 0);
517 		if (!cascade_irq)
518 			printk(KERN_ERR "i8259: failed to map cascade irq\n");
519 		else
520 			irq_set_chained_handler(cascade_irq,
521 						chrp_8259_cascade);
522 	}
523 }
524 
525 void __init chrp_init_IRQ(void)
526 {
527 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
528 	struct device_node *kbd;
529 #endif
530 	chrp_find_openpic();
531 	chrp_find_8259();
532 
533 #ifdef CONFIG_SMP
534 	/* Pegasos has no MPIC, those ops would make it crash. It might be an
535 	 * option to move setting them to after we probe the PIC though
536 	 */
537 	if (chrp_mpic != NULL)
538 		smp_ops = &chrp_smp_ops;
539 #endif /* CONFIG_SMP */
540 
541 	if (_chrp_type == _CHRP_Pegasos)
542 		ppc_md.get_irq        = i8259_irq;
543 
544 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
545 	/* see if there is a keyboard in the device tree
546 	   with a parent of type "adb" */
547 	for_each_node_by_name(kbd, "keyboard")
548 		if (kbd->parent && kbd->parent->type
549 		    && strcmp(kbd->parent->type, "adb") == 0)
550 			break;
551 	of_node_put(kbd);
552 	if (kbd)
553 		setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
554 #endif
555 }
556 
557 void __init
558 chrp_init2(void)
559 {
560 #ifdef CONFIG_NVRAM
561 	chrp_nvram_init();
562 #endif
563 
564 	request_region(0x20,0x20,"pic1");
565 	request_region(0xa0,0x20,"pic2");
566 	request_region(0x00,0x20,"dma1");
567 	request_region(0x40,0x20,"timer");
568 	request_region(0x80,0x10,"dma page reg");
569 	request_region(0xc0,0x20,"dma2");
570 
571 	if (ppc_md.progress)
572 		ppc_md.progress("  Have fun!    ", 0x7777);
573 }
574 
575 static int __init chrp_probe(void)
576 {
577 	const char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
578 						"device_type", NULL);
579  	if (dtype == NULL)
580  		return 0;
581  	if (strcmp(dtype, "chrp"))
582 		return 0;
583 
584 	ISA_DMA_THRESHOLD = ~0L;
585 	DMA_MODE_READ = 0x44;
586 	DMA_MODE_WRITE = 0x48;
587 
588 	pm_power_off = rtas_power_off;
589 
590 	chrp_init();
591 
592 	return 1;
593 }
594 
595 define_machine(chrp) {
596 	.name			= "CHRP",
597 	.probe			= chrp_probe,
598 	.setup_arch		= chrp_setup_arch,
599 	.init			= chrp_init2,
600 	.show_cpuinfo		= chrp_show_cpuinfo,
601 	.init_IRQ		= chrp_init_IRQ,
602 	.restart		= rtas_restart,
603 	.halt			= rtas_halt,
604 	.time_init		= chrp_time_init,
605 	.set_rtc_time		= chrp_set_rtc_time,
606 	.get_rtc_time		= chrp_get_rtc_time,
607 	.calibrate_decr		= generic_calibrate_decr,
608 	.phys_mem_access_prot	= pci_phys_mem_access_prot,
609 };
610