1 /* 2 * Copyright (C) 1995 Linus Torvalds 3 * Adapted from 'alpha' version by Gary Thomas 4 * Modified by Cort Dougan (cort@cs.nmt.edu) 5 */ 6 7 /* 8 * bootup setup stuff.. 9 */ 10 11 #include <linux/errno.h> 12 #include <linux/sched.h> 13 #include <linux/kernel.h> 14 #include <linux/mm.h> 15 #include <linux/stddef.h> 16 #include <linux/unistd.h> 17 #include <linux/ptrace.h> 18 #include <linux/slab.h> 19 #include <linux/user.h> 20 #include <linux/a.out.h> 21 #include <linux/tty.h> 22 #include <linux/major.h> 23 #include <linux/interrupt.h> 24 #include <linux/reboot.h> 25 #include <linux/init.h> 26 #include <linux/pci.h> 27 #include <linux/utsrelease.h> 28 #include <linux/adb.h> 29 #include <linux/module.h> 30 #include <linux/delay.h> 31 #include <linux/console.h> 32 #include <linux/seq_file.h> 33 #include <linux/root_dev.h> 34 #include <linux/initrd.h> 35 #include <linux/timer.h> 36 37 #include <asm/io.h> 38 #include <asm/pgtable.h> 39 #include <asm/prom.h> 40 #include <asm/pci-bridge.h> 41 #include <asm/dma.h> 42 #include <asm/machdep.h> 43 #include <asm/irq.h> 44 #include <asm/hydra.h> 45 #include <asm/sections.h> 46 #include <asm/time.h> 47 #include <asm/i8259.h> 48 #include <asm/mpic.h> 49 #include <asm/rtas.h> 50 #include <asm/xmon.h> 51 52 #include "chrp.h" 53 #include "gg2.h" 54 55 void rtas_indicator_progress(char *, unsigned short); 56 57 int _chrp_type; 58 EXPORT_SYMBOL(_chrp_type); 59 60 static struct mpic *chrp_mpic; 61 62 /* Used for doing CHRP event-scans */ 63 DEFINE_PER_CPU(struct timer_list, heartbeat_timer); 64 unsigned long event_scan_interval; 65 66 /* 67 * XXX this should be in xmon.h, but putting it there means xmon.h 68 * has to include <linux/interrupt.h> (to get irqreturn_t), which 69 * causes all sorts of problems. -- paulus 70 */ 71 extern irqreturn_t xmon_irq(int, void *); 72 73 extern unsigned long loops_per_jiffy; 74 75 /* To be replaced by RTAS when available */ 76 static unsigned int __iomem *briq_SPOR; 77 78 #ifdef CONFIG_SMP 79 extern struct smp_ops_t chrp_smp_ops; 80 #endif 81 82 static const char *gg2_memtypes[4] = { 83 "FPM", "SDRAM", "EDO", "BEDO" 84 }; 85 static const char *gg2_cachesizes[4] = { 86 "256 KB", "512 KB", "1 MB", "Reserved" 87 }; 88 static const char *gg2_cachetypes[4] = { 89 "Asynchronous", "Reserved", "Flow-Through Synchronous", 90 "Pipelined Synchronous" 91 }; 92 static const char *gg2_cachemodes[4] = { 93 "Disabled", "Write-Through", "Copy-Back", "Transparent Mode" 94 }; 95 96 static const char *chrp_names[] = { 97 "Unknown", 98 "","","", 99 "Motorola", 100 "IBM or Longtrail", 101 "Genesi Pegasos", 102 "Total Impact Briq" 103 }; 104 105 void chrp_show_cpuinfo(struct seq_file *m) 106 { 107 int i, sdramen; 108 unsigned int t; 109 struct device_node *root; 110 const char *model = ""; 111 112 root = of_find_node_by_path("/"); 113 if (root) 114 model = of_get_property(root, "model", NULL); 115 seq_printf(m, "machine\t\t: CHRP %s\n", model); 116 117 /* longtrail (goldengate) stuff */ 118 if (model && !strncmp(model, "IBM,LongTrail", 13)) { 119 /* VLSI VAS96011/12 `Golden Gate 2' */ 120 /* Memory banks */ 121 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL) 122 >>31) & 1; 123 for (i = 0; i < (sdramen ? 4 : 6); i++) { 124 t = in_le32(gg2_pci_config_base+ 125 GG2_PCI_DRAM_BANK0+ 126 i*4); 127 if (!(t & 1)) 128 continue; 129 switch ((t>>8) & 0x1f) { 130 case 0x1f: 131 model = "4 MB"; 132 break; 133 case 0x1e: 134 model = "8 MB"; 135 break; 136 case 0x1c: 137 model = "16 MB"; 138 break; 139 case 0x18: 140 model = "32 MB"; 141 break; 142 case 0x10: 143 model = "64 MB"; 144 break; 145 case 0x00: 146 model = "128 MB"; 147 break; 148 default: 149 model = "Reserved"; 150 break; 151 } 152 seq_printf(m, "memory bank %d\t: %s %s\n", i, model, 153 gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]); 154 } 155 /* L2 cache */ 156 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL); 157 seq_printf(m, "board l2\t: %s %s (%s)\n", 158 gg2_cachesizes[(t>>7) & 3], 159 gg2_cachetypes[(t>>2) & 3], 160 gg2_cachemodes[t & 3]); 161 } 162 of_node_put(root); 163 } 164 165 /* 166 * Fixes for the National Semiconductor PC78308VUL SuperI/O 167 * 168 * Some versions of Open Firmware incorrectly initialize the IRQ settings 169 * for keyboard and mouse 170 */ 171 static inline void __init sio_write(u8 val, u8 index) 172 { 173 outb(index, 0x15c); 174 outb(val, 0x15d); 175 } 176 177 static inline u8 __init sio_read(u8 index) 178 { 179 outb(index, 0x15c); 180 return inb(0x15d); 181 } 182 183 static void __init sio_fixup_irq(const char *name, u8 device, u8 level, 184 u8 type) 185 { 186 u8 level0, type0, active; 187 188 /* select logical device */ 189 sio_write(device, 0x07); 190 active = sio_read(0x30); 191 level0 = sio_read(0x70); 192 type0 = sio_read(0x71); 193 if (level0 != level || type0 != type || !active) { 194 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: " 195 "remapping to level %d, type %d, active\n", 196 name, level0, type0, !active ? "in" : "", level, type); 197 sio_write(0x01, 0x30); 198 sio_write(level, 0x70); 199 sio_write(type, 0x71); 200 } 201 } 202 203 static void __init sio_init(void) 204 { 205 struct device_node *root; 206 const char *model; 207 208 root = of_find_node_by_path("/"); 209 if (!root) 210 return; 211 212 model = of_get_property(root, "model", NULL); 213 if (model && !strncmp(model, "IBM,LongTrail", 13)) { 214 /* logical device 0 (KBC/Keyboard) */ 215 sio_fixup_irq("keyboard", 0, 1, 2); 216 /* select logical device 1 (KBC/Mouse) */ 217 sio_fixup_irq("mouse", 1, 12, 2); 218 } 219 220 of_node_put(root); 221 } 222 223 224 static void __init pegasos_set_l2cr(void) 225 { 226 struct device_node *np; 227 228 /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */ 229 if (_chrp_type != _CHRP_Pegasos) 230 return; 231 232 /* Enable L2 cache if needed */ 233 np = of_find_node_by_type(NULL, "cpu"); 234 if (np != NULL) { 235 const unsigned int *l2cr = of_get_property(np, "l2cr", NULL); 236 if (l2cr == NULL) { 237 printk ("Pegasos l2cr : no cpu l2cr property found\n"); 238 goto out; 239 } 240 if (!((*l2cr) & 0x80000000)) { 241 printk ("Pegasos l2cr : L2 cache was not active, " 242 "activating\n"); 243 _set_L2CR(0); 244 _set_L2CR((*l2cr) | 0x80000000); 245 } 246 } 247 out: 248 of_node_put(np); 249 } 250 251 static void briq_restart(char *cmd) 252 { 253 local_irq_disable(); 254 if (briq_SPOR) 255 out_be32(briq_SPOR, 0); 256 for(;;); 257 } 258 259 /* 260 * Per default, input/output-device points to the keyboard/screen 261 * If no card is installed, the built-in serial port is used as a fallback. 262 * But unfortunately, the firmware does not connect /chosen/{stdin,stdout} 263 * the the built-in serial node. Instead, a /failsafe node is created. 264 */ 265 static void chrp_init_early(void) 266 { 267 struct device_node *node; 268 const char *property; 269 270 if (strstr(cmd_line, "console=")) 271 return; 272 /* find the boot console from /chosen/stdout */ 273 if (!of_chosen) 274 return; 275 node = of_find_node_by_path("/"); 276 if (!node) 277 return; 278 property = of_get_property(node, "model", NULL); 279 if (!property) 280 goto out_put; 281 if (strcmp(property, "Pegasos2")) 282 goto out_put; 283 /* this is a Pegasos2 */ 284 property = of_get_property(of_chosen, "linux,stdout-path", NULL); 285 if (!property) 286 goto out_put; 287 of_node_put(node); 288 node = of_find_node_by_path(property); 289 if (!node) 290 return; 291 property = of_get_property(node, "device_type", NULL); 292 if (!property) 293 goto out_put; 294 if (strcmp(property, "serial")) 295 goto out_put; 296 /* 297 * The 9pin connector is either /failsafe 298 * or /pci@80000000/isa@C/serial@i2F8 299 * The optional graphics card has also type 'serial' in VGA mode. 300 */ 301 property = of_get_property(node, "name", NULL); 302 if (!property) 303 goto out_put; 304 if (!strcmp(property, "failsafe") || !strcmp(property, "serial")) 305 add_preferred_console("ttyS", 0, NULL); 306 out_put: 307 of_node_put(node); 308 } 309 310 void __init chrp_setup_arch(void) 311 { 312 struct device_node *root = of_find_node_by_path("/"); 313 const char *machine = NULL; 314 315 /* init to some ~sane value until calibrate_delay() runs */ 316 loops_per_jiffy = 50000000/HZ; 317 318 if (root) 319 machine = of_get_property(root, "model", NULL); 320 if (machine && strncmp(machine, "Pegasos", 7) == 0) { 321 _chrp_type = _CHRP_Pegasos; 322 } else if (machine && strncmp(machine, "IBM", 3) == 0) { 323 _chrp_type = _CHRP_IBM; 324 } else if (machine && strncmp(machine, "MOT", 3) == 0) { 325 _chrp_type = _CHRP_Motorola; 326 } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) { 327 _chrp_type = _CHRP_briq; 328 /* Map the SPOR register on briq and change the restart hook */ 329 briq_SPOR = ioremap(0xff0000e8, 4); 330 ppc_md.restart = briq_restart; 331 } else { 332 /* Let's assume it is an IBM chrp if all else fails */ 333 _chrp_type = _CHRP_IBM; 334 } 335 of_node_put(root); 336 printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]); 337 338 rtas_initialize(); 339 if (rtas_token("display-character") >= 0) 340 ppc_md.progress = rtas_progress; 341 342 /* use RTAS time-of-day routines if available */ 343 if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) { 344 ppc_md.get_boot_time = rtas_get_boot_time; 345 ppc_md.get_rtc_time = rtas_get_rtc_time; 346 ppc_md.set_rtc_time = rtas_set_rtc_time; 347 } 348 349 /* On pegasos, enable the L2 cache if not already done by OF */ 350 pegasos_set_l2cr(); 351 352 /* Lookup PCI host bridges */ 353 chrp_find_bridges(); 354 355 /* 356 * Temporary fixes for PCI devices. 357 * -- Geert 358 */ 359 hydra_init(); /* Mac I/O */ 360 361 /* 362 * Fix the Super I/O configuration 363 */ 364 sio_init(); 365 366 pci_create_OF_bus_map(); 367 368 /* 369 * Print the banner, then scroll down so boot progress 370 * can be printed. -- Cort 371 */ 372 if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0); 373 } 374 375 void 376 chrp_event_scan(unsigned long unused) 377 { 378 unsigned char log[1024]; 379 int ret = 0; 380 381 /* XXX: we should loop until the hardware says no more error logs -- Cort */ 382 rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0, 383 __pa(log), 1024); 384 mod_timer(&__get_cpu_var(heartbeat_timer), 385 jiffies + event_scan_interval); 386 } 387 388 static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc) 389 { 390 unsigned int cascade_irq = i8259_irq(); 391 if (cascade_irq != NO_IRQ) 392 generic_handle_irq(cascade_irq); 393 desc->chip->eoi(irq); 394 } 395 396 /* 397 * Finds the open-pic node and sets up the mpic driver. 398 */ 399 static void __init chrp_find_openpic(void) 400 { 401 struct device_node *np, *root; 402 int len, i, j; 403 int isu_size, idu_size; 404 const unsigned int *iranges, *opprop = NULL; 405 int oplen = 0; 406 unsigned long opaddr; 407 int na = 1; 408 409 np = of_find_node_by_type(NULL, "open-pic"); 410 if (np == NULL) 411 return; 412 root = of_find_node_by_path("/"); 413 if (root) { 414 opprop = of_get_property(root, "platform-open-pic", &oplen); 415 na = of_n_addr_cells(root); 416 } 417 if (opprop && oplen >= na * sizeof(unsigned int)) { 418 opaddr = opprop[na-1]; /* assume 32-bit */ 419 oplen /= na * sizeof(unsigned int); 420 } else { 421 struct resource r; 422 if (of_address_to_resource(np, 0, &r)) { 423 goto bail; 424 } 425 opaddr = r.start; 426 oplen = 0; 427 } 428 429 printk(KERN_INFO "OpenPIC at %lx\n", opaddr); 430 431 iranges = of_get_property(np, "interrupt-ranges", &len); 432 if (iranges == NULL) 433 len = 0; /* non-distributed mpic */ 434 else 435 len /= 2 * sizeof(unsigned int); 436 437 /* 438 * The first pair of cells in interrupt-ranges refers to the 439 * IDU; subsequent pairs refer to the ISUs. 440 */ 441 if (oplen < len) { 442 printk(KERN_ERR "Insufficient addresses for distributed" 443 " OpenPIC (%d < %d)\n", oplen, len); 444 len = oplen; 445 } 446 447 isu_size = 0; 448 idu_size = 0; 449 if (len > 0 && iranges[1] != 0) { 450 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n", 451 iranges[0], iranges[0] + iranges[1] - 1); 452 idu_size = iranges[1]; 453 } 454 if (len > 1) 455 isu_size = iranges[3]; 456 457 chrp_mpic = mpic_alloc(np, opaddr, MPIC_PRIMARY, 458 isu_size, 0, " MPIC "); 459 if (chrp_mpic == NULL) { 460 printk(KERN_ERR "Failed to allocate MPIC structure\n"); 461 goto bail; 462 } 463 j = na - 1; 464 for (i = 1; i < len; ++i) { 465 iranges += 2; 466 j += na; 467 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n", 468 iranges[0], iranges[0] + iranges[1] - 1, 469 opprop[j]); 470 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]); 471 } 472 473 mpic_init(chrp_mpic); 474 ppc_md.get_irq = mpic_get_irq; 475 bail: 476 of_node_put(root); 477 of_node_put(np); 478 } 479 480 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) 481 static struct irqaction xmon_irqaction = { 482 .handler = xmon_irq, 483 .mask = CPU_MASK_NONE, 484 .name = "XMON break", 485 }; 486 #endif 487 488 static void __init chrp_find_8259(void) 489 { 490 struct device_node *np, *pic = NULL; 491 unsigned long chrp_int_ack = 0; 492 unsigned int cascade_irq; 493 494 /* Look for cascade */ 495 for_each_node_by_type(np, "interrupt-controller") 496 if (of_device_is_compatible(np, "chrp,iic")) { 497 pic = np; 498 break; 499 } 500 /* Ok, 8259 wasn't found. We need to handle the case where 501 * we have a pegasos that claims to be chrp but doesn't have 502 * a proper interrupt tree 503 */ 504 if (pic == NULL && chrp_mpic != NULL) { 505 printk(KERN_ERR "i8259: Not found in device-tree" 506 " assuming no legacy interrupts\n"); 507 return; 508 } 509 510 /* Look for intack. In a perfect world, we would look for it on 511 * the ISA bus that holds the 8259 but heh... Works that way. If 512 * we ever see a problem, we can try to re-use the pSeries code here. 513 * Also, Pegasos-type platforms don't have a proper node to start 514 * from anyway 515 */ 516 for_each_node_by_name(np, "pci") { 517 const unsigned int *addrp = of_get_property(np, 518 "8259-interrupt-acknowledge", NULL); 519 520 if (addrp == NULL) 521 continue; 522 chrp_int_ack = addrp[of_n_addr_cells(np)-1]; 523 break; 524 } 525 of_node_put(np); 526 if (np == NULL) 527 printk(KERN_WARNING "Cannot find PCI interrupt acknowledge" 528 " address, polling\n"); 529 530 i8259_init(pic, chrp_int_ack); 531 if (ppc_md.get_irq == NULL) { 532 ppc_md.get_irq = i8259_irq; 533 irq_set_default_host(i8259_get_host()); 534 } 535 if (chrp_mpic != NULL) { 536 cascade_irq = irq_of_parse_and_map(pic, 0); 537 if (cascade_irq == NO_IRQ) 538 printk(KERN_ERR "i8259: failed to map cascade irq\n"); 539 else 540 set_irq_chained_handler(cascade_irq, 541 chrp_8259_cascade); 542 } 543 } 544 545 void __init chrp_init_IRQ(void) 546 { 547 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) 548 struct device_node *kbd; 549 #endif 550 chrp_find_openpic(); 551 chrp_find_8259(); 552 553 #ifdef CONFIG_SMP 554 /* Pegasos has no MPIC, those ops would make it crash. It might be an 555 * option to move setting them to after we probe the PIC though 556 */ 557 if (chrp_mpic != NULL) 558 smp_ops = &chrp_smp_ops; 559 #endif /* CONFIG_SMP */ 560 561 if (_chrp_type == _CHRP_Pegasos) 562 ppc_md.get_irq = i8259_irq; 563 564 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) 565 /* see if there is a keyboard in the device tree 566 with a parent of type "adb" */ 567 for_each_node_by_name(kbd, "keyboard") 568 if (kbd->parent && kbd->parent->type 569 && strcmp(kbd->parent->type, "adb") == 0) 570 break; 571 of_node_put(kbd); 572 if (kbd) 573 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction); 574 #endif 575 } 576 577 void __init 578 chrp_init2(void) 579 { 580 struct device_node *device; 581 const unsigned int *p = NULL; 582 583 #ifdef CONFIG_NVRAM 584 chrp_nvram_init(); 585 #endif 586 587 request_region(0x20,0x20,"pic1"); 588 request_region(0xa0,0x20,"pic2"); 589 request_region(0x00,0x20,"dma1"); 590 request_region(0x40,0x20,"timer"); 591 request_region(0x80,0x10,"dma page reg"); 592 request_region(0xc0,0x20,"dma2"); 593 594 /* Get the event scan rate for the rtas so we know how 595 * often it expects a heartbeat. -- Cort 596 */ 597 device = of_find_node_by_name(NULL, "rtas"); 598 if (device) 599 p = of_get_property(device, "rtas-event-scan-rate", NULL); 600 if (p && *p) { 601 /* 602 * Arrange to call chrp_event_scan at least *p times 603 * per minute. We use 59 rather than 60 here so that 604 * the rate will be slightly higher than the minimum. 605 * This all assumes we don't do hotplug CPU on any 606 * machine that needs the event scans done. 607 */ 608 unsigned long interval, offset; 609 int cpu, ncpus; 610 struct timer_list *timer; 611 612 interval = HZ * 59 / *p; 613 offset = HZ; 614 ncpus = num_online_cpus(); 615 event_scan_interval = ncpus * interval; 616 for (cpu = 0; cpu < ncpus; ++cpu) { 617 timer = &per_cpu(heartbeat_timer, cpu); 618 setup_timer(timer, chrp_event_scan, 0); 619 timer->expires = jiffies + offset; 620 add_timer_on(timer, cpu); 621 offset += interval; 622 } 623 printk("RTAS Event Scan Rate: %u (%lu jiffies)\n", 624 *p, interval); 625 } 626 of_node_put(device); 627 628 if (ppc_md.progress) 629 ppc_md.progress(" Have fun! ", 0x7777); 630 } 631 632 static int __init chrp_probe(void) 633 { 634 char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(), 635 "device_type", NULL); 636 if (dtype == NULL) 637 return 0; 638 if (strcmp(dtype, "chrp")) 639 return 0; 640 641 ISA_DMA_THRESHOLD = ~0L; 642 DMA_MODE_READ = 0x44; 643 DMA_MODE_WRITE = 0x48; 644 645 return 1; 646 } 647 648 define_machine(chrp) { 649 .name = "CHRP", 650 .probe = chrp_probe, 651 .setup_arch = chrp_setup_arch, 652 .init = chrp_init2, 653 .init_early = chrp_init_early, 654 .show_cpuinfo = chrp_show_cpuinfo, 655 .init_IRQ = chrp_init_IRQ, 656 .restart = rtas_restart, 657 .power_off = rtas_power_off, 658 .halt = rtas_halt, 659 .time_init = chrp_time_init, 660 .set_rtc_time = chrp_set_rtc_time, 661 .get_rtc_time = chrp_get_rtc_time, 662 .calibrate_decr = generic_calibrate_decr, 663 .phys_mem_access_prot = pci_phys_mem_access_prot, 664 }; 665