1 /* 2 * Copyright (C) 2005 Sven Luther <sl@bplan-gmbh.de> 3 * Thanks to : 4 * Dale Farnsworth <dale@farnsworth.org> 5 * Mark A. Greer <mgreer@mvista.com> 6 * Nicolas DET <nd@bplan-gmbh.de> 7 * Benjamin Herrenschmidt <benh@kernel.crashing.org> 8 * And anyone else who helped me on this. 9 */ 10 11 #include <linux/types.h> 12 #include <linux/init.h> 13 #include <linux/ioport.h> 14 #include <linux/device.h> 15 #include <linux/platform_device.h> 16 #include <linux/mv643xx.h> 17 #include <linux/pci.h> 18 19 #define PEGASOS2_MARVELL_REGBASE (0xf1000000) 20 #define PEGASOS2_MARVELL_REGSIZE (0x00004000) 21 #define PEGASOS2_SRAM_BASE (0xf2000000) 22 #define PEGASOS2_SRAM_SIZE (256*1024) 23 24 #define PEGASOS2_SRAM_BASE_ETH0 (PEGASOS2_SRAM_BASE) 25 #define PEGASOS2_SRAM_BASE_ETH1 (PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) ) 26 27 28 #define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4) 29 #define PEGASOS2_SRAM_TXRING_SIZE (PEGASOS2_SRAM_SIZE/4) 30 31 #undef BE_VERBOSE 32 33 static struct resource mv643xx_eth_shared_resources[] = { 34 [0] = { 35 .name = "ethernet shared base", 36 .start = 0xf1000000 + MV643XX_ETH_SHARED_REGS, 37 .end = 0xf1000000 + MV643XX_ETH_SHARED_REGS + 38 MV643XX_ETH_SHARED_REGS_SIZE - 1, 39 .flags = IORESOURCE_MEM, 40 }, 41 }; 42 43 static struct platform_device mv643xx_eth_shared_device = { 44 .name = MV643XX_ETH_SHARED_NAME, 45 .id = 0, 46 .num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources), 47 .resource = mv643xx_eth_shared_resources, 48 }; 49 50 static struct resource mv643xx_eth0_resources[] = { 51 [0] = { 52 .name = "eth0 irq", 53 .start = 9, 54 .end = 9, 55 .flags = IORESOURCE_IRQ, 56 }, 57 }; 58 59 60 static struct mv643xx_eth_platform_data eth0_pd = { 61 .port_number = 0, 62 .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH0, 63 .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE, 64 .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16, 65 66 .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH0 + PEGASOS2_SRAM_TXRING_SIZE, 67 .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE, 68 .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16, 69 }; 70 71 static struct platform_device eth0_device = { 72 .name = MV643XX_ETH_NAME, 73 .id = 0, 74 .num_resources = ARRAY_SIZE(mv643xx_eth0_resources), 75 .resource = mv643xx_eth0_resources, 76 .dev = { 77 .platform_data = ð0_pd, 78 }, 79 }; 80 81 static struct resource mv643xx_eth1_resources[] = { 82 [0] = { 83 .name = "eth1 irq", 84 .start = 9, 85 .end = 9, 86 .flags = IORESOURCE_IRQ, 87 }, 88 }; 89 90 static struct mv643xx_eth_platform_data eth1_pd = { 91 .port_number = 1, 92 .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH1, 93 .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE, 94 .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16, 95 96 .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH1 + PEGASOS2_SRAM_TXRING_SIZE, 97 .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE, 98 .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16, 99 }; 100 101 static struct platform_device eth1_device = { 102 .name = MV643XX_ETH_NAME, 103 .id = 1, 104 .num_resources = ARRAY_SIZE(mv643xx_eth1_resources), 105 .resource = mv643xx_eth1_resources, 106 .dev = { 107 .platform_data = ð1_pd, 108 }, 109 }; 110 111 static struct platform_device *mv643xx_eth_pd_devs[] __initdata = { 112 &mv643xx_eth_shared_device, 113 ð0_device, 114 ð1_device, 115 }; 116 117 /***********/ 118 /***********/ 119 #define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); } 120 #define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset) 121 122 static void __iomem *mv643xx_reg_base; 123 124 static int Enable_SRAM(void) 125 { 126 u32 ALong; 127 128 if (mv643xx_reg_base == NULL) 129 mv643xx_reg_base = ioremap(PEGASOS2_MARVELL_REGBASE, 130 PEGASOS2_MARVELL_REGSIZE); 131 132 if (mv643xx_reg_base == NULL) 133 return -ENOMEM; 134 135 #ifdef BE_VERBOSE 136 printk("Pegasos II/Marvell MV64361: register remapped from %p to %p\n", 137 (void *)PEGASOS2_MARVELL_REGBASE, (void *)mv643xx_reg_base); 138 #endif 139 140 MV_WRITE(MV64340_SRAM_CONFIG, 0); 141 142 MV_WRITE(MV64340_INTEGRATED_SRAM_BASE_ADDR, PEGASOS2_SRAM_BASE >> 16); 143 144 MV_READ(MV64340_BASE_ADDR_ENABLE, ALong); 145 ALong &= ~(1 << 19); 146 MV_WRITE(MV64340_BASE_ADDR_ENABLE, ALong); 147 148 ALong = 0x02; 149 ALong |= PEGASOS2_SRAM_BASE & 0xffff0000; 150 MV_WRITE(MV643XX_ETH_BAR_4, ALong); 151 152 MV_WRITE(MV643XX_ETH_SIZE_REG_4, (PEGASOS2_SRAM_SIZE-1) & 0xffff0000); 153 154 MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong); 155 ALong &= ~(1 << 4); 156 MV_WRITE(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong); 157 158 #ifdef BE_VERBOSE 159 printk("Pegasos II/Marvell MV64361: register unmapped\n"); 160 printk("Pegasos II/Marvell MV64361: SRAM at %p, size=%x\n", (void*) PEGASOS2_SRAM_BASE, PEGASOS2_SRAM_SIZE); 161 #endif 162 163 iounmap(mv643xx_reg_base); 164 mv643xx_reg_base = NULL; 165 166 return 1; 167 } 168 169 170 /***********/ 171 /***********/ 172 int mv643xx_eth_add_pds(void) 173 { 174 int ret = 0; 175 static struct pci_device_id pci_marvell_mv64360[] = { 176 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360) }, 177 { } 178 }; 179 180 #ifdef BE_VERBOSE 181 printk("Pegasos II/Marvell MV64361: init\n"); 182 #endif 183 184 if (pci_dev_present(pci_marvell_mv64360)) { 185 ret = platform_add_devices(mv643xx_eth_pd_devs, 186 ARRAY_SIZE(mv643xx_eth_pd_devs)); 187 188 if ( Enable_SRAM() < 0) 189 { 190 eth0_pd.tx_sram_addr = 0; 191 eth0_pd.tx_sram_size = 0; 192 eth0_pd.rx_sram_addr = 0; 193 eth0_pd.rx_sram_size = 0; 194 195 eth1_pd.tx_sram_addr = 0; 196 eth1_pd.tx_sram_size = 0; 197 eth1_pd.rx_sram_addr = 0; 198 eth1_pd.rx_sram_size = 0; 199 200 #ifdef BE_VERBOSE 201 printk("Pegasos II/Marvell MV64361: Can't enable the " 202 "SRAM\n"); 203 #endif 204 } 205 } 206 207 #ifdef BE_VERBOSE 208 printk("Pegasos II/Marvell MV64361: init is over\n"); 209 #endif 210 211 return ret; 212 } 213 214 device_initcall(mv643xx_eth_add_pds); 215