1 /* 2 * spu_switch.c 3 * 4 * (C) Copyright IBM Corp. 2005 5 * 6 * Author: Mark Nutter <mnutter@us.ibm.com> 7 * 8 * Host-side part of SPU context switch sequence outlined in 9 * Synergistic Processor Element, Book IV. 10 * 11 * A fully premptive switch of an SPE is very expensive in terms 12 * of time and system resources. SPE Book IV indicates that SPE 13 * allocation should follow a "serially reusable device" model, 14 * in which the SPE is assigned a task until it completes. When 15 * this is not possible, this sequence may be used to premptively 16 * save, and then later (optionally) restore the context of a 17 * program executing on an SPE. 18 * 19 * 20 * This program is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2, or (at your option) 23 * any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; if not, write to the Free Software 32 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 33 */ 34 35 #include <linux/module.h> 36 #include <linux/errno.h> 37 #include <linux/sched.h> 38 #include <linux/kernel.h> 39 #include <linux/mm.h> 40 #include <linux/vmalloc.h> 41 #include <linux/smp.h> 42 #include <linux/stddef.h> 43 #include <linux/unistd.h> 44 45 #include <asm/io.h> 46 #include <asm/spu.h> 47 #include <asm/spu_priv1.h> 48 #include <asm/spu_csa.h> 49 #include <asm/mmu_context.h> 50 51 #include "spufs.h" 52 53 #include "spu_save_dump.h" 54 #include "spu_restore_dump.h" 55 56 #if 0 57 #define POLL_WHILE_TRUE(_c) { \ 58 do { \ 59 } while (_c); \ 60 } 61 #else 62 #define RELAX_SPIN_COUNT 1000 63 #define POLL_WHILE_TRUE(_c) { \ 64 do { \ 65 int _i; \ 66 for (_i=0; _i<RELAX_SPIN_COUNT && (_c); _i++) { \ 67 cpu_relax(); \ 68 } \ 69 if (unlikely(_c)) yield(); \ 70 else break; \ 71 } while (_c); \ 72 } 73 #endif /* debug */ 74 75 #define POLL_WHILE_FALSE(_c) POLL_WHILE_TRUE(!(_c)) 76 77 static inline void acquire_spu_lock(struct spu *spu) 78 { 79 /* Save, Step 1: 80 * Restore, Step 1: 81 * Acquire SPU-specific mutual exclusion lock. 82 * TBD. 83 */ 84 } 85 86 static inline void release_spu_lock(struct spu *spu) 87 { 88 /* Restore, Step 76: 89 * Release SPU-specific mutual exclusion lock. 90 * TBD. 91 */ 92 } 93 94 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu) 95 { 96 struct spu_problem __iomem *prob = spu->problem; 97 u32 isolate_state; 98 99 /* Save, Step 2: 100 * Save, Step 6: 101 * If SPU_Status[E,L,IS] any field is '1', this 102 * SPU is in isolate state and cannot be context 103 * saved at this time. 104 */ 105 isolate_state = SPU_STATUS_ISOLATED_STATE | 106 SPU_STATUS_ISOLATED_LOAD_STATUS | SPU_STATUS_ISOLATED_EXIT_STATUS; 107 return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0; 108 } 109 110 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu) 111 { 112 /* Save, Step 3: 113 * Restore, Step 2: 114 * Save INT_Mask_class0 in CSA. 115 * Write INT_MASK_class0 with value of 0. 116 * Save INT_Mask_class1 in CSA. 117 * Write INT_MASK_class1 with value of 0. 118 * Save INT_Mask_class2 in CSA. 119 * Write INT_MASK_class2 with value of 0. 120 */ 121 spin_lock_irq(&spu->register_lock); 122 if (csa) { 123 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0); 124 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1); 125 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2); 126 } 127 spu_int_mask_set(spu, 0, 0ul); 128 spu_int_mask_set(spu, 1, 0ul); 129 spu_int_mask_set(spu, 2, 0ul); 130 eieio(); 131 spin_unlock_irq(&spu->register_lock); 132 } 133 134 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu) 135 { 136 /* Save, Step 4: 137 * Restore, Step 25. 138 * Set a software watchdog timer, which specifies the 139 * maximum allowable time for a context save sequence. 140 * 141 * For present, this implementation will not set a global 142 * watchdog timer, as virtualization & variable system load 143 * may cause unpredictable execution times. 144 */ 145 } 146 147 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu) 148 { 149 /* Save, Step 5: 150 * Restore, Step 3: 151 * Inhibit user-space access (if provided) to this 152 * SPU by unmapping the virtual pages assigned to 153 * the SPU memory-mapped I/O (MMIO) for problem 154 * state. TBD. 155 */ 156 } 157 158 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu) 159 { 160 /* Save, Step 7: 161 * Restore, Step 5: 162 * Set a software context switch pending flag. 163 */ 164 set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags); 165 mb(); 166 } 167 168 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu) 169 { 170 struct spu_priv2 __iomem *priv2 = spu->priv2; 171 172 /* Save, Step 8: 173 * Suspend DMA and save MFC_CNTL. 174 */ 175 switch (in_be64(&priv2->mfc_control_RW) & 176 MFC_CNTL_SUSPEND_DMA_STATUS_MASK) { 177 case MFC_CNTL_SUSPEND_IN_PROGRESS: 178 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & 179 MFC_CNTL_SUSPEND_DMA_STATUS_MASK) == 180 MFC_CNTL_SUSPEND_COMPLETE); 181 /* fall through */ 182 case MFC_CNTL_SUSPEND_COMPLETE: 183 if (csa) { 184 csa->priv2.mfc_control_RW = 185 MFC_CNTL_SUSPEND_MASK | 186 MFC_CNTL_SUSPEND_DMA_QUEUE; 187 } 188 break; 189 case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION: 190 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE); 191 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & 192 MFC_CNTL_SUSPEND_DMA_STATUS_MASK) == 193 MFC_CNTL_SUSPEND_COMPLETE); 194 if (csa) { 195 csa->priv2.mfc_control_RW = 0; 196 } 197 break; 198 } 199 } 200 201 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu) 202 { 203 struct spu_problem __iomem *prob = spu->problem; 204 205 /* Save, Step 9: 206 * Save SPU_Runcntl in the CSA. This value contains 207 * the "Application Desired State". 208 */ 209 csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW); 210 } 211 212 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu) 213 { 214 /* Save, Step 10: 215 * Save MFC_SR1 in the CSA. 216 */ 217 csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu); 218 } 219 220 static inline void save_spu_status(struct spu_state *csa, struct spu *spu) 221 { 222 struct spu_problem __iomem *prob = spu->problem; 223 224 /* Save, Step 11: 225 * Read SPU_Status[R], and save to CSA. 226 */ 227 if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) { 228 csa->prob.spu_status_R = in_be32(&prob->spu_status_R); 229 } else { 230 u32 stopped; 231 232 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP); 233 eieio(); 234 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & 235 SPU_STATUS_RUNNING); 236 stopped = 237 SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP | 238 SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP; 239 if ((in_be32(&prob->spu_status_R) & stopped) == 0) 240 csa->prob.spu_status_R = SPU_STATUS_RUNNING; 241 else 242 csa->prob.spu_status_R = in_be32(&prob->spu_status_R); 243 } 244 } 245 246 static inline void save_mfc_decr(struct spu_state *csa, struct spu *spu) 247 { 248 struct spu_priv2 __iomem *priv2 = spu->priv2; 249 250 /* Save, Step 12: 251 * Read MFC_CNTL[Ds]. Update saved copy of 252 * CSA.MFC_CNTL[Ds]. 253 */ 254 csa->priv2.mfc_control_RW |= 255 in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING; 256 } 257 258 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu) 259 { 260 struct spu_priv2 __iomem *priv2 = spu->priv2; 261 262 /* Save, Step 13: 263 * Write MFC_CNTL[Dh] set to a '1' to halt 264 * the decrementer. 265 */ 266 out_be64(&priv2->mfc_control_RW, 267 MFC_CNTL_DECREMENTER_HALTED | MFC_CNTL_SUSPEND_MASK); 268 eieio(); 269 } 270 271 static inline void save_timebase(struct spu_state *csa, struct spu *spu) 272 { 273 /* Save, Step 14: 274 * Read PPE Timebase High and Timebase low registers 275 * and save in CSA. TBD. 276 */ 277 csa->suspend_time = get_cycles(); 278 } 279 280 static inline void remove_other_spu_access(struct spu_state *csa, 281 struct spu *spu) 282 { 283 /* Save, Step 15: 284 * Remove other SPU access to this SPU by unmapping 285 * this SPU's pages from their address space. TBD. 286 */ 287 } 288 289 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu) 290 { 291 struct spu_problem __iomem *prob = spu->problem; 292 293 /* Save, Step 16: 294 * Restore, Step 11. 295 * Write SPU_MSSync register. Poll SPU_MSSync[P] 296 * for a value of 0. 297 */ 298 out_be64(&prob->spc_mssync_RW, 1UL); 299 POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING); 300 } 301 302 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu) 303 { 304 /* Save, Step 17: 305 * Restore, Step 12. 306 * Restore, Step 48. 307 * Write TLB_Invalidate_Entry[IS,VPN,L,Lp]=0 register. 308 * Then issue a PPE sync instruction. 309 */ 310 spu_tlb_invalidate(spu); 311 mb(); 312 } 313 314 static inline void handle_pending_interrupts(struct spu_state *csa, 315 struct spu *spu) 316 { 317 /* Save, Step 18: 318 * Handle any pending interrupts from this SPU 319 * here. This is OS or hypervisor specific. One 320 * option is to re-enable interrupts to handle any 321 * pending interrupts, with the interrupt handlers 322 * recognizing the software Context Switch Pending 323 * flag, to ensure the SPU execution or MFC command 324 * queue is not restarted. TBD. 325 */ 326 } 327 328 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu) 329 { 330 struct spu_priv2 __iomem *priv2 = spu->priv2; 331 int i; 332 333 /* Save, Step 19: 334 * If MFC_Cntl[Se]=0 then save 335 * MFC command queues. 336 */ 337 if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) { 338 for (i = 0; i < 8; i++) { 339 csa->priv2.puq[i].mfc_cq_data0_RW = 340 in_be64(&priv2->puq[i].mfc_cq_data0_RW); 341 csa->priv2.puq[i].mfc_cq_data1_RW = 342 in_be64(&priv2->puq[i].mfc_cq_data1_RW); 343 csa->priv2.puq[i].mfc_cq_data2_RW = 344 in_be64(&priv2->puq[i].mfc_cq_data2_RW); 345 csa->priv2.puq[i].mfc_cq_data3_RW = 346 in_be64(&priv2->puq[i].mfc_cq_data3_RW); 347 } 348 for (i = 0; i < 16; i++) { 349 csa->priv2.spuq[i].mfc_cq_data0_RW = 350 in_be64(&priv2->spuq[i].mfc_cq_data0_RW); 351 csa->priv2.spuq[i].mfc_cq_data1_RW = 352 in_be64(&priv2->spuq[i].mfc_cq_data1_RW); 353 csa->priv2.spuq[i].mfc_cq_data2_RW = 354 in_be64(&priv2->spuq[i].mfc_cq_data2_RW); 355 csa->priv2.spuq[i].mfc_cq_data3_RW = 356 in_be64(&priv2->spuq[i].mfc_cq_data3_RW); 357 } 358 } 359 } 360 361 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu) 362 { 363 struct spu_problem __iomem *prob = spu->problem; 364 365 /* Save, Step 20: 366 * Save the PPU_QueryMask register 367 * in the CSA. 368 */ 369 csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW); 370 } 371 372 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu) 373 { 374 struct spu_problem __iomem *prob = spu->problem; 375 376 /* Save, Step 21: 377 * Save the PPU_QueryType register 378 * in the CSA. 379 */ 380 csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW); 381 } 382 383 static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu) 384 { 385 struct spu_problem __iomem *prob = spu->problem; 386 387 /* Save the Prxy_TagStatus register in the CSA. 388 * 389 * It is unnecessary to restore dma_tagstatus_R, however, 390 * dma_tagstatus_R in the CSA is accessed via backing_ops, so 391 * we must save it. 392 */ 393 csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R); 394 } 395 396 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu) 397 { 398 struct spu_priv2 __iomem *priv2 = spu->priv2; 399 400 /* Save, Step 22: 401 * Save the MFC_CSR_TSQ register 402 * in the LSCSA. 403 */ 404 csa->priv2.spu_tag_status_query_RW = 405 in_be64(&priv2->spu_tag_status_query_RW); 406 } 407 408 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu) 409 { 410 struct spu_priv2 __iomem *priv2 = spu->priv2; 411 412 /* Save, Step 23: 413 * Save the MFC_CSR_CMD1 and MFC_CSR_CMD2 414 * registers in the CSA. 415 */ 416 csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW); 417 csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW); 418 } 419 420 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu) 421 { 422 struct spu_priv2 __iomem *priv2 = spu->priv2; 423 424 /* Save, Step 24: 425 * Save the MFC_CSR_ATO register in 426 * the CSA. 427 */ 428 csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW); 429 } 430 431 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu) 432 { 433 /* Save, Step 25: 434 * Save the MFC_TCLASS_ID register in 435 * the CSA. 436 */ 437 csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu); 438 } 439 440 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu) 441 { 442 /* Save, Step 26: 443 * Restore, Step 23. 444 * Write the MFC_TCLASS_ID register with 445 * the value 0x10000000. 446 */ 447 spu_mfc_tclass_id_set(spu, 0x10000000); 448 eieio(); 449 } 450 451 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu) 452 { 453 struct spu_priv2 __iomem *priv2 = spu->priv2; 454 455 /* Save, Step 27: 456 * Restore, Step 14. 457 * Write MFC_CNTL[Pc]=1 (purge queue). 458 */ 459 out_be64(&priv2->mfc_control_RW, MFC_CNTL_PURGE_DMA_REQUEST); 460 eieio(); 461 } 462 463 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu) 464 { 465 struct spu_priv2 __iomem *priv2 = spu->priv2; 466 467 /* Save, Step 28: 468 * Poll MFC_CNTL[Ps] until value '11' is read 469 * (purge complete). 470 */ 471 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & 472 MFC_CNTL_PURGE_DMA_STATUS_MASK) == 473 MFC_CNTL_PURGE_DMA_COMPLETE); 474 } 475 476 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu) 477 { 478 /* Save, Step 30: 479 * Restore, Step 18: 480 * Write MFC_SR1 with MFC_SR1[D=0,S=1] and 481 * MFC_SR1[TL,R,Pr,T] set correctly for the 482 * OS specific environment. 483 * 484 * Implementation note: The SPU-side code 485 * for save/restore is privileged, so the 486 * MFC_SR1[Pr] bit is not set. 487 * 488 */ 489 spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK | 490 MFC_STATE1_RELOCATE_MASK | 491 MFC_STATE1_BUS_TLBIE_MASK)); 492 } 493 494 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu) 495 { 496 struct spu_problem __iomem *prob = spu->problem; 497 498 /* Save, Step 31: 499 * Save SPU_NPC in the CSA. 500 */ 501 csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW); 502 } 503 504 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu) 505 { 506 struct spu_priv2 __iomem *priv2 = spu->priv2; 507 508 /* Save, Step 32: 509 * Save SPU_PrivCntl in the CSA. 510 */ 511 csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW); 512 } 513 514 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu) 515 { 516 struct spu_priv2 __iomem *priv2 = spu->priv2; 517 518 /* Save, Step 33: 519 * Restore, Step 16: 520 * Write SPU_PrivCntl[S,Le,A] fields reset to 0. 521 */ 522 out_be64(&priv2->spu_privcntl_RW, 0UL); 523 eieio(); 524 } 525 526 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu) 527 { 528 struct spu_priv2 __iomem *priv2 = spu->priv2; 529 530 /* Save, Step 34: 531 * Save SPU_LSLR in the CSA. 532 */ 533 csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW); 534 } 535 536 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu) 537 { 538 struct spu_priv2 __iomem *priv2 = spu->priv2; 539 540 /* Save, Step 35: 541 * Restore, Step 17. 542 * Reset SPU_LSLR. 543 */ 544 out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK); 545 eieio(); 546 } 547 548 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu) 549 { 550 struct spu_priv2 __iomem *priv2 = spu->priv2; 551 552 /* Save, Step 36: 553 * Save SPU_Cfg in the CSA. 554 */ 555 csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW); 556 } 557 558 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu) 559 { 560 /* Save, Step 37: 561 * Save PM_Trace_Tag_Wait_Mask in the CSA. 562 * Not performed by this implementation. 563 */ 564 } 565 566 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu) 567 { 568 /* Save, Step 38: 569 * Save RA_GROUP_ID register and the 570 * RA_ENABLE reigster in the CSA. 571 */ 572 csa->priv1.resource_allocation_groupID_RW = 573 spu_resource_allocation_groupID_get(spu); 574 csa->priv1.resource_allocation_enable_RW = 575 spu_resource_allocation_enable_get(spu); 576 } 577 578 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu) 579 { 580 struct spu_problem __iomem *prob = spu->problem; 581 582 /* Save, Step 39: 583 * Save MB_Stat register in the CSA. 584 */ 585 csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R); 586 } 587 588 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu) 589 { 590 struct spu_problem __iomem *prob = spu->problem; 591 592 /* Save, Step 40: 593 * Save the PPU_MB register in the CSA. 594 */ 595 csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R); 596 } 597 598 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu) 599 { 600 struct spu_priv2 __iomem *priv2 = spu->priv2; 601 602 /* Save, Step 41: 603 * Save the PPUINT_MB register in the CSA. 604 */ 605 csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R); 606 } 607 608 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu) 609 { 610 struct spu_priv2 __iomem *priv2 = spu->priv2; 611 u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL }; 612 int i; 613 614 /* Save, Step 42: 615 */ 616 617 /* Save CH 1, without channel count */ 618 out_be64(&priv2->spu_chnlcntptr_RW, 1); 619 csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW); 620 621 /* Save the following CH: [0,3,4,24,25,27] */ 622 for (i = 0; i < ARRAY_SIZE(ch_indices); i++) { 623 idx = ch_indices[i]; 624 out_be64(&priv2->spu_chnlcntptr_RW, idx); 625 eieio(); 626 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW); 627 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW); 628 out_be64(&priv2->spu_chnldata_RW, 0UL); 629 out_be64(&priv2->spu_chnlcnt_RW, 0UL); 630 eieio(); 631 } 632 } 633 634 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu) 635 { 636 struct spu_priv2 __iomem *priv2 = spu->priv2; 637 int i; 638 639 /* Save, Step 43: 640 * Save SPU Read Mailbox Channel. 641 */ 642 out_be64(&priv2->spu_chnlcntptr_RW, 29UL); 643 eieio(); 644 csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW); 645 for (i = 0; i < 4; i++) { 646 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW); 647 } 648 out_be64(&priv2->spu_chnlcnt_RW, 0UL); 649 eieio(); 650 } 651 652 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu) 653 { 654 struct spu_priv2 __iomem *priv2 = spu->priv2; 655 656 /* Save, Step 44: 657 * Save MFC_CMD Channel. 658 */ 659 out_be64(&priv2->spu_chnlcntptr_RW, 21UL); 660 eieio(); 661 csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW); 662 eieio(); 663 } 664 665 static inline void reset_ch(struct spu_state *csa, struct spu *spu) 666 { 667 struct spu_priv2 __iomem *priv2 = spu->priv2; 668 u64 ch_indices[4] = { 21UL, 23UL, 28UL, 30UL }; 669 u64 ch_counts[4] = { 16UL, 1UL, 1UL, 1UL }; 670 u64 idx; 671 int i; 672 673 /* Save, Step 45: 674 * Reset the following CH: [21, 23, 28, 30] 675 */ 676 for (i = 0; i < 4; i++) { 677 idx = ch_indices[i]; 678 out_be64(&priv2->spu_chnlcntptr_RW, idx); 679 eieio(); 680 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]); 681 eieio(); 682 } 683 } 684 685 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu) 686 { 687 struct spu_priv2 __iomem *priv2 = spu->priv2; 688 689 /* Save, Step 46: 690 * Restore, Step 25. 691 * Write MFC_CNTL[Sc]=0 (resume queue processing). 692 */ 693 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE); 694 } 695 696 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu, 697 unsigned int *code, int code_size) 698 { 699 /* Save, Step 47: 700 * Restore, Step 30. 701 * If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All 702 * register, then initialize SLB_VSID and SLB_ESID 703 * to provide access to SPU context save code and 704 * LSCSA. 705 * 706 * This implementation places both the context 707 * switch code and LSCSA in kernel address space. 708 * 709 * Further this implementation assumes that the 710 * MFC_SR1[R]=1 (in other words, assume that 711 * translation is desired by OS environment). 712 */ 713 spu_invalidate_slbs(spu); 714 spu_setup_kernel_slbs(spu, csa->lscsa, code, code_size); 715 } 716 717 static inline void set_switch_active(struct spu_state *csa, struct spu *spu) 718 { 719 /* Save, Step 48: 720 * Restore, Step 23. 721 * Change the software context switch pending flag 722 * to context switch active. 723 */ 724 set_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags); 725 clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags); 726 mb(); 727 } 728 729 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu) 730 { 731 unsigned long class1_mask = CLASS1_ENABLE_SEGMENT_FAULT_INTR | 732 CLASS1_ENABLE_STORAGE_FAULT_INTR; 733 734 /* Save, Step 49: 735 * Restore, Step 22: 736 * Reset and then enable interrupts, as 737 * needed by OS. 738 * 739 * This implementation enables only class1 740 * (translation) interrupts. 741 */ 742 spin_lock_irq(&spu->register_lock); 743 spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK); 744 spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK); 745 spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK); 746 spu_int_mask_set(spu, 0, 0ul); 747 spu_int_mask_set(spu, 1, class1_mask); 748 spu_int_mask_set(spu, 2, 0ul); 749 spin_unlock_irq(&spu->register_lock); 750 } 751 752 static inline int send_mfc_dma(struct spu *spu, unsigned long ea, 753 unsigned int ls_offset, unsigned int size, 754 unsigned int tag, unsigned int rclass, 755 unsigned int cmd) 756 { 757 struct spu_problem __iomem *prob = spu->problem; 758 union mfc_tag_size_class_cmd command; 759 unsigned int transfer_size; 760 volatile unsigned int status = 0x0; 761 762 while (size > 0) { 763 transfer_size = 764 (size > MFC_MAX_DMA_SIZE) ? MFC_MAX_DMA_SIZE : size; 765 command.u.mfc_size = transfer_size; 766 command.u.mfc_tag = tag; 767 command.u.mfc_rclassid = rclass; 768 command.u.mfc_cmd = cmd; 769 do { 770 out_be32(&prob->mfc_lsa_W, ls_offset); 771 out_be64(&prob->mfc_ea_W, ea); 772 out_be64(&prob->mfc_union_W.all64, command.all64); 773 status = 774 in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32); 775 if (unlikely(status & 0x2)) { 776 cpu_relax(); 777 } 778 } while (status & 0x3); 779 size -= transfer_size; 780 ea += transfer_size; 781 ls_offset += transfer_size; 782 } 783 return 0; 784 } 785 786 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu) 787 { 788 unsigned long addr = (unsigned long)&csa->lscsa->ls[0]; 789 unsigned int ls_offset = 0x0; 790 unsigned int size = 16384; 791 unsigned int tag = 0; 792 unsigned int rclass = 0; 793 unsigned int cmd = MFC_PUT_CMD; 794 795 /* Save, Step 50: 796 * Issue a DMA command to copy the first 16K bytes 797 * of local storage to the CSA. 798 */ 799 send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd); 800 } 801 802 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu) 803 { 804 struct spu_problem __iomem *prob = spu->problem; 805 806 /* Save, Step 51: 807 * Restore, Step 31. 808 * Write SPU_NPC[IE]=0 and SPU_NPC[LSA] to entry 809 * point address of context save code in local 810 * storage. 811 * 812 * This implementation uses SPU-side save/restore 813 * programs with entry points at LSA of 0. 814 */ 815 out_be32(&prob->spu_npc_RW, 0); 816 eieio(); 817 } 818 819 static inline void set_signot1(struct spu_state *csa, struct spu *spu) 820 { 821 struct spu_problem __iomem *prob = spu->problem; 822 union { 823 u64 ull; 824 u32 ui[2]; 825 } addr64; 826 827 /* Save, Step 52: 828 * Restore, Step 32: 829 * Write SPU_Sig_Notify_1 register with upper 32-bits 830 * of the CSA.LSCSA effective address. 831 */ 832 addr64.ull = (u64) csa->lscsa; 833 out_be32(&prob->signal_notify1, addr64.ui[0]); 834 eieio(); 835 } 836 837 static inline void set_signot2(struct spu_state *csa, struct spu *spu) 838 { 839 struct spu_problem __iomem *prob = spu->problem; 840 union { 841 u64 ull; 842 u32 ui[2]; 843 } addr64; 844 845 /* Save, Step 53: 846 * Restore, Step 33: 847 * Write SPU_Sig_Notify_2 register with lower 32-bits 848 * of the CSA.LSCSA effective address. 849 */ 850 addr64.ull = (u64) csa->lscsa; 851 out_be32(&prob->signal_notify2, addr64.ui[1]); 852 eieio(); 853 } 854 855 static inline void send_save_code(struct spu_state *csa, struct spu *spu) 856 { 857 unsigned long addr = (unsigned long)&spu_save_code[0]; 858 unsigned int ls_offset = 0x0; 859 unsigned int size = sizeof(spu_save_code); 860 unsigned int tag = 0; 861 unsigned int rclass = 0; 862 unsigned int cmd = MFC_GETFS_CMD; 863 864 /* Save, Step 54: 865 * Issue a DMA command to copy context save code 866 * to local storage and start SPU. 867 */ 868 send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd); 869 } 870 871 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu) 872 { 873 struct spu_problem __iomem *prob = spu->problem; 874 875 /* Save, Step 55: 876 * Restore, Step 38. 877 * Write PPU_QueryMask=1 (enable Tag Group 0) 878 * and issue eieio instruction. 879 */ 880 out_be32(&prob->dma_querymask_RW, MFC_TAGID_TO_TAGMASK(0)); 881 eieio(); 882 } 883 884 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu) 885 { 886 struct spu_problem __iomem *prob = spu->problem; 887 u32 mask = MFC_TAGID_TO_TAGMASK(0); 888 unsigned long flags; 889 890 /* Save, Step 56: 891 * Restore, Step 39. 892 * Restore, Step 39. 893 * Restore, Step 46. 894 * Poll PPU_TagStatus[gn] until 01 (Tag group 0 complete) 895 * or write PPU_QueryType[TS]=01 and wait for Tag Group 896 * Complete Interrupt. Write INT_Stat_Class0 or 897 * INT_Stat_Class2 with value of 'handled'. 898 */ 899 POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask); 900 901 local_irq_save(flags); 902 spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK); 903 spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK); 904 local_irq_restore(flags); 905 } 906 907 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu) 908 { 909 struct spu_problem __iomem *prob = spu->problem; 910 unsigned long flags; 911 912 /* Save, Step 57: 913 * Restore, Step 40. 914 * Poll until SPU_Status[R]=0 or wait for SPU Class 0 915 * or SPU Class 2 interrupt. Write INT_Stat_class0 916 * or INT_Stat_class2 with value of handled. 917 */ 918 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING); 919 920 local_irq_save(flags); 921 spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK); 922 spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK); 923 local_irq_restore(flags); 924 } 925 926 static inline int check_save_status(struct spu_state *csa, struct spu *spu) 927 { 928 struct spu_problem __iomem *prob = spu->problem; 929 u32 complete; 930 931 /* Save, Step 54: 932 * If SPU_Status[P]=1 and SPU_Status[SC] = "success", 933 * context save succeeded, otherwise context save 934 * failed. 935 */ 936 complete = ((SPU_SAVE_COMPLETE << SPU_STOP_STATUS_SHIFT) | 937 SPU_STATUS_STOPPED_BY_STOP); 938 return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0; 939 } 940 941 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu) 942 { 943 /* Restore, Step 4: 944 * If required, notify the "using application" that 945 * the SPU task has been terminated. TBD. 946 */ 947 } 948 949 static inline void suspend_mfc_and_halt_decr(struct spu_state *csa, 950 struct spu *spu) 951 { 952 struct spu_priv2 __iomem *priv2 = spu->priv2; 953 954 /* Restore, Step 7: 955 * Write MFC_Cntl[Dh,Sc,Sm]='1','1','0' to suspend 956 * the queue and halt the decrementer. 957 */ 958 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE | 959 MFC_CNTL_DECREMENTER_HALTED); 960 eieio(); 961 } 962 963 static inline void wait_suspend_mfc_complete(struct spu_state *csa, 964 struct spu *spu) 965 { 966 struct spu_priv2 __iomem *priv2 = spu->priv2; 967 968 /* Restore, Step 8: 969 * Restore, Step 47. 970 * Poll MFC_CNTL[Ss] until 11 is returned. 971 */ 972 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) & 973 MFC_CNTL_SUSPEND_DMA_STATUS_MASK) == 974 MFC_CNTL_SUSPEND_COMPLETE); 975 } 976 977 static inline int suspend_spe(struct spu_state *csa, struct spu *spu) 978 { 979 struct spu_problem __iomem *prob = spu->problem; 980 981 /* Restore, Step 9: 982 * If SPU_Status[R]=1, stop SPU execution 983 * and wait for stop to complete. 984 * 985 * Returns 1 if SPU_Status[R]=1 on entry. 986 * 0 otherwise 987 */ 988 if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) { 989 if (in_be32(&prob->spu_status_R) & 990 SPU_STATUS_ISOLATED_EXIT_STATUS) { 991 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & 992 SPU_STATUS_RUNNING); 993 } 994 if ((in_be32(&prob->spu_status_R) & 995 SPU_STATUS_ISOLATED_LOAD_STATUS) 996 || (in_be32(&prob->spu_status_R) & 997 SPU_STATUS_ISOLATED_STATE)) { 998 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP); 999 eieio(); 1000 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & 1001 SPU_STATUS_RUNNING); 1002 out_be32(&prob->spu_runcntl_RW, 0x2); 1003 eieio(); 1004 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & 1005 SPU_STATUS_RUNNING); 1006 } 1007 if (in_be32(&prob->spu_status_R) & 1008 SPU_STATUS_WAITING_FOR_CHANNEL) { 1009 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP); 1010 eieio(); 1011 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & 1012 SPU_STATUS_RUNNING); 1013 } 1014 return 1; 1015 } 1016 return 0; 1017 } 1018 1019 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu) 1020 { 1021 struct spu_problem __iomem *prob = spu->problem; 1022 1023 /* Restore, Step 10: 1024 * If SPU_Status[R]=0 and SPU_Status[E,L,IS]=1, 1025 * release SPU from isolate state. 1026 */ 1027 if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) { 1028 if (in_be32(&prob->spu_status_R) & 1029 SPU_STATUS_ISOLATED_EXIT_STATUS) { 1030 spu_mfc_sr1_set(spu, 1031 MFC_STATE1_MASTER_RUN_CONTROL_MASK); 1032 eieio(); 1033 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE); 1034 eieio(); 1035 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & 1036 SPU_STATUS_RUNNING); 1037 } 1038 if ((in_be32(&prob->spu_status_R) & 1039 SPU_STATUS_ISOLATED_LOAD_STATUS) 1040 || (in_be32(&prob->spu_status_R) & 1041 SPU_STATUS_ISOLATED_STATE)) { 1042 spu_mfc_sr1_set(spu, 1043 MFC_STATE1_MASTER_RUN_CONTROL_MASK); 1044 eieio(); 1045 out_be32(&prob->spu_runcntl_RW, 0x2); 1046 eieio(); 1047 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & 1048 SPU_STATUS_RUNNING); 1049 } 1050 } 1051 } 1052 1053 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu) 1054 { 1055 struct spu_priv2 __iomem *priv2 = spu->priv2; 1056 u64 ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL }; 1057 u64 idx; 1058 int i; 1059 1060 /* Restore, Step 20: 1061 */ 1062 1063 /* Reset CH 1 */ 1064 out_be64(&priv2->spu_chnlcntptr_RW, 1); 1065 out_be64(&priv2->spu_chnldata_RW, 0UL); 1066 1067 /* Reset the following CH: [0,3,4,24,25,27] */ 1068 for (i = 0; i < ARRAY_SIZE(ch_indices); i++) { 1069 idx = ch_indices[i]; 1070 out_be64(&priv2->spu_chnlcntptr_RW, idx); 1071 eieio(); 1072 out_be64(&priv2->spu_chnldata_RW, 0UL); 1073 out_be64(&priv2->spu_chnlcnt_RW, 0UL); 1074 eieio(); 1075 } 1076 } 1077 1078 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu) 1079 { 1080 struct spu_priv2 __iomem *priv2 = spu->priv2; 1081 u64 ch_indices[5] = { 21UL, 23UL, 28UL, 29UL, 30UL }; 1082 u64 ch_counts[5] = { 16UL, 1UL, 1UL, 0UL, 1UL }; 1083 u64 idx; 1084 int i; 1085 1086 /* Restore, Step 21: 1087 * Reset the following CH: [21, 23, 28, 29, 30] 1088 */ 1089 for (i = 0; i < 5; i++) { 1090 idx = ch_indices[i]; 1091 out_be64(&priv2->spu_chnlcntptr_RW, idx); 1092 eieio(); 1093 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]); 1094 eieio(); 1095 } 1096 } 1097 1098 static inline void setup_spu_status_part1(struct spu_state *csa, 1099 struct spu *spu) 1100 { 1101 u32 status_P = SPU_STATUS_STOPPED_BY_STOP; 1102 u32 status_I = SPU_STATUS_INVALID_INSTR; 1103 u32 status_H = SPU_STATUS_STOPPED_BY_HALT; 1104 u32 status_S = SPU_STATUS_SINGLE_STEP; 1105 u32 status_S_I = SPU_STATUS_SINGLE_STEP | SPU_STATUS_INVALID_INSTR; 1106 u32 status_S_P = SPU_STATUS_SINGLE_STEP | SPU_STATUS_STOPPED_BY_STOP; 1107 u32 status_P_H = SPU_STATUS_STOPPED_BY_HALT |SPU_STATUS_STOPPED_BY_STOP; 1108 u32 status_P_I = SPU_STATUS_STOPPED_BY_STOP |SPU_STATUS_INVALID_INSTR; 1109 u32 status_code; 1110 1111 /* Restore, Step 27: 1112 * If the CSA.SPU_Status[I,S,H,P]=1 then add the correct 1113 * instruction sequence to the end of the SPU based restore 1114 * code (after the "context restored" stop and signal) to 1115 * restore the correct SPU status. 1116 * 1117 * NOTE: Rather than modifying the SPU executable, we 1118 * instead add a new 'stopped_status' field to the 1119 * LSCSA. The SPU-side restore reads this field and 1120 * takes the appropriate action when exiting. 1121 */ 1122 1123 status_code = 1124 (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF; 1125 if ((csa->prob.spu_status_R & status_P_I) == status_P_I) { 1126 1127 /* SPU_Status[P,I]=1 - Illegal Instruction followed 1128 * by Stop and Signal instruction, followed by 'br -4'. 1129 * 1130 */ 1131 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I; 1132 csa->lscsa->stopped_status.slot[1] = status_code; 1133 1134 } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) { 1135 1136 /* SPU_Status[P,H]=1 - Halt Conditional, followed 1137 * by Stop and Signal instruction, followed by 1138 * 'br -4'. 1139 */ 1140 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H; 1141 csa->lscsa->stopped_status.slot[1] = status_code; 1142 1143 } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) { 1144 1145 /* SPU_Status[S,P]=1 - Stop and Signal instruction 1146 * followed by 'br -4'. 1147 */ 1148 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P; 1149 csa->lscsa->stopped_status.slot[1] = status_code; 1150 1151 } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) { 1152 1153 /* SPU_Status[S,I]=1 - Illegal instruction followed 1154 * by 'br -4'. 1155 */ 1156 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I; 1157 csa->lscsa->stopped_status.slot[1] = status_code; 1158 1159 } else if ((csa->prob.spu_status_R & status_P) == status_P) { 1160 1161 /* SPU_Status[P]=1 - Stop and Signal instruction 1162 * followed by 'br -4'. 1163 */ 1164 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P; 1165 csa->lscsa->stopped_status.slot[1] = status_code; 1166 1167 } else if ((csa->prob.spu_status_R & status_H) == status_H) { 1168 1169 /* SPU_Status[H]=1 - Halt Conditional, followed 1170 * by 'br -4'. 1171 */ 1172 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H; 1173 1174 } else if ((csa->prob.spu_status_R & status_S) == status_S) { 1175 1176 /* SPU_Status[S]=1 - Two nop instructions. 1177 */ 1178 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S; 1179 1180 } else if ((csa->prob.spu_status_R & status_I) == status_I) { 1181 1182 /* SPU_Status[I]=1 - Illegal instruction followed 1183 * by 'br -4'. 1184 */ 1185 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I; 1186 1187 } 1188 } 1189 1190 static inline void setup_spu_status_part2(struct spu_state *csa, 1191 struct spu *spu) 1192 { 1193 u32 mask; 1194 1195 /* Restore, Step 28: 1196 * If the CSA.SPU_Status[I,S,H,P,R]=0 then 1197 * add a 'br *' instruction to the end of 1198 * the SPU based restore code. 1199 * 1200 * NOTE: Rather than modifying the SPU executable, we 1201 * instead add a new 'stopped_status' field to the 1202 * LSCSA. The SPU-side restore reads this field and 1203 * takes the appropriate action when exiting. 1204 */ 1205 mask = SPU_STATUS_INVALID_INSTR | 1206 SPU_STATUS_SINGLE_STEP | 1207 SPU_STATUS_STOPPED_BY_HALT | 1208 SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING; 1209 if (!(csa->prob.spu_status_R & mask)) { 1210 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R; 1211 } 1212 } 1213 1214 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu) 1215 { 1216 /* Restore, Step 29: 1217 * Restore RA_GROUP_ID register and the 1218 * RA_ENABLE reigster from the CSA. 1219 */ 1220 spu_resource_allocation_groupID_set(spu, 1221 csa->priv1.resource_allocation_groupID_RW); 1222 spu_resource_allocation_enable_set(spu, 1223 csa->priv1.resource_allocation_enable_RW); 1224 } 1225 1226 static inline void send_restore_code(struct spu_state *csa, struct spu *spu) 1227 { 1228 unsigned long addr = (unsigned long)&spu_restore_code[0]; 1229 unsigned int ls_offset = 0x0; 1230 unsigned int size = sizeof(spu_restore_code); 1231 unsigned int tag = 0; 1232 unsigned int rclass = 0; 1233 unsigned int cmd = MFC_GETFS_CMD; 1234 1235 /* Restore, Step 37: 1236 * Issue MFC DMA command to copy context 1237 * restore code to local storage. 1238 */ 1239 send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd); 1240 } 1241 1242 static inline void setup_decr(struct spu_state *csa, struct spu *spu) 1243 { 1244 /* Restore, Step 34: 1245 * If CSA.MFC_CNTL[Ds]=1 (decrementer was 1246 * running) then adjust decrementer, set 1247 * decrementer running status in LSCSA, 1248 * and set decrementer "wrapped" status 1249 * in LSCSA. 1250 */ 1251 if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) { 1252 cycles_t resume_time = get_cycles(); 1253 cycles_t delta_time = resume_time - csa->suspend_time; 1254 1255 csa->lscsa->decr_status.slot[0] = SPU_DECR_STATUS_RUNNING; 1256 if (csa->lscsa->decr.slot[0] < delta_time) { 1257 csa->lscsa->decr_status.slot[0] |= 1258 SPU_DECR_STATUS_WRAPPED; 1259 } 1260 1261 csa->lscsa->decr.slot[0] -= delta_time; 1262 } else { 1263 csa->lscsa->decr_status.slot[0] = 0; 1264 } 1265 } 1266 1267 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu) 1268 { 1269 /* Restore, Step 35: 1270 * Copy the CSA.PU_MB data into the LSCSA. 1271 */ 1272 csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R; 1273 } 1274 1275 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu) 1276 { 1277 /* Restore, Step 36: 1278 * Copy the CSA.PUINT_MB data into the LSCSA. 1279 */ 1280 csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R; 1281 } 1282 1283 static inline int check_restore_status(struct spu_state *csa, struct spu *spu) 1284 { 1285 struct spu_problem __iomem *prob = spu->problem; 1286 u32 complete; 1287 1288 /* Restore, Step 40: 1289 * If SPU_Status[P]=1 and SPU_Status[SC] = "success", 1290 * context restore succeeded, otherwise context restore 1291 * failed. 1292 */ 1293 complete = ((SPU_RESTORE_COMPLETE << SPU_STOP_STATUS_SHIFT) | 1294 SPU_STATUS_STOPPED_BY_STOP); 1295 return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0; 1296 } 1297 1298 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu) 1299 { 1300 struct spu_priv2 __iomem *priv2 = spu->priv2; 1301 1302 /* Restore, Step 41: 1303 * Restore SPU_PrivCntl from the CSA. 1304 */ 1305 out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW); 1306 eieio(); 1307 } 1308 1309 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu) 1310 { 1311 struct spu_problem __iomem *prob = spu->problem; 1312 u32 mask; 1313 1314 /* Restore, Step 42: 1315 * If any CSA.SPU_Status[I,S,H,P]=1, then 1316 * restore the error or single step state. 1317 */ 1318 mask = SPU_STATUS_INVALID_INSTR | 1319 SPU_STATUS_SINGLE_STEP | 1320 SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP; 1321 if (csa->prob.spu_status_R & mask) { 1322 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE); 1323 eieio(); 1324 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & 1325 SPU_STATUS_RUNNING); 1326 } 1327 } 1328 1329 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu) 1330 { 1331 struct spu_problem __iomem *prob = spu->problem; 1332 u32 mask; 1333 1334 /* Restore, Step 43: 1335 * If all CSA.SPU_Status[I,S,H,P,R]=0 then write 1336 * SPU_RunCntl[R0R1]='01', wait for SPU_Status[R]=1, 1337 * then write '00' to SPU_RunCntl[R0R1] and wait 1338 * for SPU_Status[R]=0. 1339 */ 1340 mask = SPU_STATUS_INVALID_INSTR | 1341 SPU_STATUS_SINGLE_STEP | 1342 SPU_STATUS_STOPPED_BY_HALT | 1343 SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING; 1344 if (!(csa->prob.spu_status_R & mask)) { 1345 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE); 1346 eieio(); 1347 POLL_WHILE_FALSE(in_be32(&prob->spu_status_R) & 1348 SPU_STATUS_RUNNING); 1349 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP); 1350 eieio(); 1351 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & 1352 SPU_STATUS_RUNNING); 1353 } 1354 } 1355 1356 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu) 1357 { 1358 unsigned long addr = (unsigned long)&csa->lscsa->ls[0]; 1359 unsigned int ls_offset = 0x0; 1360 unsigned int size = 16384; 1361 unsigned int tag = 0; 1362 unsigned int rclass = 0; 1363 unsigned int cmd = MFC_GET_CMD; 1364 1365 /* Restore, Step 44: 1366 * Issue a DMA command to restore the first 1367 * 16kb of local storage from CSA. 1368 */ 1369 send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd); 1370 } 1371 1372 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu) 1373 { 1374 struct spu_priv2 __iomem *priv2 = spu->priv2; 1375 1376 /* Restore, Step 47. 1377 * Write MFC_Cntl[Sc,Sm]='1','0' to suspend 1378 * the queue. 1379 */ 1380 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE); 1381 eieio(); 1382 } 1383 1384 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu) 1385 { 1386 /* Restore, Step 49: 1387 * Write INT_MASK_class0 with value of 0. 1388 * Write INT_MASK_class1 with value of 0. 1389 * Write INT_MASK_class2 with value of 0. 1390 * Write INT_STAT_class0 with value of -1. 1391 * Write INT_STAT_class1 with value of -1. 1392 * Write INT_STAT_class2 with value of -1. 1393 */ 1394 spin_lock_irq(&spu->register_lock); 1395 spu_int_mask_set(spu, 0, 0ul); 1396 spu_int_mask_set(spu, 1, 0ul); 1397 spu_int_mask_set(spu, 2, 0ul); 1398 spu_int_stat_clear(spu, 0, CLASS0_INTR_MASK); 1399 spu_int_stat_clear(spu, 1, CLASS1_INTR_MASK); 1400 spu_int_stat_clear(spu, 2, CLASS2_INTR_MASK); 1401 spin_unlock_irq(&spu->register_lock); 1402 } 1403 1404 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu) 1405 { 1406 struct spu_priv2 __iomem *priv2 = spu->priv2; 1407 int i; 1408 1409 /* Restore, Step 50: 1410 * If MFC_Cntl[Se]!=0 then restore 1411 * MFC command queues. 1412 */ 1413 if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) { 1414 for (i = 0; i < 8; i++) { 1415 out_be64(&priv2->puq[i].mfc_cq_data0_RW, 1416 csa->priv2.puq[i].mfc_cq_data0_RW); 1417 out_be64(&priv2->puq[i].mfc_cq_data1_RW, 1418 csa->priv2.puq[i].mfc_cq_data1_RW); 1419 out_be64(&priv2->puq[i].mfc_cq_data2_RW, 1420 csa->priv2.puq[i].mfc_cq_data2_RW); 1421 out_be64(&priv2->puq[i].mfc_cq_data3_RW, 1422 csa->priv2.puq[i].mfc_cq_data3_RW); 1423 } 1424 for (i = 0; i < 16; i++) { 1425 out_be64(&priv2->spuq[i].mfc_cq_data0_RW, 1426 csa->priv2.spuq[i].mfc_cq_data0_RW); 1427 out_be64(&priv2->spuq[i].mfc_cq_data1_RW, 1428 csa->priv2.spuq[i].mfc_cq_data1_RW); 1429 out_be64(&priv2->spuq[i].mfc_cq_data2_RW, 1430 csa->priv2.spuq[i].mfc_cq_data2_RW); 1431 out_be64(&priv2->spuq[i].mfc_cq_data3_RW, 1432 csa->priv2.spuq[i].mfc_cq_data3_RW); 1433 } 1434 } 1435 eieio(); 1436 } 1437 1438 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu) 1439 { 1440 struct spu_problem __iomem *prob = spu->problem; 1441 1442 /* Restore, Step 51: 1443 * Restore the PPU_QueryMask register from CSA. 1444 */ 1445 out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW); 1446 eieio(); 1447 } 1448 1449 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu) 1450 { 1451 struct spu_problem __iomem *prob = spu->problem; 1452 1453 /* Restore, Step 52: 1454 * Restore the PPU_QueryType register from CSA. 1455 */ 1456 out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW); 1457 eieio(); 1458 } 1459 1460 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu) 1461 { 1462 struct spu_priv2 __iomem *priv2 = spu->priv2; 1463 1464 /* Restore, Step 53: 1465 * Restore the MFC_CSR_TSQ register from CSA. 1466 */ 1467 out_be64(&priv2->spu_tag_status_query_RW, 1468 csa->priv2.spu_tag_status_query_RW); 1469 eieio(); 1470 } 1471 1472 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu) 1473 { 1474 struct spu_priv2 __iomem *priv2 = spu->priv2; 1475 1476 /* Restore, Step 54: 1477 * Restore the MFC_CSR_CMD1 and MFC_CSR_CMD2 1478 * registers from CSA. 1479 */ 1480 out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW); 1481 out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW); 1482 eieio(); 1483 } 1484 1485 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu) 1486 { 1487 struct spu_priv2 __iomem *priv2 = spu->priv2; 1488 1489 /* Restore, Step 55: 1490 * Restore the MFC_CSR_ATO register from CSA. 1491 */ 1492 out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW); 1493 } 1494 1495 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu) 1496 { 1497 /* Restore, Step 56: 1498 * Restore the MFC_TCLASS_ID register from CSA. 1499 */ 1500 spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW); 1501 eieio(); 1502 } 1503 1504 static inline void set_llr_event(struct spu_state *csa, struct spu *spu) 1505 { 1506 u64 ch0_cnt, ch0_data; 1507 u64 ch1_data; 1508 1509 /* Restore, Step 57: 1510 * Set the Lock Line Reservation Lost Event by: 1511 * 1. OR CSA.SPU_Event_Status with bit 21 (Lr) set to 1. 1512 * 2. If CSA.SPU_Channel_0_Count=0 and 1513 * CSA.SPU_Wr_Event_Mask[Lr]=1 and 1514 * CSA.SPU_Event_Status[Lr]=0 then set 1515 * CSA.SPU_Event_Status_Count=1. 1516 */ 1517 ch0_cnt = csa->spu_chnlcnt_RW[0]; 1518 ch0_data = csa->spu_chnldata_RW[0]; 1519 ch1_data = csa->spu_chnldata_RW[1]; 1520 csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT; 1521 if ((ch0_cnt == 0) && !(ch0_data & MFC_LLR_LOST_EVENT) && 1522 (ch1_data & MFC_LLR_LOST_EVENT)) { 1523 csa->spu_chnlcnt_RW[0] = 1; 1524 } 1525 } 1526 1527 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu) 1528 { 1529 /* Restore, Step 58: 1530 * If the status of the CSA software decrementer 1531 * "wrapped" flag is set, OR in a '1' to 1532 * CSA.SPU_Event_Status[Tm]. 1533 */ 1534 if (!(csa->lscsa->decr_status.slot[0] & SPU_DECR_STATUS_WRAPPED)) 1535 return; 1536 1537 if ((csa->spu_chnlcnt_RW[0] == 0) && 1538 (csa->spu_chnldata_RW[1] & 0x20) && 1539 !(csa->spu_chnldata_RW[0] & 0x20)) 1540 csa->spu_chnlcnt_RW[0] = 1; 1541 1542 csa->spu_chnldata_RW[0] |= 0x20; 1543 } 1544 1545 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu) 1546 { 1547 struct spu_priv2 __iomem *priv2 = spu->priv2; 1548 u64 idx, ch_indices[] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL }; 1549 int i; 1550 1551 /* Restore, Step 59: 1552 * Restore the following CH: [0,3,4,24,25,27] 1553 */ 1554 for (i = 0; i < ARRAY_SIZE(ch_indices); i++) { 1555 idx = ch_indices[i]; 1556 out_be64(&priv2->spu_chnlcntptr_RW, idx); 1557 eieio(); 1558 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]); 1559 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]); 1560 eieio(); 1561 } 1562 } 1563 1564 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu) 1565 { 1566 struct spu_priv2 __iomem *priv2 = spu->priv2; 1567 u64 ch_indices[3] = { 9UL, 21UL, 23UL }; 1568 u64 ch_counts[3] = { 1UL, 16UL, 1UL }; 1569 u64 idx; 1570 int i; 1571 1572 /* Restore, Step 60: 1573 * Restore the following CH: [9,21,23]. 1574 */ 1575 ch_counts[0] = 1UL; 1576 ch_counts[1] = csa->spu_chnlcnt_RW[21]; 1577 ch_counts[2] = 1UL; 1578 for (i = 0; i < 3; i++) { 1579 idx = ch_indices[i]; 1580 out_be64(&priv2->spu_chnlcntptr_RW, idx); 1581 eieio(); 1582 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]); 1583 eieio(); 1584 } 1585 } 1586 1587 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu) 1588 { 1589 struct spu_priv2 __iomem *priv2 = spu->priv2; 1590 1591 /* Restore, Step 61: 1592 * Restore the SPU_LSLR register from CSA. 1593 */ 1594 out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW); 1595 eieio(); 1596 } 1597 1598 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu) 1599 { 1600 struct spu_priv2 __iomem *priv2 = spu->priv2; 1601 1602 /* Restore, Step 62: 1603 * Restore the SPU_Cfg register from CSA. 1604 */ 1605 out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW); 1606 eieio(); 1607 } 1608 1609 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu) 1610 { 1611 /* Restore, Step 63: 1612 * Restore PM_Trace_Tag_Wait_Mask from CSA. 1613 * Not performed by this implementation. 1614 */ 1615 } 1616 1617 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu) 1618 { 1619 struct spu_problem __iomem *prob = spu->problem; 1620 1621 /* Restore, Step 64: 1622 * Restore SPU_NPC from CSA. 1623 */ 1624 out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW); 1625 eieio(); 1626 } 1627 1628 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu) 1629 { 1630 struct spu_priv2 __iomem *priv2 = spu->priv2; 1631 int i; 1632 1633 /* Restore, Step 65: 1634 * Restore MFC_RdSPU_MB from CSA. 1635 */ 1636 out_be64(&priv2->spu_chnlcntptr_RW, 29UL); 1637 eieio(); 1638 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]); 1639 for (i = 0; i < 4; i++) { 1640 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]); 1641 } 1642 eieio(); 1643 } 1644 1645 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu) 1646 { 1647 struct spu_problem __iomem *prob = spu->problem; 1648 u32 dummy = 0; 1649 1650 /* Restore, Step 66: 1651 * If CSA.MB_Stat[P]=0 (mailbox empty) then 1652 * read from the PPU_MB register. 1653 */ 1654 if ((csa->prob.mb_stat_R & 0xFF) == 0) { 1655 dummy = in_be32(&prob->pu_mb_R); 1656 eieio(); 1657 } 1658 } 1659 1660 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu) 1661 { 1662 struct spu_priv2 __iomem *priv2 = spu->priv2; 1663 u64 dummy = 0UL; 1664 1665 /* Restore, Step 66: 1666 * If CSA.MB_Stat[I]=0 (mailbox empty) then 1667 * read from the PPUINT_MB register. 1668 */ 1669 if ((csa->prob.mb_stat_R & 0xFF0000) == 0) { 1670 dummy = in_be64(&priv2->puint_mb_R); 1671 eieio(); 1672 spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR); 1673 eieio(); 1674 } 1675 } 1676 1677 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu) 1678 { 1679 /* Restore, Step 69: 1680 * Restore the MFC_SR1 register from CSA. 1681 */ 1682 spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW); 1683 eieio(); 1684 } 1685 1686 static inline void restore_other_spu_access(struct spu_state *csa, 1687 struct spu *spu) 1688 { 1689 /* Restore, Step 70: 1690 * Restore other SPU mappings to this SPU. TBD. 1691 */ 1692 } 1693 1694 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu) 1695 { 1696 struct spu_problem __iomem *prob = spu->problem; 1697 1698 /* Restore, Step 71: 1699 * If CSA.SPU_Status[R]=1 then write 1700 * SPU_RunCntl[R0R1]='01'. 1701 */ 1702 if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) { 1703 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE); 1704 eieio(); 1705 } 1706 } 1707 1708 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu) 1709 { 1710 struct spu_priv2 __iomem *priv2 = spu->priv2; 1711 1712 /* Restore, Step 72: 1713 * Restore the MFC_CNTL register for the CSA. 1714 */ 1715 out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW); 1716 eieio(); 1717 /* 1718 * FIXME: this is to restart a DMA that we were processing 1719 * before the save. better remember the fault information 1720 * in the csa instead. 1721 */ 1722 if ((csa->priv2.mfc_control_RW & MFC_CNTL_SUSPEND_DMA_QUEUE_MASK)) { 1723 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND); 1724 eieio(); 1725 } 1726 } 1727 1728 static inline void enable_user_access(struct spu_state *csa, struct spu *spu) 1729 { 1730 /* Restore, Step 73: 1731 * Enable user-space access (if provided) to this 1732 * SPU by mapping the virtual pages assigned to 1733 * the SPU memory-mapped I/O (MMIO) for problem 1734 * state. TBD. 1735 */ 1736 } 1737 1738 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu) 1739 { 1740 /* Restore, Step 74: 1741 * Reset the "context switch active" flag. 1742 */ 1743 clear_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags); 1744 mb(); 1745 } 1746 1747 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu) 1748 { 1749 /* Restore, Step 75: 1750 * Re-enable SPU interrupts. 1751 */ 1752 spin_lock_irq(&spu->register_lock); 1753 spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW); 1754 spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW); 1755 spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW); 1756 spin_unlock_irq(&spu->register_lock); 1757 } 1758 1759 static int quiece_spu(struct spu_state *prev, struct spu *spu) 1760 { 1761 /* 1762 * Combined steps 2-18 of SPU context save sequence, which 1763 * quiesce the SPU state (disable SPU execution, MFC command 1764 * queues, decrementer, SPU interrupts, etc.). 1765 * 1766 * Returns 0 on success. 1767 * 2 if failed step 2. 1768 * 6 if failed step 6. 1769 */ 1770 1771 if (check_spu_isolate(prev, spu)) { /* Step 2. */ 1772 return 2; 1773 } 1774 disable_interrupts(prev, spu); /* Step 3. */ 1775 set_watchdog_timer(prev, spu); /* Step 4. */ 1776 inhibit_user_access(prev, spu); /* Step 5. */ 1777 if (check_spu_isolate(prev, spu)) { /* Step 6. */ 1778 return 6; 1779 } 1780 set_switch_pending(prev, spu); /* Step 7. */ 1781 save_mfc_cntl(prev, spu); /* Step 8. */ 1782 save_spu_runcntl(prev, spu); /* Step 9. */ 1783 save_mfc_sr1(prev, spu); /* Step 10. */ 1784 save_spu_status(prev, spu); /* Step 11. */ 1785 save_mfc_decr(prev, spu); /* Step 12. */ 1786 halt_mfc_decr(prev, spu); /* Step 13. */ 1787 save_timebase(prev, spu); /* Step 14. */ 1788 remove_other_spu_access(prev, spu); /* Step 15. */ 1789 do_mfc_mssync(prev, spu); /* Step 16. */ 1790 issue_mfc_tlbie(prev, spu); /* Step 17. */ 1791 handle_pending_interrupts(prev, spu); /* Step 18. */ 1792 1793 return 0; 1794 } 1795 1796 static void save_csa(struct spu_state *prev, struct spu *spu) 1797 { 1798 /* 1799 * Combine steps 19-44 of SPU context save sequence, which 1800 * save regions of the privileged & problem state areas. 1801 */ 1802 1803 save_mfc_queues(prev, spu); /* Step 19. */ 1804 save_ppu_querymask(prev, spu); /* Step 20. */ 1805 save_ppu_querytype(prev, spu); /* Step 21. */ 1806 save_ppu_tagstatus(prev, spu); /* NEW. */ 1807 save_mfc_csr_tsq(prev, spu); /* Step 22. */ 1808 save_mfc_csr_cmd(prev, spu); /* Step 23. */ 1809 save_mfc_csr_ato(prev, spu); /* Step 24. */ 1810 save_mfc_tclass_id(prev, spu); /* Step 25. */ 1811 set_mfc_tclass_id(prev, spu); /* Step 26. */ 1812 purge_mfc_queue(prev, spu); /* Step 27. */ 1813 wait_purge_complete(prev, spu); /* Step 28. */ 1814 setup_mfc_sr1(prev, spu); /* Step 30. */ 1815 save_spu_npc(prev, spu); /* Step 31. */ 1816 save_spu_privcntl(prev, spu); /* Step 32. */ 1817 reset_spu_privcntl(prev, spu); /* Step 33. */ 1818 save_spu_lslr(prev, spu); /* Step 34. */ 1819 reset_spu_lslr(prev, spu); /* Step 35. */ 1820 save_spu_cfg(prev, spu); /* Step 36. */ 1821 save_pm_trace(prev, spu); /* Step 37. */ 1822 save_mfc_rag(prev, spu); /* Step 38. */ 1823 save_ppu_mb_stat(prev, spu); /* Step 39. */ 1824 save_ppu_mb(prev, spu); /* Step 40. */ 1825 save_ppuint_mb(prev, spu); /* Step 41. */ 1826 save_ch_part1(prev, spu); /* Step 42. */ 1827 save_spu_mb(prev, spu); /* Step 43. */ 1828 save_mfc_cmd(prev, spu); /* Step 44. */ 1829 reset_ch(prev, spu); /* Step 45. */ 1830 } 1831 1832 static void save_lscsa(struct spu_state *prev, struct spu *spu) 1833 { 1834 /* 1835 * Perform steps 46-57 of SPU context save sequence, 1836 * which save regions of the local store and register 1837 * file. 1838 */ 1839 1840 resume_mfc_queue(prev, spu); /* Step 46. */ 1841 /* Step 47. */ 1842 setup_mfc_slbs(prev, spu, spu_save_code, sizeof(spu_save_code)); 1843 set_switch_active(prev, spu); /* Step 48. */ 1844 enable_interrupts(prev, spu); /* Step 49. */ 1845 save_ls_16kb(prev, spu); /* Step 50. */ 1846 set_spu_npc(prev, spu); /* Step 51. */ 1847 set_signot1(prev, spu); /* Step 52. */ 1848 set_signot2(prev, spu); /* Step 53. */ 1849 send_save_code(prev, spu); /* Step 54. */ 1850 set_ppu_querymask(prev, spu); /* Step 55. */ 1851 wait_tag_complete(prev, spu); /* Step 56. */ 1852 wait_spu_stopped(prev, spu); /* Step 57. */ 1853 } 1854 1855 static void force_spu_isolate_exit(struct spu *spu) 1856 { 1857 struct spu_problem __iomem *prob = spu->problem; 1858 struct spu_priv2 __iomem *priv2 = spu->priv2; 1859 1860 /* Stop SPE execution and wait for completion. */ 1861 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP); 1862 iobarrier_rw(); 1863 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING); 1864 1865 /* Restart SPE master runcntl. */ 1866 spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK); 1867 iobarrier_w(); 1868 1869 /* Initiate isolate exit request and wait for completion. */ 1870 out_be64(&priv2->spu_privcntl_RW, 4LL); 1871 iobarrier_w(); 1872 out_be32(&prob->spu_runcntl_RW, 2); 1873 iobarrier_rw(); 1874 POLL_WHILE_FALSE((in_be32(&prob->spu_status_R) 1875 & SPU_STATUS_STOPPED_BY_STOP)); 1876 1877 /* Reset load request to normal. */ 1878 out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL); 1879 iobarrier_w(); 1880 } 1881 1882 /** 1883 * stop_spu_isolate 1884 * Check SPU run-control state and force isolated 1885 * exit function as necessary. 1886 */ 1887 static void stop_spu_isolate(struct spu *spu) 1888 { 1889 struct spu_problem __iomem *prob = spu->problem; 1890 1891 if (in_be32(&prob->spu_status_R) & SPU_STATUS_ISOLATED_STATE) { 1892 /* The SPU is in isolated state; the only way 1893 * to get it out is to perform an isolated 1894 * exit (clean) operation. 1895 */ 1896 force_spu_isolate_exit(spu); 1897 } 1898 } 1899 1900 static void harvest(struct spu_state *prev, struct spu *spu) 1901 { 1902 /* 1903 * Perform steps 2-25 of SPU context restore sequence, 1904 * which resets an SPU either after a failed save, or 1905 * when using SPU for first time. 1906 */ 1907 1908 disable_interrupts(prev, spu); /* Step 2. */ 1909 inhibit_user_access(prev, spu); /* Step 3. */ 1910 terminate_spu_app(prev, spu); /* Step 4. */ 1911 set_switch_pending(prev, spu); /* Step 5. */ 1912 stop_spu_isolate(spu); /* NEW. */ 1913 remove_other_spu_access(prev, spu); /* Step 6. */ 1914 suspend_mfc_and_halt_decr(prev, spu); /* Step 7. */ 1915 wait_suspend_mfc_complete(prev, spu); /* Step 8. */ 1916 if (!suspend_spe(prev, spu)) /* Step 9. */ 1917 clear_spu_status(prev, spu); /* Step 10. */ 1918 do_mfc_mssync(prev, spu); /* Step 11. */ 1919 issue_mfc_tlbie(prev, spu); /* Step 12. */ 1920 handle_pending_interrupts(prev, spu); /* Step 13. */ 1921 purge_mfc_queue(prev, spu); /* Step 14. */ 1922 wait_purge_complete(prev, spu); /* Step 15. */ 1923 reset_spu_privcntl(prev, spu); /* Step 16. */ 1924 reset_spu_lslr(prev, spu); /* Step 17. */ 1925 setup_mfc_sr1(prev, spu); /* Step 18. */ 1926 spu_invalidate_slbs(spu); /* Step 19. */ 1927 reset_ch_part1(prev, spu); /* Step 20. */ 1928 reset_ch_part2(prev, spu); /* Step 21. */ 1929 enable_interrupts(prev, spu); /* Step 22. */ 1930 set_switch_active(prev, spu); /* Step 23. */ 1931 set_mfc_tclass_id(prev, spu); /* Step 24. */ 1932 resume_mfc_queue(prev, spu); /* Step 25. */ 1933 } 1934 1935 static void restore_lscsa(struct spu_state *next, struct spu *spu) 1936 { 1937 /* 1938 * Perform steps 26-40 of SPU context restore sequence, 1939 * which restores regions of the local store and register 1940 * file. 1941 */ 1942 1943 set_watchdog_timer(next, spu); /* Step 26. */ 1944 setup_spu_status_part1(next, spu); /* Step 27. */ 1945 setup_spu_status_part2(next, spu); /* Step 28. */ 1946 restore_mfc_rag(next, spu); /* Step 29. */ 1947 /* Step 30. */ 1948 setup_mfc_slbs(next, spu, spu_restore_code, sizeof(spu_restore_code)); 1949 set_spu_npc(next, spu); /* Step 31. */ 1950 set_signot1(next, spu); /* Step 32. */ 1951 set_signot2(next, spu); /* Step 33. */ 1952 setup_decr(next, spu); /* Step 34. */ 1953 setup_ppu_mb(next, spu); /* Step 35. */ 1954 setup_ppuint_mb(next, spu); /* Step 36. */ 1955 send_restore_code(next, spu); /* Step 37. */ 1956 set_ppu_querymask(next, spu); /* Step 38. */ 1957 wait_tag_complete(next, spu); /* Step 39. */ 1958 wait_spu_stopped(next, spu); /* Step 40. */ 1959 } 1960 1961 static void restore_csa(struct spu_state *next, struct spu *spu) 1962 { 1963 /* 1964 * Combine steps 41-76 of SPU context restore sequence, which 1965 * restore regions of the privileged & problem state areas. 1966 */ 1967 1968 restore_spu_privcntl(next, spu); /* Step 41. */ 1969 restore_status_part1(next, spu); /* Step 42. */ 1970 restore_status_part2(next, spu); /* Step 43. */ 1971 restore_ls_16kb(next, spu); /* Step 44. */ 1972 wait_tag_complete(next, spu); /* Step 45. */ 1973 suspend_mfc(next, spu); /* Step 46. */ 1974 wait_suspend_mfc_complete(next, spu); /* Step 47. */ 1975 issue_mfc_tlbie(next, spu); /* Step 48. */ 1976 clear_interrupts(next, spu); /* Step 49. */ 1977 restore_mfc_queues(next, spu); /* Step 50. */ 1978 restore_ppu_querymask(next, spu); /* Step 51. */ 1979 restore_ppu_querytype(next, spu); /* Step 52. */ 1980 restore_mfc_csr_tsq(next, spu); /* Step 53. */ 1981 restore_mfc_csr_cmd(next, spu); /* Step 54. */ 1982 restore_mfc_csr_ato(next, spu); /* Step 55. */ 1983 restore_mfc_tclass_id(next, spu); /* Step 56. */ 1984 set_llr_event(next, spu); /* Step 57. */ 1985 restore_decr_wrapped(next, spu); /* Step 58. */ 1986 restore_ch_part1(next, spu); /* Step 59. */ 1987 restore_ch_part2(next, spu); /* Step 60. */ 1988 restore_spu_lslr(next, spu); /* Step 61. */ 1989 restore_spu_cfg(next, spu); /* Step 62. */ 1990 restore_pm_trace(next, spu); /* Step 63. */ 1991 restore_spu_npc(next, spu); /* Step 64. */ 1992 restore_spu_mb(next, spu); /* Step 65. */ 1993 check_ppu_mb_stat(next, spu); /* Step 66. */ 1994 check_ppuint_mb_stat(next, spu); /* Step 67. */ 1995 spu_invalidate_slbs(spu); /* Modified Step 68. */ 1996 restore_mfc_sr1(next, spu); /* Step 69. */ 1997 restore_other_spu_access(next, spu); /* Step 70. */ 1998 restore_spu_runcntl(next, spu); /* Step 71. */ 1999 restore_mfc_cntl(next, spu); /* Step 72. */ 2000 enable_user_access(next, spu); /* Step 73. */ 2001 reset_switch_active(next, spu); /* Step 74. */ 2002 reenable_interrupts(next, spu); /* Step 75. */ 2003 } 2004 2005 static int __do_spu_save(struct spu_state *prev, struct spu *spu) 2006 { 2007 int rc; 2008 2009 /* 2010 * SPU context save can be broken into three phases: 2011 * 2012 * (a) quiesce [steps 2-16]. 2013 * (b) save of CSA, performed by PPE [steps 17-42] 2014 * (c) save of LSCSA, mostly performed by SPU [steps 43-52]. 2015 * 2016 * Returns 0 on success. 2017 * 2,6 if failed to quiece SPU 2018 * 53 if SPU-side of save failed. 2019 */ 2020 2021 rc = quiece_spu(prev, spu); /* Steps 2-16. */ 2022 switch (rc) { 2023 default: 2024 case 2: 2025 case 6: 2026 harvest(prev, spu); 2027 return rc; 2028 break; 2029 case 0: 2030 break; 2031 } 2032 save_csa(prev, spu); /* Steps 17-43. */ 2033 save_lscsa(prev, spu); /* Steps 44-53. */ 2034 return check_save_status(prev, spu); /* Step 54. */ 2035 } 2036 2037 static int __do_spu_restore(struct spu_state *next, struct spu *spu) 2038 { 2039 int rc; 2040 2041 /* 2042 * SPU context restore can be broken into three phases: 2043 * 2044 * (a) harvest (or reset) SPU [steps 2-24]. 2045 * (b) restore LSCSA [steps 25-40], mostly performed by SPU. 2046 * (c) restore CSA [steps 41-76], performed by PPE. 2047 * 2048 * The 'harvest' step is not performed here, but rather 2049 * as needed below. 2050 */ 2051 2052 restore_lscsa(next, spu); /* Steps 24-39. */ 2053 rc = check_restore_status(next, spu); /* Step 40. */ 2054 switch (rc) { 2055 default: 2056 /* Failed. Return now. */ 2057 return rc; 2058 break; 2059 case 0: 2060 /* Fall through to next step. */ 2061 break; 2062 } 2063 restore_csa(next, spu); 2064 2065 return 0; 2066 } 2067 2068 /** 2069 * spu_save - SPU context save, with locking. 2070 * @prev: pointer to SPU context save area, to be saved. 2071 * @spu: pointer to SPU iomem structure. 2072 * 2073 * Acquire locks, perform the save operation then return. 2074 */ 2075 int spu_save(struct spu_state *prev, struct spu *spu) 2076 { 2077 int rc; 2078 2079 acquire_spu_lock(spu); /* Step 1. */ 2080 rc = __do_spu_save(prev, spu); /* Steps 2-53. */ 2081 release_spu_lock(spu); 2082 if (rc != 0 && rc != 2 && rc != 6) { 2083 panic("%s failed on SPU[%d], rc=%d.\n", 2084 __func__, spu->number, rc); 2085 } 2086 return 0; 2087 } 2088 EXPORT_SYMBOL_GPL(spu_save); 2089 2090 /** 2091 * spu_restore - SPU context restore, with harvest and locking. 2092 * @new: pointer to SPU context save area, to be restored. 2093 * @spu: pointer to SPU iomem structure. 2094 * 2095 * Perform harvest + restore, as we may not be coming 2096 * from a previous successful save operation, and the 2097 * hardware state is unknown. 2098 */ 2099 int spu_restore(struct spu_state *new, struct spu *spu) 2100 { 2101 int rc; 2102 2103 acquire_spu_lock(spu); 2104 harvest(NULL, spu); 2105 spu->slb_replace = 0; 2106 rc = __do_spu_restore(new, spu); 2107 release_spu_lock(spu); 2108 if (rc) { 2109 panic("%s failed on SPU[%d] rc=%d.\n", 2110 __func__, spu->number, rc); 2111 } 2112 return rc; 2113 } 2114 EXPORT_SYMBOL_GPL(spu_restore); 2115 2116 static void init_prob(struct spu_state *csa) 2117 { 2118 csa->spu_chnlcnt_RW[9] = 1; 2119 csa->spu_chnlcnt_RW[21] = 16; 2120 csa->spu_chnlcnt_RW[23] = 1; 2121 csa->spu_chnlcnt_RW[28] = 1; 2122 csa->spu_chnlcnt_RW[30] = 1; 2123 csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP; 2124 csa->prob.mb_stat_R = 0x000400; 2125 } 2126 2127 static void init_priv1(struct spu_state *csa) 2128 { 2129 /* Enable decode, relocate, tlbie response, master runcntl. */ 2130 csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK | 2131 MFC_STATE1_MASTER_RUN_CONTROL_MASK | 2132 MFC_STATE1_PROBLEM_STATE_MASK | 2133 MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK; 2134 2135 /* Enable OS-specific set of interrupts. */ 2136 csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR | 2137 CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR | 2138 CLASS0_ENABLE_SPU_ERROR_INTR; 2139 csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR | 2140 CLASS1_ENABLE_STORAGE_FAULT_INTR; 2141 csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR | 2142 CLASS2_ENABLE_SPU_HALT_INTR | 2143 CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR; 2144 } 2145 2146 static void init_priv2(struct spu_state *csa) 2147 { 2148 csa->priv2.spu_lslr_RW = LS_ADDR_MASK; 2149 csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE | 2150 MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION | 2151 MFC_CNTL_DMA_QUEUES_EMPTY_MASK; 2152 } 2153 2154 /** 2155 * spu_alloc_csa - allocate and initialize an SPU context save area. 2156 * 2157 * Allocate and initialize the contents of an SPU context save area. 2158 * This includes enabling address translation, interrupt masks, etc., 2159 * as appropriate for the given OS environment. 2160 * 2161 * Note that storage for the 'lscsa' is allocated separately, 2162 * as it is by far the largest of the context save regions, 2163 * and may need to be pinned or otherwise specially aligned. 2164 */ 2165 int spu_init_csa(struct spu_state *csa) 2166 { 2167 int rc; 2168 2169 if (!csa) 2170 return -EINVAL; 2171 memset(csa, 0, sizeof(struct spu_state)); 2172 2173 rc = spu_alloc_lscsa(csa); 2174 if (rc) 2175 return rc; 2176 2177 spin_lock_init(&csa->register_lock); 2178 2179 init_prob(csa); 2180 init_priv1(csa); 2181 init_priv2(csa); 2182 2183 return 0; 2184 } 2185 2186 void spu_fini_csa(struct spu_state *csa) 2187 { 2188 spu_free_lscsa(csa); 2189 } 2190