1 /* hw_ops.c - query/set operations on active SPU context.
2  *
3  * Copyright (C) IBM 2005
4  * Author: Mark Nutter <mnutter@us.ibm.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19  */
20 
21 #include <linux/module.h>
22 #include <linux/errno.h>
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/poll.h>
27 #include <linux/smp.h>
28 #include <linux/smp_lock.h>
29 #include <linux/stddef.h>
30 #include <linux/unistd.h>
31 
32 #include <asm/io.h>
33 #include <asm/spu.h>
34 #include <asm/spu_priv1.h>
35 #include <asm/spu_csa.h>
36 #include <asm/mmu_context.h>
37 #include "spufs.h"
38 
39 static int spu_hw_mbox_read(struct spu_context *ctx, u32 * data)
40 {
41 	struct spu *spu = ctx->spu;
42 	struct spu_problem __iomem *prob = spu->problem;
43 	u32 mbox_stat;
44 	int ret = 0;
45 
46 	spin_lock_irq(&spu->register_lock);
47 	mbox_stat = in_be32(&prob->mb_stat_R);
48 	if (mbox_stat & 0x0000ff) {
49 		*data = in_be32(&prob->pu_mb_R);
50 		ret = 4;
51 	}
52 	spin_unlock_irq(&spu->register_lock);
53 	return ret;
54 }
55 
56 static u32 spu_hw_mbox_stat_read(struct spu_context *ctx)
57 {
58 	return in_be32(&ctx->spu->problem->mb_stat_R);
59 }
60 
61 static unsigned int spu_hw_mbox_stat_poll(struct spu_context *ctx,
62 					  unsigned int events)
63 {
64 	struct spu *spu = ctx->spu;
65 	int ret = 0;
66 	u32 stat;
67 
68 	spin_lock_irq(&spu->register_lock);
69 	stat = in_be32(&spu->problem->mb_stat_R);
70 
71 	/* if the requested event is there, return the poll
72 	   mask, otherwise enable the interrupt to get notified,
73 	   but first mark any pending interrupts as done so
74 	   we don't get woken up unnecessarily */
75 
76 	if (events & (POLLIN | POLLRDNORM)) {
77 		if (stat & 0xff0000)
78 			ret |= POLLIN | POLLRDNORM;
79 		else {
80 			spu_int_stat_clear(spu, 2, 0x1);
81 			spu_int_mask_or(spu, 2, 0x1);
82 		}
83 	}
84 	if (events & (POLLOUT | POLLWRNORM)) {
85 		if (stat & 0x00ff00)
86 			ret = POLLOUT | POLLWRNORM;
87 		else {
88 			spu_int_stat_clear(spu, 2, 0x10);
89 			spu_int_mask_or(spu, 2, 0x10);
90 		}
91 	}
92 	spin_unlock_irq(&spu->register_lock);
93 	return ret;
94 }
95 
96 static int spu_hw_ibox_read(struct spu_context *ctx, u32 * data)
97 {
98 	struct spu *spu = ctx->spu;
99 	struct spu_problem __iomem *prob = spu->problem;
100 	struct spu_priv2 __iomem *priv2 = spu->priv2;
101 	int ret;
102 
103 	spin_lock_irq(&spu->register_lock);
104 	if (in_be32(&prob->mb_stat_R) & 0xff0000) {
105 		/* read the first available word */
106 		*data = in_be64(&priv2->puint_mb_R);
107 		ret = 4;
108 	} else {
109 		/* make sure we get woken up by the interrupt */
110 		spu_int_mask_or(spu, 2, 0x1);
111 		ret = 0;
112 	}
113 	spin_unlock_irq(&spu->register_lock);
114 	return ret;
115 }
116 
117 static int spu_hw_wbox_write(struct spu_context *ctx, u32 data)
118 {
119 	struct spu *spu = ctx->spu;
120 	struct spu_problem __iomem *prob = spu->problem;
121 	int ret;
122 
123 	spin_lock_irq(&spu->register_lock);
124 	if (in_be32(&prob->mb_stat_R) & 0x00ff00) {
125 		/* we have space to write wbox_data to */
126 		out_be32(&prob->spu_mb_W, data);
127 		ret = 4;
128 	} else {
129 		/* make sure we get woken up by the interrupt when space
130 		   becomes available */
131 		spu_int_mask_or(spu, 2, 0x10);
132 		ret = 0;
133 	}
134 	spin_unlock_irq(&spu->register_lock);
135 	return ret;
136 }
137 
138 static void spu_hw_signal1_write(struct spu_context *ctx, u32 data)
139 {
140 	out_be32(&ctx->spu->problem->signal_notify1, data);
141 }
142 
143 static void spu_hw_signal2_write(struct spu_context *ctx, u32 data)
144 {
145 	out_be32(&ctx->spu->problem->signal_notify2, data);
146 }
147 
148 static void spu_hw_signal1_type_set(struct spu_context *ctx, u64 val)
149 {
150 	struct spu *spu = ctx->spu;
151 	struct spu_priv2 __iomem *priv2 = spu->priv2;
152 	u64 tmp;
153 
154 	spin_lock_irq(&spu->register_lock);
155 	tmp = in_be64(&priv2->spu_cfg_RW);
156 	if (val)
157 		tmp |= 1;
158 	else
159 		tmp &= ~1;
160 	out_be64(&priv2->spu_cfg_RW, tmp);
161 	spin_unlock_irq(&spu->register_lock);
162 }
163 
164 static u64 spu_hw_signal1_type_get(struct spu_context *ctx)
165 {
166 	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0);
167 }
168 
169 static void spu_hw_signal2_type_set(struct spu_context *ctx, u64 val)
170 {
171 	struct spu *spu = ctx->spu;
172 	struct spu_priv2 __iomem *priv2 = spu->priv2;
173 	u64 tmp;
174 
175 	spin_lock_irq(&spu->register_lock);
176 	tmp = in_be64(&priv2->spu_cfg_RW);
177 	if (val)
178 		tmp |= 2;
179 	else
180 		tmp &= ~2;
181 	out_be64(&priv2->spu_cfg_RW, tmp);
182 	spin_unlock_irq(&spu->register_lock);
183 }
184 
185 static u64 spu_hw_signal2_type_get(struct spu_context *ctx)
186 {
187 	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0);
188 }
189 
190 static u32 spu_hw_npc_read(struct spu_context *ctx)
191 {
192 	return in_be32(&ctx->spu->problem->spu_npc_RW);
193 }
194 
195 static void spu_hw_npc_write(struct spu_context *ctx, u32 val)
196 {
197 	out_be32(&ctx->spu->problem->spu_npc_RW, val);
198 }
199 
200 static u32 spu_hw_status_read(struct spu_context *ctx)
201 {
202 	return in_be32(&ctx->spu->problem->spu_status_R);
203 }
204 
205 static char *spu_hw_get_ls(struct spu_context *ctx)
206 {
207 	return ctx->spu->local_store;
208 }
209 
210 static void spu_hw_runcntl_write(struct spu_context *ctx, u32 val)
211 {
212 	spin_lock_irq(&ctx->spu->register_lock);
213 	if (val & SPU_RUNCNTL_ISOLATE)
214 		out_be64(&ctx->spu->priv2->spu_privcntl_RW, 4LL);
215 	out_be32(&ctx->spu->problem->spu_runcntl_RW, val);
216 	spin_unlock_irq(&ctx->spu->register_lock);
217 }
218 
219 static void spu_hw_master_start(struct spu_context *ctx)
220 {
221 	struct spu *spu = ctx->spu;
222 	u64 sr1;
223 
224 	spin_lock_irq(&spu->register_lock);
225 	sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
226 	spu_mfc_sr1_set(spu, sr1);
227 	spin_unlock_irq(&spu->register_lock);
228 }
229 
230 static void spu_hw_master_stop(struct spu_context *ctx)
231 {
232 	struct spu *spu = ctx->spu;
233 	u64 sr1;
234 
235 	spin_lock_irq(&spu->register_lock);
236 	sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
237 	spu_mfc_sr1_set(spu, sr1);
238 	spin_unlock_irq(&spu->register_lock);
239 }
240 
241 static int spu_hw_set_mfc_query(struct spu_context * ctx, u32 mask, u32 mode)
242 {
243 	struct spu_problem __iomem *prob = ctx->spu->problem;
244 	int ret;
245 
246 	spin_lock_irq(&ctx->spu->register_lock);
247 	ret = -EAGAIN;
248 	if (in_be32(&prob->dma_querytype_RW))
249 		goto out;
250 	ret = 0;
251 	out_be32(&prob->dma_querymask_RW, mask);
252 	out_be32(&prob->dma_querytype_RW, mode);
253 out:
254 	spin_unlock_irq(&ctx->spu->register_lock);
255 	return ret;
256 }
257 
258 static u32 spu_hw_read_mfc_tagstatus(struct spu_context * ctx)
259 {
260 	return in_be32(&ctx->spu->problem->dma_tagstatus_R);
261 }
262 
263 static u32 spu_hw_get_mfc_free_elements(struct spu_context *ctx)
264 {
265 	return in_be32(&ctx->spu->problem->dma_qstatus_R);
266 }
267 
268 static int spu_hw_send_mfc_command(struct spu_context *ctx,
269 					struct mfc_dma_command *cmd)
270 {
271 	u32 status;
272 	struct spu_problem __iomem *prob = ctx->spu->problem;
273 
274 	spin_lock_irq(&ctx->spu->register_lock);
275 	out_be32(&prob->mfc_lsa_W, cmd->lsa);
276 	out_be64(&prob->mfc_ea_W, cmd->ea);
277 	out_be32(&prob->mfc_union_W.by32.mfc_size_tag32,
278 				cmd->size << 16 | cmd->tag);
279 	out_be32(&prob->mfc_union_W.by32.mfc_class_cmd32,
280 				cmd->class << 16 | cmd->cmd);
281 	status = in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
282 	spin_unlock_irq(&ctx->spu->register_lock);
283 
284 	switch (status & 0xffff) {
285 	case 0:
286 		return 0;
287 	case 2:
288 		return -EAGAIN;
289 	default:
290 		return -EINVAL;
291 	}
292 }
293 
294 struct spu_context_ops spu_hw_ops = {
295 	.mbox_read = spu_hw_mbox_read,
296 	.mbox_stat_read = spu_hw_mbox_stat_read,
297 	.mbox_stat_poll = spu_hw_mbox_stat_poll,
298 	.ibox_read = spu_hw_ibox_read,
299 	.wbox_write = spu_hw_wbox_write,
300 	.signal1_write = spu_hw_signal1_write,
301 	.signal2_write = spu_hw_signal2_write,
302 	.signal1_type_set = spu_hw_signal1_type_set,
303 	.signal1_type_get = spu_hw_signal1_type_get,
304 	.signal2_type_set = spu_hw_signal2_type_set,
305 	.signal2_type_get = spu_hw_signal2_type_get,
306 	.npc_read = spu_hw_npc_read,
307 	.npc_write = spu_hw_npc_write,
308 	.status_read = spu_hw_status_read,
309 	.get_ls = spu_hw_get_ls,
310 	.runcntl_write = spu_hw_runcntl_write,
311 	.master_start = spu_hw_master_start,
312 	.master_stop = spu_hw_master_stop,
313 	.set_mfc_query = spu_hw_set_mfc_query,
314 	.read_mfc_tagstatus = spu_hw_read_mfc_tagstatus,
315 	.get_mfc_free_elements = spu_hw_get_mfc_free_elements,
316 	.send_mfc_command = spu_hw_send_mfc_command,
317 };
318