1 /* hw_ops.c - query/set operations on active SPU context.
2  *
3  * Copyright (C) IBM 2005
4  * Author: Mark Nutter <mnutter@us.ibm.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19  */
20 
21 #include <linux/errno.h>
22 #include <linux/sched.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/poll.h>
26 #include <linux/smp.h>
27 #include <linux/stddef.h>
28 #include <linux/unistd.h>
29 
30 #include <asm/io.h>
31 #include <asm/spu.h>
32 #include <asm/spu_priv1.h>
33 #include <asm/spu_csa.h>
34 #include <asm/mmu_context.h>
35 #include "spufs.h"
36 
37 static int spu_hw_mbox_read(struct spu_context *ctx, u32 * data)
38 {
39 	struct spu *spu = ctx->spu;
40 	struct spu_problem __iomem *prob = spu->problem;
41 	u32 mbox_stat;
42 	int ret = 0;
43 
44 	spin_lock_irq(&spu->register_lock);
45 	mbox_stat = in_be32(&prob->mb_stat_R);
46 	if (mbox_stat & 0x0000ff) {
47 		*data = in_be32(&prob->pu_mb_R);
48 		ret = 4;
49 	}
50 	spin_unlock_irq(&spu->register_lock);
51 	return ret;
52 }
53 
54 static u32 spu_hw_mbox_stat_read(struct spu_context *ctx)
55 {
56 	return in_be32(&ctx->spu->problem->mb_stat_R);
57 }
58 
59 static __poll_t spu_hw_mbox_stat_poll(struct spu_context *ctx, __poll_t events)
60 {
61 	struct spu *spu = ctx->spu;
62 	__poll_t ret = 0;
63 	u32 stat;
64 
65 	spin_lock_irq(&spu->register_lock);
66 	stat = in_be32(&spu->problem->mb_stat_R);
67 
68 	/* if the requested event is there, return the poll
69 	   mask, otherwise enable the interrupt to get notified,
70 	   but first mark any pending interrupts as done so
71 	   we don't get woken up unnecessarily */
72 
73 	if (events & (EPOLLIN | EPOLLRDNORM)) {
74 		if (stat & 0xff0000)
75 			ret |= EPOLLIN | EPOLLRDNORM;
76 		else {
77 			spu_int_stat_clear(spu, 2, CLASS2_MAILBOX_INTR);
78 			spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
79 		}
80 	}
81 	if (events & (EPOLLOUT | EPOLLWRNORM)) {
82 		if (stat & 0x00ff00)
83 			ret = EPOLLOUT | EPOLLWRNORM;
84 		else {
85 			spu_int_stat_clear(spu, 2,
86 					CLASS2_MAILBOX_THRESHOLD_INTR);
87 			spu_int_mask_or(spu, 2,
88 					CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR);
89 		}
90 	}
91 	spin_unlock_irq(&spu->register_lock);
92 	return ret;
93 }
94 
95 static int spu_hw_ibox_read(struct spu_context *ctx, u32 * data)
96 {
97 	struct spu *spu = ctx->spu;
98 	struct spu_problem __iomem *prob = spu->problem;
99 	struct spu_priv2 __iomem *priv2 = spu->priv2;
100 	int ret;
101 
102 	spin_lock_irq(&spu->register_lock);
103 	if (in_be32(&prob->mb_stat_R) & 0xff0000) {
104 		/* read the first available word */
105 		*data = in_be64(&priv2->puint_mb_R);
106 		ret = 4;
107 	} else {
108 		/* make sure we get woken up by the interrupt */
109 		spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
110 		ret = 0;
111 	}
112 	spin_unlock_irq(&spu->register_lock);
113 	return ret;
114 }
115 
116 static int spu_hw_wbox_write(struct spu_context *ctx, u32 data)
117 {
118 	struct spu *spu = ctx->spu;
119 	struct spu_problem __iomem *prob = spu->problem;
120 	int ret;
121 
122 	spin_lock_irq(&spu->register_lock);
123 	if (in_be32(&prob->mb_stat_R) & 0x00ff00) {
124 		/* we have space to write wbox_data to */
125 		out_be32(&prob->spu_mb_W, data);
126 		ret = 4;
127 	} else {
128 		/* make sure we get woken up by the interrupt when space
129 		   becomes available */
130 		spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR);
131 		ret = 0;
132 	}
133 	spin_unlock_irq(&spu->register_lock);
134 	return ret;
135 }
136 
137 static void spu_hw_signal1_write(struct spu_context *ctx, u32 data)
138 {
139 	out_be32(&ctx->spu->problem->signal_notify1, data);
140 }
141 
142 static void spu_hw_signal2_write(struct spu_context *ctx, u32 data)
143 {
144 	out_be32(&ctx->spu->problem->signal_notify2, data);
145 }
146 
147 static void spu_hw_signal1_type_set(struct spu_context *ctx, u64 val)
148 {
149 	struct spu *spu = ctx->spu;
150 	struct spu_priv2 __iomem *priv2 = spu->priv2;
151 	u64 tmp;
152 
153 	spin_lock_irq(&spu->register_lock);
154 	tmp = in_be64(&priv2->spu_cfg_RW);
155 	if (val)
156 		tmp |= 1;
157 	else
158 		tmp &= ~1;
159 	out_be64(&priv2->spu_cfg_RW, tmp);
160 	spin_unlock_irq(&spu->register_lock);
161 }
162 
163 static u64 spu_hw_signal1_type_get(struct spu_context *ctx)
164 {
165 	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0);
166 }
167 
168 static void spu_hw_signal2_type_set(struct spu_context *ctx, u64 val)
169 {
170 	struct spu *spu = ctx->spu;
171 	struct spu_priv2 __iomem *priv2 = spu->priv2;
172 	u64 tmp;
173 
174 	spin_lock_irq(&spu->register_lock);
175 	tmp = in_be64(&priv2->spu_cfg_RW);
176 	if (val)
177 		tmp |= 2;
178 	else
179 		tmp &= ~2;
180 	out_be64(&priv2->spu_cfg_RW, tmp);
181 	spin_unlock_irq(&spu->register_lock);
182 }
183 
184 static u64 spu_hw_signal2_type_get(struct spu_context *ctx)
185 {
186 	return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0);
187 }
188 
189 static u32 spu_hw_npc_read(struct spu_context *ctx)
190 {
191 	return in_be32(&ctx->spu->problem->spu_npc_RW);
192 }
193 
194 static void spu_hw_npc_write(struct spu_context *ctx, u32 val)
195 {
196 	out_be32(&ctx->spu->problem->spu_npc_RW, val);
197 }
198 
199 static u32 spu_hw_status_read(struct spu_context *ctx)
200 {
201 	return in_be32(&ctx->spu->problem->spu_status_R);
202 }
203 
204 static char *spu_hw_get_ls(struct spu_context *ctx)
205 {
206 	return ctx->spu->local_store;
207 }
208 
209 static void spu_hw_privcntl_write(struct spu_context *ctx, u64 val)
210 {
211 	out_be64(&ctx->spu->priv2->spu_privcntl_RW, val);
212 }
213 
214 static u32 spu_hw_runcntl_read(struct spu_context *ctx)
215 {
216 	return in_be32(&ctx->spu->problem->spu_runcntl_RW);
217 }
218 
219 static void spu_hw_runcntl_write(struct spu_context *ctx, u32 val)
220 {
221 	spin_lock_irq(&ctx->spu->register_lock);
222 	if (val & SPU_RUNCNTL_ISOLATE)
223 		spu_hw_privcntl_write(ctx,
224 			SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK);
225 	out_be32(&ctx->spu->problem->spu_runcntl_RW, val);
226 	spin_unlock_irq(&ctx->spu->register_lock);
227 }
228 
229 static void spu_hw_runcntl_stop(struct spu_context *ctx)
230 {
231 	spin_lock_irq(&ctx->spu->register_lock);
232 	out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP);
233 	while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING)
234 		cpu_relax();
235 	spin_unlock_irq(&ctx->spu->register_lock);
236 }
237 
238 static void spu_hw_master_start(struct spu_context *ctx)
239 {
240 	struct spu *spu = ctx->spu;
241 	u64 sr1;
242 
243 	spin_lock_irq(&spu->register_lock);
244 	sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
245 	spu_mfc_sr1_set(spu, sr1);
246 	spin_unlock_irq(&spu->register_lock);
247 }
248 
249 static void spu_hw_master_stop(struct spu_context *ctx)
250 {
251 	struct spu *spu = ctx->spu;
252 	u64 sr1;
253 
254 	spin_lock_irq(&spu->register_lock);
255 	sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
256 	spu_mfc_sr1_set(spu, sr1);
257 	spin_unlock_irq(&spu->register_lock);
258 }
259 
260 static int spu_hw_set_mfc_query(struct spu_context * ctx, u32 mask, u32 mode)
261 {
262 	struct spu_problem __iomem *prob = ctx->spu->problem;
263 	int ret;
264 
265 	spin_lock_irq(&ctx->spu->register_lock);
266 	ret = -EAGAIN;
267 	if (in_be32(&prob->dma_querytype_RW))
268 		goto out;
269 	ret = 0;
270 	out_be32(&prob->dma_querymask_RW, mask);
271 	out_be32(&prob->dma_querytype_RW, mode);
272 out:
273 	spin_unlock_irq(&ctx->spu->register_lock);
274 	return ret;
275 }
276 
277 static u32 spu_hw_read_mfc_tagstatus(struct spu_context * ctx)
278 {
279 	return in_be32(&ctx->spu->problem->dma_tagstatus_R);
280 }
281 
282 static u32 spu_hw_get_mfc_free_elements(struct spu_context *ctx)
283 {
284 	return in_be32(&ctx->spu->problem->dma_qstatus_R);
285 }
286 
287 static int spu_hw_send_mfc_command(struct spu_context *ctx,
288 					struct mfc_dma_command *cmd)
289 {
290 	u32 status;
291 	struct spu_problem __iomem *prob = ctx->spu->problem;
292 
293 	spin_lock_irq(&ctx->spu->register_lock);
294 	out_be32(&prob->mfc_lsa_W, cmd->lsa);
295 	out_be64(&prob->mfc_ea_W, cmd->ea);
296 	out_be32(&prob->mfc_union_W.by32.mfc_size_tag32,
297 				cmd->size << 16 | cmd->tag);
298 	out_be32(&prob->mfc_union_W.by32.mfc_class_cmd32,
299 				cmd->class << 16 | cmd->cmd);
300 	status = in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
301 	spin_unlock_irq(&ctx->spu->register_lock);
302 
303 	switch (status & 0xffff) {
304 	case 0:
305 		return 0;
306 	case 2:
307 		return -EAGAIN;
308 	default:
309 		return -EINVAL;
310 	}
311 }
312 
313 static void spu_hw_restart_dma(struct spu_context *ctx)
314 {
315 	struct spu_priv2 __iomem *priv2 = ctx->spu->priv2;
316 
317 	if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &ctx->spu->flags))
318 		out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
319 }
320 
321 struct spu_context_ops spu_hw_ops = {
322 	.mbox_read = spu_hw_mbox_read,
323 	.mbox_stat_read = spu_hw_mbox_stat_read,
324 	.mbox_stat_poll = spu_hw_mbox_stat_poll,
325 	.ibox_read = spu_hw_ibox_read,
326 	.wbox_write = spu_hw_wbox_write,
327 	.signal1_write = spu_hw_signal1_write,
328 	.signal2_write = spu_hw_signal2_write,
329 	.signal1_type_set = spu_hw_signal1_type_set,
330 	.signal1_type_get = spu_hw_signal1_type_get,
331 	.signal2_type_set = spu_hw_signal2_type_set,
332 	.signal2_type_get = spu_hw_signal2_type_get,
333 	.npc_read = spu_hw_npc_read,
334 	.npc_write = spu_hw_npc_write,
335 	.status_read = spu_hw_status_read,
336 	.get_ls = spu_hw_get_ls,
337 	.privcntl_write = spu_hw_privcntl_write,
338 	.runcntl_read = spu_hw_runcntl_read,
339 	.runcntl_write = spu_hw_runcntl_write,
340 	.runcntl_stop = spu_hw_runcntl_stop,
341 	.master_start = spu_hw_master_start,
342 	.master_stop = spu_hw_master_stop,
343 	.set_mfc_query = spu_hw_set_mfc_query,
344 	.read_mfc_tagstatus = spu_hw_read_mfc_tagstatus,
345 	.get_mfc_free_elements = spu_hw_get_mfc_free_elements,
346 	.send_mfc_command = spu_hw_send_mfc_command,
347 	.restart_dma = spu_hw_restart_dma,
348 };
349