1 /*
2  * spu hypervisor abstraction for direct hardware access.
3  *
4  *  (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5  *  Copyright 2006 Sony Corp.
6  *
7  *  This program is free software; you can redistribute it and/or modify
8  *  it under the terms of the GNU General Public License as published by
9  *  the Free Software Foundation; version 2 of the License.
10  *
11  *  This program is distributed in the hope that it will be useful,
12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  *  GNU General Public License for more details.
15  *
16  *  You should have received a copy of the GNU General Public License
17  *  along with this program; if not, write to the Free Software
18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19  */
20 
21 #include <linux/interrupt.h>
22 #include <linux/list.h>
23 #include <linux/module.h>
24 #include <linux/ptrace.h>
25 #include <linux/wait.h>
26 #include <linux/mm.h>
27 #include <linux/io.h>
28 #include <linux/mutex.h>
29 #include <linux/device.h>
30 #include <linux/sched.h>
31 
32 #include <asm/spu.h>
33 #include <asm/spu_priv1.h>
34 #include <asm/firmware.h>
35 #include <asm/prom.h>
36 
37 #include "interrupt.h"
38 #include "spu_priv1_mmio.h"
39 
40 static void int_mask_and(struct spu *spu, int class, u64 mask)
41 {
42 	u64 old_mask;
43 
44 	old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
45 	out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask);
46 }
47 
48 static void int_mask_or(struct spu *spu, int class, u64 mask)
49 {
50 	u64 old_mask;
51 
52 	old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
53 	out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask);
54 }
55 
56 static void int_mask_set(struct spu *spu, int class, u64 mask)
57 {
58 	out_be64(&spu->priv1->int_mask_RW[class], mask);
59 }
60 
61 static u64 int_mask_get(struct spu *spu, int class)
62 {
63 	return in_be64(&spu->priv1->int_mask_RW[class]);
64 }
65 
66 static void int_stat_clear(struct spu *spu, int class, u64 stat)
67 {
68 	out_be64(&spu->priv1->int_stat_RW[class], stat);
69 }
70 
71 static u64 int_stat_get(struct spu *spu, int class)
72 {
73 	return in_be64(&spu->priv1->int_stat_RW[class]);
74 }
75 
76 static void cpu_affinity_set(struct spu *spu, int cpu)
77 {
78 	u64 target;
79 	u64 route;
80 
81 	if (nr_cpus_node(spu->node)) {
82 		const struct cpumask *spumask = cpumask_of_node(spu->node),
83 			*cpumask = cpumask_of_node(cpu_to_node(cpu));
84 
85 		if (!cpumask_intersects(spumask, cpumask))
86 			return;
87 	}
88 
89 	target = iic_get_target_id(cpu);
90 	route = target << 48 | target << 32 | target << 16;
91 	out_be64(&spu->priv1->int_route_RW, route);
92 }
93 
94 static u64 mfc_dar_get(struct spu *spu)
95 {
96 	return in_be64(&spu->priv1->mfc_dar_RW);
97 }
98 
99 static u64 mfc_dsisr_get(struct spu *spu)
100 {
101 	return in_be64(&spu->priv1->mfc_dsisr_RW);
102 }
103 
104 static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
105 {
106 	out_be64(&spu->priv1->mfc_dsisr_RW, dsisr);
107 }
108 
109 static void mfc_sdr_setup(struct spu *spu)
110 {
111 	out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
112 }
113 
114 static void mfc_sr1_set(struct spu *spu, u64 sr1)
115 {
116 	out_be64(&spu->priv1->mfc_sr1_RW, sr1);
117 }
118 
119 static u64 mfc_sr1_get(struct spu *spu)
120 {
121 	return in_be64(&spu->priv1->mfc_sr1_RW);
122 }
123 
124 static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
125 {
126 	out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id);
127 }
128 
129 static u64 mfc_tclass_id_get(struct spu *spu)
130 {
131 	return in_be64(&spu->priv1->mfc_tclass_id_RW);
132 }
133 
134 static void tlb_invalidate(struct spu *spu)
135 {
136 	out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul);
137 }
138 
139 static void resource_allocation_groupID_set(struct spu *spu, u64 id)
140 {
141 	out_be64(&spu->priv1->resource_allocation_groupID_RW, id);
142 }
143 
144 static u64 resource_allocation_groupID_get(struct spu *spu)
145 {
146 	return in_be64(&spu->priv1->resource_allocation_groupID_RW);
147 }
148 
149 static void resource_allocation_enable_set(struct spu *spu, u64 enable)
150 {
151 	out_be64(&spu->priv1->resource_allocation_enable_RW, enable);
152 }
153 
154 static u64 resource_allocation_enable_get(struct spu *spu)
155 {
156 	return in_be64(&spu->priv1->resource_allocation_enable_RW);
157 }
158 
159 const struct spu_priv1_ops spu_priv1_mmio_ops =
160 {
161 	.int_mask_and = int_mask_and,
162 	.int_mask_or = int_mask_or,
163 	.int_mask_set = int_mask_set,
164 	.int_mask_get = int_mask_get,
165 	.int_stat_clear = int_stat_clear,
166 	.int_stat_get = int_stat_get,
167 	.cpu_affinity_set = cpu_affinity_set,
168 	.mfc_dar_get = mfc_dar_get,
169 	.mfc_dsisr_get = mfc_dsisr_get,
170 	.mfc_dsisr_set = mfc_dsisr_set,
171 	.mfc_sdr_setup = mfc_sdr_setup,
172 	.mfc_sr1_set = mfc_sr1_set,
173 	.mfc_sr1_get = mfc_sr1_get,
174 	.mfc_tclass_id_set = mfc_tclass_id_set,
175 	.mfc_tclass_id_get = mfc_tclass_id_get,
176 	.tlb_invalidate = tlb_invalidate,
177 	.resource_allocation_groupID_set = resource_allocation_groupID_set,
178 	.resource_allocation_groupID_get = resource_allocation_groupID_get,
179 	.resource_allocation_enable_set = resource_allocation_enable_set,
180 	.resource_allocation_enable_get = resource_allocation_enable_get,
181 };
182