1 /*
2  * Low-level SPU handling
3  *
4  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5  *
6  * Author: Arnd Bergmann <arndb@de.ibm.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2, or (at your option)
11  * any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22 
23 #undef DEBUG
24 
25 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/module.h>
28 #include <linux/ptrace.h>
29 #include <linux/slab.h>
30 #include <linux/wait.h>
31 #include <linux/mm.h>
32 #include <linux/io.h>
33 #include <linux/mutex.h>
34 #include <asm/spu.h>
35 #include <asm/spu_priv1.h>
36 #include <asm/xmon.h>
37 
38 const struct spu_management_ops *spu_management_ops;
39 EXPORT_SYMBOL_GPL(spu_management_ops);
40 
41 const struct spu_priv1_ops *spu_priv1_ops;
42 
43 static struct list_head spu_list[MAX_NUMNODES];
44 static LIST_HEAD(spu_full_list);
45 static DEFINE_MUTEX(spu_mutex);
46 static DEFINE_SPINLOCK(spu_list_lock);
47 
48 EXPORT_SYMBOL_GPL(spu_priv1_ops);
49 
50 void spu_invalidate_slbs(struct spu *spu)
51 {
52 	struct spu_priv2 __iomem *priv2 = spu->priv2;
53 
54 	if (spu_mfc_sr1_get(spu) & MFC_STATE1_RELOCATE_MASK)
55 		out_be64(&priv2->slb_invalidate_all_W, 0UL);
56 }
57 EXPORT_SYMBOL_GPL(spu_invalidate_slbs);
58 
59 /* This is called by the MM core when a segment size is changed, to
60  * request a flush of all the SPEs using a given mm
61  */
62 void spu_flush_all_slbs(struct mm_struct *mm)
63 {
64 	struct spu *spu;
65 	unsigned long flags;
66 
67 	spin_lock_irqsave(&spu_list_lock, flags);
68 	list_for_each_entry(spu, &spu_full_list, full_list) {
69 		if (spu->mm == mm)
70 			spu_invalidate_slbs(spu);
71 	}
72 	spin_unlock_irqrestore(&spu_list_lock, flags);
73 }
74 
75 /* The hack below stinks... try to do something better one of
76  * these days... Does it even work properly with NR_CPUS == 1 ?
77  */
78 static inline void mm_needs_global_tlbie(struct mm_struct *mm)
79 {
80 	int nr = (NR_CPUS > 1) ? NR_CPUS : NR_CPUS + 1;
81 
82 	/* Global TLBIE broadcast required with SPEs. */
83 	__cpus_setall(&mm->cpu_vm_mask, nr);
84 }
85 
86 void spu_associate_mm(struct spu *spu, struct mm_struct *mm)
87 {
88 	unsigned long flags;
89 
90 	spin_lock_irqsave(&spu_list_lock, flags);
91 	spu->mm = mm;
92 	spin_unlock_irqrestore(&spu_list_lock, flags);
93 	if (mm)
94 		mm_needs_global_tlbie(mm);
95 }
96 EXPORT_SYMBOL_GPL(spu_associate_mm);
97 
98 static int __spu_trap_invalid_dma(struct spu *spu)
99 {
100 	pr_debug("%s\n", __FUNCTION__);
101 	spu->dma_callback(spu, SPE_EVENT_INVALID_DMA);
102 	return 0;
103 }
104 
105 static int __spu_trap_dma_align(struct spu *spu)
106 {
107 	pr_debug("%s\n", __FUNCTION__);
108 	spu->dma_callback(spu, SPE_EVENT_DMA_ALIGNMENT);
109 	return 0;
110 }
111 
112 static int __spu_trap_error(struct spu *spu)
113 {
114 	pr_debug("%s\n", __FUNCTION__);
115 	spu->dma_callback(spu, SPE_EVENT_SPE_ERROR);
116 	return 0;
117 }
118 
119 static void spu_restart_dma(struct spu *spu)
120 {
121 	struct spu_priv2 __iomem *priv2 = spu->priv2;
122 
123 	if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags))
124 		out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
125 }
126 
127 static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
128 {
129 	struct spu_priv2 __iomem *priv2 = spu->priv2;
130 	struct mm_struct *mm = spu->mm;
131 	u64 esid, vsid, llp;
132 	int psize;
133 
134 	pr_debug("%s\n", __FUNCTION__);
135 
136 	if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
137 		/* SLBs are pre-loaded for context switch, so
138 		 * we should never get here!
139 		 */
140 		printk("%s: invalid access during switch!\n", __func__);
141 		return 1;
142 	}
143 	esid = (ea & ESID_MASK) | SLB_ESID_V;
144 
145 	switch(REGION_ID(ea)) {
146 	case USER_REGION_ID:
147 #ifdef CONFIG_PPC_MM_SLICES
148 		psize = get_slice_psize(mm, ea);
149 #else
150 		psize = mm->context.user_psize;
151 #endif
152 		vsid = (get_vsid(mm->context.id, ea) << SLB_VSID_SHIFT) |
153 				SLB_VSID_USER;
154 		break;
155 	case VMALLOC_REGION_ID:
156 		if (ea < VMALLOC_END)
157 			psize = mmu_vmalloc_psize;
158 		else
159 			psize = mmu_io_psize;
160 		vsid = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
161 			SLB_VSID_KERNEL;
162 		break;
163 	case KERNEL_REGION_ID:
164 		psize = mmu_linear_psize;
165 		vsid = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
166 			SLB_VSID_KERNEL;
167 		break;
168 	default:
169 		/* Future: support kernel segments so that drivers
170 		 * can use SPUs.
171 		 */
172 		pr_debug("invalid region access at %016lx\n", ea);
173 		return 1;
174 	}
175 	llp = mmu_psize_defs[psize].sllp;
176 
177 	out_be64(&priv2->slb_index_W, spu->slb_replace);
178 	out_be64(&priv2->slb_vsid_RW, vsid | llp);
179 	out_be64(&priv2->slb_esid_RW, esid);
180 
181 	spu->slb_replace++;
182 	if (spu->slb_replace >= 8)
183 		spu->slb_replace = 0;
184 
185 	spu_restart_dma(spu);
186 
187 	return 0;
188 }
189 
190 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX
191 static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
192 {
193 	pr_debug("%s, %lx, %lx\n", __FUNCTION__, dsisr, ea);
194 
195 	/* Handle kernel space hash faults immediately.
196 	   User hash faults need to be deferred to process context. */
197 	if ((dsisr & MFC_DSISR_PTE_NOT_FOUND)
198 	    && REGION_ID(ea) != USER_REGION_ID
199 	    && hash_page(ea, _PAGE_PRESENT, 0x300) == 0) {
200 		spu_restart_dma(spu);
201 		return 0;
202 	}
203 
204 	if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags)) {
205 		printk("%s: invalid access during switch!\n", __func__);
206 		return 1;
207 	}
208 
209 	spu->dar = ea;
210 	spu->dsisr = dsisr;
211 	mb();
212 	spu->stop_callback(spu);
213 	return 0;
214 }
215 
216 static irqreturn_t
217 spu_irq_class_0(int irq, void *data)
218 {
219 	struct spu *spu;
220 
221 	spu = data;
222 	spu->class_0_pending = 1;
223 	spu->stop_callback(spu);
224 
225 	return IRQ_HANDLED;
226 }
227 
228 int
229 spu_irq_class_0_bottom(struct spu *spu)
230 {
231 	unsigned long stat, mask;
232 	unsigned long flags;
233 
234 	spu->class_0_pending = 0;
235 
236 	spin_lock_irqsave(&spu->register_lock, flags);
237 	mask = spu_int_mask_get(spu, 0);
238 	stat = spu_int_stat_get(spu, 0);
239 
240 	stat &= mask;
241 
242 	if (stat & 1) /* invalid DMA alignment */
243 		__spu_trap_dma_align(spu);
244 
245 	if (stat & 2) /* invalid MFC DMA */
246 		__spu_trap_invalid_dma(spu);
247 
248 	if (stat & 4) /* error on SPU */
249 		__spu_trap_error(spu);
250 
251 	spu_int_stat_clear(spu, 0, stat);
252 	spin_unlock_irqrestore(&spu->register_lock, flags);
253 
254 	return (stat & 0x7) ? -EIO : 0;
255 }
256 EXPORT_SYMBOL_GPL(spu_irq_class_0_bottom);
257 
258 static irqreturn_t
259 spu_irq_class_1(int irq, void *data)
260 {
261 	struct spu *spu;
262 	unsigned long stat, mask, dar, dsisr;
263 
264 	spu = data;
265 
266 	/* atomically read & clear class1 status. */
267 	spin_lock(&spu->register_lock);
268 	mask  = spu_int_mask_get(spu, 1);
269 	stat  = spu_int_stat_get(spu, 1) & mask;
270 	dar   = spu_mfc_dar_get(spu);
271 	dsisr = spu_mfc_dsisr_get(spu);
272 	if (stat & 2) /* mapping fault */
273 		spu_mfc_dsisr_set(spu, 0ul);
274 	spu_int_stat_clear(spu, 1, stat);
275 	spin_unlock(&spu->register_lock);
276 	pr_debug("%s: %lx %lx %lx %lx\n", __FUNCTION__, mask, stat,
277 			dar, dsisr);
278 
279 	if (stat & 1) /* segment fault */
280 		__spu_trap_data_seg(spu, dar);
281 
282 	if (stat & 2) { /* mapping fault */
283 		__spu_trap_data_map(spu, dar, dsisr);
284 	}
285 
286 	if (stat & 4) /* ls compare & suspend on get */
287 		;
288 
289 	if (stat & 8) /* ls compare & suspend on put */
290 		;
291 
292 	return stat ? IRQ_HANDLED : IRQ_NONE;
293 }
294 
295 static irqreturn_t
296 spu_irq_class_2(int irq, void *data)
297 {
298 	struct spu *spu;
299 	unsigned long stat;
300 	unsigned long mask;
301 
302 	spu = data;
303 	spin_lock(&spu->register_lock);
304 	stat = spu_int_stat_get(spu, 2);
305 	mask = spu_int_mask_get(spu, 2);
306 	/* ignore interrupts we're not waiting for */
307 	stat &= mask;
308 	/*
309 	 * mailbox interrupts (0x1 and 0x10) are level triggered.
310 	 * mask them now before acknowledging.
311 	 */
312 	if (stat & 0x11)
313 		spu_int_mask_and(spu, 2, ~(stat & 0x11));
314 	/* acknowledge all interrupts before the callbacks */
315 	spu_int_stat_clear(spu, 2, stat);
316 	spin_unlock(&spu->register_lock);
317 
318 	pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask);
319 
320 	if (stat & 1)  /* PPC core mailbox */
321 		spu->ibox_callback(spu);
322 
323 	if (stat & 2) /* SPU stop-and-signal */
324 		spu->stop_callback(spu);
325 
326 	if (stat & 4) /* SPU halted */
327 		spu->stop_callback(spu);
328 
329 	if (stat & 8) /* DMA tag group complete */
330 		spu->mfc_callback(spu);
331 
332 	if (stat & 0x10) /* SPU mailbox threshold */
333 		spu->wbox_callback(spu);
334 
335 	return stat ? IRQ_HANDLED : IRQ_NONE;
336 }
337 
338 static int spu_request_irqs(struct spu *spu)
339 {
340 	int ret = 0;
341 
342 	if (spu->irqs[0] != NO_IRQ) {
343 		snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0",
344 			 spu->number);
345 		ret = request_irq(spu->irqs[0], spu_irq_class_0,
346 				  IRQF_DISABLED,
347 				  spu->irq_c0, spu);
348 		if (ret)
349 			goto bail0;
350 	}
351 	if (spu->irqs[1] != NO_IRQ) {
352 		snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1",
353 			 spu->number);
354 		ret = request_irq(spu->irqs[1], spu_irq_class_1,
355 				  IRQF_DISABLED,
356 				  spu->irq_c1, spu);
357 		if (ret)
358 			goto bail1;
359 	}
360 	if (spu->irqs[2] != NO_IRQ) {
361 		snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2",
362 			 spu->number);
363 		ret = request_irq(spu->irqs[2], spu_irq_class_2,
364 				  IRQF_DISABLED,
365 				  spu->irq_c2, spu);
366 		if (ret)
367 			goto bail2;
368 	}
369 	return 0;
370 
371 bail2:
372 	if (spu->irqs[1] != NO_IRQ)
373 		free_irq(spu->irqs[1], spu);
374 bail1:
375 	if (spu->irqs[0] != NO_IRQ)
376 		free_irq(spu->irqs[0], spu);
377 bail0:
378 	return ret;
379 }
380 
381 static void spu_free_irqs(struct spu *spu)
382 {
383 	if (spu->irqs[0] != NO_IRQ)
384 		free_irq(spu->irqs[0], spu);
385 	if (spu->irqs[1] != NO_IRQ)
386 		free_irq(spu->irqs[1], spu);
387 	if (spu->irqs[2] != NO_IRQ)
388 		free_irq(spu->irqs[2], spu);
389 }
390 
391 static void spu_init_channels(struct spu *spu)
392 {
393 	static const struct {
394 		 unsigned channel;
395 		 unsigned count;
396 	} zero_list[] = {
397 		{ 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
398 		{ 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
399 	}, count_list[] = {
400 		{ 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
401 		{ 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
402 		{ 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
403 	};
404 	struct spu_priv2 __iomem *priv2;
405 	int i;
406 
407 	priv2 = spu->priv2;
408 
409 	/* initialize all channel data to zero */
410 	for (i = 0; i < ARRAY_SIZE(zero_list); i++) {
411 		int count;
412 
413 		out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
414 		for (count = 0; count < zero_list[i].count; count++)
415 			out_be64(&priv2->spu_chnldata_RW, 0);
416 	}
417 
418 	/* initialize channel counts to meaningful values */
419 	for (i = 0; i < ARRAY_SIZE(count_list); i++) {
420 		out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
421 		out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
422 	}
423 }
424 
425 struct spu *spu_alloc_node(int node)
426 {
427 	struct spu *spu = NULL;
428 
429 	mutex_lock(&spu_mutex);
430 	if (!list_empty(&spu_list[node])) {
431 		spu = list_entry(spu_list[node].next, struct spu, list);
432 		list_del_init(&spu->list);
433 		pr_debug("Got SPU %d %d\n", spu->number, spu->node);
434 	}
435 	mutex_unlock(&spu_mutex);
436 
437 	if (spu)
438 		spu_init_channels(spu);
439 	return spu;
440 }
441 EXPORT_SYMBOL_GPL(spu_alloc_node);
442 
443 struct spu *spu_alloc(void)
444 {
445 	struct spu *spu = NULL;
446 	int node;
447 
448 	for (node = 0; node < MAX_NUMNODES; node++) {
449 		spu = spu_alloc_node(node);
450 		if (spu)
451 			break;
452 	}
453 
454 	return spu;
455 }
456 
457 void spu_free(struct spu *spu)
458 {
459 	mutex_lock(&spu_mutex);
460 	list_add_tail(&spu->list, &spu_list[spu->node]);
461 	mutex_unlock(&spu_mutex);
462 }
463 EXPORT_SYMBOL_GPL(spu_free);
464 
465 struct sysdev_class spu_sysdev_class = {
466 	set_kset_name("spu")
467 };
468 
469 int spu_add_sysdev_attr(struct sysdev_attribute *attr)
470 {
471 	struct spu *spu;
472 	mutex_lock(&spu_mutex);
473 
474 	list_for_each_entry(spu, &spu_full_list, full_list)
475 		sysdev_create_file(&spu->sysdev, attr);
476 
477 	mutex_unlock(&spu_mutex);
478 	return 0;
479 }
480 EXPORT_SYMBOL_GPL(spu_add_sysdev_attr);
481 
482 int spu_add_sysdev_attr_group(struct attribute_group *attrs)
483 {
484 	struct spu *spu;
485 	mutex_lock(&spu_mutex);
486 
487 	list_for_each_entry(spu, &spu_full_list, full_list)
488 		sysfs_create_group(&spu->sysdev.kobj, attrs);
489 
490 	mutex_unlock(&spu_mutex);
491 	return 0;
492 }
493 EXPORT_SYMBOL_GPL(spu_add_sysdev_attr_group);
494 
495 
496 void spu_remove_sysdev_attr(struct sysdev_attribute *attr)
497 {
498 	struct spu *spu;
499 	mutex_lock(&spu_mutex);
500 
501 	list_for_each_entry(spu, &spu_full_list, full_list)
502 		sysdev_remove_file(&spu->sysdev, attr);
503 
504 	mutex_unlock(&spu_mutex);
505 }
506 EXPORT_SYMBOL_GPL(spu_remove_sysdev_attr);
507 
508 void spu_remove_sysdev_attr_group(struct attribute_group *attrs)
509 {
510 	struct spu *spu;
511 	mutex_lock(&spu_mutex);
512 
513 	list_for_each_entry(spu, &spu_full_list, full_list)
514 		sysfs_remove_group(&spu->sysdev.kobj, attrs);
515 
516 	mutex_unlock(&spu_mutex);
517 }
518 EXPORT_SYMBOL_GPL(spu_remove_sysdev_attr_group);
519 
520 static int spu_create_sysdev(struct spu *spu)
521 {
522 	int ret;
523 
524 	spu->sysdev.id = spu->number;
525 	spu->sysdev.cls = &spu_sysdev_class;
526 	ret = sysdev_register(&spu->sysdev);
527 	if (ret) {
528 		printk(KERN_ERR "Can't register SPU %d with sysfs\n",
529 				spu->number);
530 		return ret;
531 	}
532 
533 	sysfs_add_device_to_node(&spu->sysdev, spu->node);
534 
535 	return 0;
536 }
537 
538 static int __init create_spu(void *data)
539 {
540 	struct spu *spu;
541 	int ret;
542 	static int number;
543 	unsigned long flags;
544 
545 	ret = -ENOMEM;
546 	spu = kzalloc(sizeof (*spu), GFP_KERNEL);
547 	if (!spu)
548 		goto out;
549 
550 	spin_lock_init(&spu->register_lock);
551 	mutex_lock(&spu_mutex);
552 	spu->number = number++;
553 	mutex_unlock(&spu_mutex);
554 
555 	ret = spu_create_spu(spu, data);
556 
557 	if (ret)
558 		goto out_free;
559 
560 	spu_mfc_sdr_setup(spu);
561 	spu_mfc_sr1_set(spu, 0x33);
562 	ret = spu_request_irqs(spu);
563 	if (ret)
564 		goto out_destroy;
565 
566 	ret = spu_create_sysdev(spu);
567 	if (ret)
568 		goto out_free_irqs;
569 
570 	mutex_lock(&spu_mutex);
571 	spin_lock_irqsave(&spu_list_lock, flags);
572 	list_add(&spu->list, &spu_list[spu->node]);
573 	list_add(&spu->full_list, &spu_full_list);
574 	spin_unlock_irqrestore(&spu_list_lock, flags);
575 	mutex_unlock(&spu_mutex);
576 
577 	goto out;
578 
579 out_free_irqs:
580 	spu_free_irqs(spu);
581 out_destroy:
582 	spu_destroy_spu(spu);
583 out_free:
584 	kfree(spu);
585 out:
586 	return ret;
587 }
588 
589 static int __init init_spu_base(void)
590 {
591 	int i, ret = 0;
592 
593 	for (i = 0; i < MAX_NUMNODES; i++)
594 		INIT_LIST_HEAD(&spu_list[i]);
595 
596 	if (!spu_management_ops)
597 		goto out;
598 
599 	/* create sysdev class for spus */
600 	ret = sysdev_class_register(&spu_sysdev_class);
601 	if (ret)
602 		goto out;
603 
604 	ret = spu_enumerate_spus(create_spu);
605 
606 	if (ret) {
607 		printk(KERN_WARNING "%s: Error initializing spus\n",
608 			__FUNCTION__);
609 		goto out_unregister_sysdev_class;
610 	}
611 
612 	xmon_register_spus(&spu_full_list);
613 
614 	return 0;
615 
616  out_unregister_sysdev_class:
617 	sysdev_class_unregister(&spu_sysdev_class);
618  out:
619 
620 	return ret;
621 }
622 module_init(init_spu_base);
623 
624 MODULE_LICENSE("GPL");
625 MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>");
626