1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * External Interrupt Controller on Spider South Bridge
4  *
5  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
6  *
7  * Author: Arnd Bergmann <arndb@de.ibm.com>
8  */
9 
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/ioport.h>
13 
14 #include <asm/pgtable.h>
15 #include <asm/prom.h>
16 #include <asm/io.h>
17 
18 #include "interrupt.h"
19 
20 /* register layout taken from Spider spec, table 7.4-4 */
21 enum {
22 	TIR_DEN		= 0x004, /* Detection Enable Register */
23 	TIR_MSK		= 0x084, /* Mask Level Register */
24 	TIR_EDC		= 0x0c0, /* Edge Detection Clear Register */
25 	TIR_PNDA	= 0x100, /* Pending Register A */
26 	TIR_PNDB	= 0x104, /* Pending Register B */
27 	TIR_CS		= 0x144, /* Current Status Register */
28 	TIR_LCSA	= 0x150, /* Level Current Status Register A */
29 	TIR_LCSB	= 0x154, /* Level Current Status Register B */
30 	TIR_LCSC	= 0x158, /* Level Current Status Register C */
31 	TIR_LCSD	= 0x15c, /* Level Current Status Register D */
32 	TIR_CFGA	= 0x200, /* Setting Register A0 */
33 	TIR_CFGB	= 0x204, /* Setting Register B0 */
34 			/* 0x208 ... 0x3ff Setting Register An/Bn */
35 	TIR_PPNDA	= 0x400, /* Packet Pending Register A */
36 	TIR_PPNDB	= 0x404, /* Packet Pending Register B */
37 	TIR_PIERA	= 0x408, /* Packet Output Error Register A */
38 	TIR_PIERB	= 0x40c, /* Packet Output Error Register B */
39 	TIR_PIEN	= 0x444, /* Packet Output Enable Register */
40 	TIR_PIPND	= 0x454, /* Packet Output Pending Register */
41 	TIRDID		= 0x484, /* Spider Device ID Register */
42 	REISTIM		= 0x500, /* Reissue Command Timeout Time Setting */
43 	REISTIMEN	= 0x504, /* Reissue Command Timeout Setting */
44 	REISWAITEN	= 0x508, /* Reissue Wait Control*/
45 };
46 
47 #define SPIDER_CHIP_COUNT	4
48 #define SPIDER_SRC_COUNT	64
49 #define SPIDER_IRQ_INVALID	63
50 
51 struct spider_pic {
52 	struct irq_domain		*host;
53 	void __iomem		*regs;
54 	unsigned int		node_id;
55 };
56 static struct spider_pic spider_pics[SPIDER_CHIP_COUNT];
57 
58 static struct spider_pic *spider_irq_data_to_pic(struct irq_data *d)
59 {
60 	return irq_data_get_irq_chip_data(d);
61 }
62 
63 static void __iomem *spider_get_irq_config(struct spider_pic *pic,
64 					   unsigned int src)
65 {
66 	return pic->regs + TIR_CFGA + 8 * src;
67 }
68 
69 static void spider_unmask_irq(struct irq_data *d)
70 {
71 	struct spider_pic *pic = spider_irq_data_to_pic(d);
72 	void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d));
73 
74 	out_be32(cfg, in_be32(cfg) | 0x30000000u);
75 }
76 
77 static void spider_mask_irq(struct irq_data *d)
78 {
79 	struct spider_pic *pic = spider_irq_data_to_pic(d);
80 	void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d));
81 
82 	out_be32(cfg, in_be32(cfg) & ~0x30000000u);
83 }
84 
85 static void spider_ack_irq(struct irq_data *d)
86 {
87 	struct spider_pic *pic = spider_irq_data_to_pic(d);
88 	unsigned int src = irqd_to_hwirq(d);
89 
90 	/* Reset edge detection logic if necessary
91 	 */
92 	if (irqd_is_level_type(d))
93 		return;
94 
95 	/* Only interrupts 47 to 50 can be set to edge */
96 	if (src < 47 || src > 50)
97 		return;
98 
99 	/* Perform the clear of the edge logic */
100 	out_be32(pic->regs + TIR_EDC, 0x100 | (src & 0xf));
101 }
102 
103 static int spider_set_irq_type(struct irq_data *d, unsigned int type)
104 {
105 	unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
106 	struct spider_pic *pic = spider_irq_data_to_pic(d);
107 	unsigned int hw = irqd_to_hwirq(d);
108 	void __iomem *cfg = spider_get_irq_config(pic, hw);
109 	u32 old_mask;
110 	u32 ic;
111 
112 	/* Note that only level high is supported for most interrupts */
113 	if (sense != IRQ_TYPE_NONE && sense != IRQ_TYPE_LEVEL_HIGH &&
114 	    (hw < 47 || hw > 50))
115 		return -EINVAL;
116 
117 	/* Decode sense type */
118 	switch(sense) {
119 	case IRQ_TYPE_EDGE_RISING:
120 		ic = 0x3;
121 		break;
122 	case IRQ_TYPE_EDGE_FALLING:
123 		ic = 0x2;
124 		break;
125 	case IRQ_TYPE_LEVEL_LOW:
126 		ic = 0x0;
127 		break;
128 	case IRQ_TYPE_LEVEL_HIGH:
129 	case IRQ_TYPE_NONE:
130 		ic = 0x1;
131 		break;
132 	default:
133 		return -EINVAL;
134 	}
135 
136 	/* Configure the source. One gross hack that was there before and
137 	 * that I've kept around is the priority to the BE which I set to
138 	 * be the same as the interrupt source number. I don't know whether
139 	 * that's supposed to make any kind of sense however, we'll have to
140 	 * decide that, but for now, I'm not changing the behaviour.
141 	 */
142 	old_mask = in_be32(cfg) & 0x30000000u;
143 	out_be32(cfg, old_mask | (ic << 24) | (0x7 << 16) |
144 		 (pic->node_id << 4) | 0xe);
145 	out_be32(cfg + 4, (0x2 << 16) | (hw & 0xff));
146 
147 	return 0;
148 }
149 
150 static struct irq_chip spider_pic = {
151 	.name = "SPIDER",
152 	.irq_unmask = spider_unmask_irq,
153 	.irq_mask = spider_mask_irq,
154 	.irq_ack = spider_ack_irq,
155 	.irq_set_type = spider_set_irq_type,
156 };
157 
158 static int spider_host_map(struct irq_domain *h, unsigned int virq,
159 			irq_hw_number_t hw)
160 {
161 	irq_set_chip_data(virq, h->host_data);
162 	irq_set_chip_and_handler(virq, &spider_pic, handle_level_irq);
163 
164 	/* Set default irq type */
165 	irq_set_irq_type(virq, IRQ_TYPE_NONE);
166 
167 	return 0;
168 }
169 
170 static int spider_host_xlate(struct irq_domain *h, struct device_node *ct,
171 			   const u32 *intspec, unsigned int intsize,
172 			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)
173 
174 {
175 	/* Spider interrupts have 2 cells, first is the interrupt source,
176 	 * second, well, I don't know for sure yet ... We mask the top bits
177 	 * because old device-trees encode a node number in there
178 	 */
179 	*out_hwirq = intspec[0] & 0x3f;
180 	*out_flags = IRQ_TYPE_LEVEL_HIGH;
181 	return 0;
182 }
183 
184 static const struct irq_domain_ops spider_host_ops = {
185 	.map = spider_host_map,
186 	.xlate = spider_host_xlate,
187 };
188 
189 static void spider_irq_cascade(struct irq_desc *desc)
190 {
191 	struct irq_chip *chip = irq_desc_get_chip(desc);
192 	struct spider_pic *pic = irq_desc_get_handler_data(desc);
193 	unsigned int cs, virq;
194 
195 	cs = in_be32(pic->regs + TIR_CS) >> 24;
196 	if (cs == SPIDER_IRQ_INVALID)
197 		virq = 0;
198 	else
199 		virq = irq_linear_revmap(pic->host, cs);
200 
201 	if (virq)
202 		generic_handle_irq(virq);
203 
204 	chip->irq_eoi(&desc->irq_data);
205 }
206 
207 /* For hooking up the cascade we have a problem. Our device-tree is
208  * crap and we don't know on which BE iic interrupt we are hooked on at
209  * least not the "standard" way. We can reconstitute it based on two
210  * informations though: which BE node we are connected to and whether
211  * we are connected to IOIF0 or IOIF1. Right now, we really only care
212  * about the IBM cell blade and we know that its firmware gives us an
213  * interrupt-map property which is pretty strange.
214  */
215 static unsigned int __init spider_find_cascade_and_node(struct spider_pic *pic)
216 {
217 	unsigned int virq;
218 	const u32 *imap, *tmp;
219 	int imaplen, intsize, unit;
220 	struct device_node *iic;
221 	struct device_node *of_node;
222 
223 	of_node = irq_domain_get_of_node(pic->host);
224 
225 	/* First, we check whether we have a real "interrupts" in the device
226 	 * tree in case the device-tree is ever fixed
227 	 */
228 	virq = irq_of_parse_and_map(of_node, 0);
229 	if (virq)
230 		return virq;
231 
232 	/* Now do the horrible hacks */
233 	tmp = of_get_property(of_node, "#interrupt-cells", NULL);
234 	if (tmp == NULL)
235 		return 0;
236 	intsize = *tmp;
237 	imap = of_get_property(of_node, "interrupt-map", &imaplen);
238 	if (imap == NULL || imaplen < (intsize + 1))
239 		return 0;
240 	iic = of_find_node_by_phandle(imap[intsize]);
241 	if (iic == NULL)
242 		return 0;
243 	imap += intsize + 1;
244 	tmp = of_get_property(iic, "#interrupt-cells", NULL);
245 	if (tmp == NULL) {
246 		of_node_put(iic);
247 		return 0;
248 	}
249 	intsize = *tmp;
250 	/* Assume unit is last entry of interrupt specifier */
251 	unit = imap[intsize - 1];
252 	/* Ok, we have a unit, now let's try to get the node */
253 	tmp = of_get_property(iic, "ibm,interrupt-server-ranges", NULL);
254 	if (tmp == NULL) {
255 		of_node_put(iic);
256 		return 0;
257 	}
258 	/* ugly as hell but works for now */
259 	pic->node_id = (*tmp) >> 1;
260 	of_node_put(iic);
261 
262 	/* Ok, now let's get cracking. You may ask me why I just didn't match
263 	 * the iic host from the iic OF node, but that way I'm still compatible
264 	 * with really really old old firmwares for which we don't have a node
265 	 */
266 	/* Manufacture an IIC interrupt number of class 2 */
267 	virq = irq_create_mapping(NULL,
268 				  (pic->node_id << IIC_IRQ_NODE_SHIFT) |
269 				  (2 << IIC_IRQ_CLASS_SHIFT) |
270 				  unit);
271 	if (!virq)
272 		printk(KERN_ERR "spider_pic: failed to map cascade !");
273 	return virq;
274 }
275 
276 
277 static void __init spider_init_one(struct device_node *of_node, int chip,
278 				   unsigned long addr)
279 {
280 	struct spider_pic *pic = &spider_pics[chip];
281 	int i, virq;
282 
283 	/* Map registers */
284 	pic->regs = ioremap(addr, 0x1000);
285 	if (pic->regs == NULL)
286 		panic("spider_pic: can't map registers !");
287 
288 	/* Allocate a host */
289 	pic->host = irq_domain_add_linear(of_node, SPIDER_SRC_COUNT,
290 					  &spider_host_ops, pic);
291 	if (pic->host == NULL)
292 		panic("spider_pic: can't allocate irq host !");
293 
294 	/* Go through all sources and disable them */
295 	for (i = 0; i < SPIDER_SRC_COUNT; i++) {
296 		void __iomem *cfg = pic->regs + TIR_CFGA + 8 * i;
297 		out_be32(cfg, in_be32(cfg) & ~0x30000000u);
298 	}
299 
300 	/* do not mask any interrupts because of level */
301 	out_be32(pic->regs + TIR_MSK, 0x0);
302 
303 	/* enable interrupt packets to be output */
304 	out_be32(pic->regs + TIR_PIEN, in_be32(pic->regs + TIR_PIEN) | 0x1);
305 
306 	/* Hook up the cascade interrupt to the iic and nodeid */
307 	virq = spider_find_cascade_and_node(pic);
308 	if (!virq)
309 		return;
310 	irq_set_handler_data(virq, pic);
311 	irq_set_chained_handler(virq, spider_irq_cascade);
312 
313 	printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %pOF\n",
314 	       pic->node_id, addr, of_node);
315 
316 	/* Enable the interrupt detection enable bit. Do this last! */
317 	out_be32(pic->regs + TIR_DEN, in_be32(pic->regs + TIR_DEN) | 0x1);
318 }
319 
320 void __init spider_init_IRQ(void)
321 {
322 	struct resource r;
323 	struct device_node *dn;
324 	int chip = 0;
325 
326 	/* XXX node numbers are totally bogus. We _hope_ we get the device
327 	 * nodes in the right order here but that's definitely not guaranteed,
328 	 * we need to get the node from the device tree instead.
329 	 * There is currently no proper property for it (but our whole
330 	 * device-tree is bogus anyway) so all we can do is pray or maybe test
331 	 * the address and deduce the node-id
332 	 */
333 	for_each_node_by_name(dn, "interrupt-controller") {
334 		if (of_device_is_compatible(dn, "CBEA,platform-spider-pic")) {
335 			if (of_address_to_resource(dn, 0, &r)) {
336 				printk(KERN_WARNING "spider-pic: Failed\n");
337 				continue;
338 			}
339 		} else if (of_device_is_compatible(dn, "sti,platform-spider-pic")
340 			   && (chip < 2)) {
341 			static long hard_coded_pics[] =
342 				{ 0x24000008000ul, 0x34000008000ul};
343 			r.start = hard_coded_pics[chip];
344 		} else
345 			continue;
346 		spider_init_one(dn, chip++, r.start);
347 	}
348 }
349