1 /* 2 * linux/arch/powerpc/platforms/cell/cell_setup.c 3 * 4 * Copyright (C) 1995 Linus Torvalds 5 * Adapted from 'alpha' version by Gary Thomas 6 * Modified by Cort Dougan (cort@cs.nmt.edu) 7 * Modified by PPC64 Team, IBM Corp 8 * Modified by Cell Team, IBM Deutschland Entwicklung GmbH 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 */ 15 #undef DEBUG 16 17 #include <linux/sched.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/stddef.h> 21 #include <linux/export.h> 22 #include <linux/unistd.h> 23 #include <linux/user.h> 24 #include <linux/reboot.h> 25 #include <linux/init.h> 26 #include <linux/delay.h> 27 #include <linux/irq.h> 28 #include <linux/seq_file.h> 29 #include <linux/root_dev.h> 30 #include <linux/console.h> 31 #include <linux/mutex.h> 32 #include <linux/memory_hotplug.h> 33 #include <linux/of_platform.h> 34 35 #include <asm/mmu.h> 36 #include <asm/processor.h> 37 #include <asm/io.h> 38 #include <asm/pgtable.h> 39 #include <asm/prom.h> 40 #include <asm/rtas.h> 41 #include <asm/pci-bridge.h> 42 #include <asm/iommu.h> 43 #include <asm/dma.h> 44 #include <asm/machdep.h> 45 #include <asm/time.h> 46 #include <asm/nvram.h> 47 #include <asm/cputable.h> 48 #include <asm/ppc-pci.h> 49 #include <asm/irq.h> 50 #include <asm/spu.h> 51 #include <asm/spu_priv1.h> 52 #include <asm/udbg.h> 53 #include <asm/mpic.h> 54 #include <asm/cell-regs.h> 55 #include <asm/io-workarounds.h> 56 57 #include "cell.h" 58 #include "interrupt.h" 59 #include "pervasive.h" 60 #include "ras.h" 61 62 #ifdef DEBUG 63 #define DBG(fmt...) udbg_printf(fmt) 64 #else 65 #define DBG(fmt...) 66 #endif 67 68 static void cell_show_cpuinfo(struct seq_file *m) 69 { 70 struct device_node *root; 71 const char *model = ""; 72 73 root = of_find_node_by_path("/"); 74 if (root) 75 model = of_get_property(root, "model", NULL); 76 seq_printf(m, "machine\t\t: CHRP %s\n", model); 77 of_node_put(root); 78 } 79 80 static void cell_progress(char *s, unsigned short hex) 81 { 82 printk("*** %04x : %s\n", hex, s ? s : ""); 83 } 84 85 static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev) 86 { 87 struct pci_controller *hose; 88 const char *s; 89 int i; 90 91 if (!machine_is(cell)) 92 return; 93 94 /* We're searching for a direct child of the PHB */ 95 if (dev->bus->self != NULL || dev->devfn != 0) 96 return; 97 98 hose = pci_bus_to_host(dev->bus); 99 if (hose == NULL) 100 return; 101 102 /* Only on PCIE */ 103 if (!of_device_is_compatible(hose->dn, "pciex")) 104 return; 105 106 /* And only on axon */ 107 s = of_get_property(hose->dn, "model", NULL); 108 if (!s || strcmp(s, "Axon") != 0) 109 return; 110 111 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 112 dev->resource[i].start = dev->resource[i].end = 0; 113 dev->resource[i].flags = 0; 114 } 115 116 printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n", 117 pci_name(dev)); 118 } 119 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex); 120 121 static int cell_setup_phb(struct pci_controller *phb) 122 { 123 const char *model; 124 struct device_node *np; 125 126 int rc = rtas_setup_phb(phb); 127 if (rc) 128 return rc; 129 130 phb->controller_ops = cell_pci_controller_ops; 131 132 np = phb->dn; 133 model = of_get_property(np, "model", NULL); 134 if (model == NULL || !of_node_name_eq(np, "pci")) 135 return 0; 136 137 /* Setup workarounds for spider */ 138 if (strcmp(model, "Spider")) 139 return 0; 140 141 iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init, 142 (void *)SPIDER_PCI_REG_BASE); 143 return 0; 144 } 145 146 static const struct of_device_id cell_bus_ids[] __initconst = { 147 { .type = "soc", }, 148 { .compatible = "soc", }, 149 { .type = "spider", }, 150 { .type = "axon", }, 151 { .type = "plb5", }, 152 { .type = "plb4", }, 153 { .type = "opb", }, 154 { .type = "ebc", }, 155 {}, 156 }; 157 158 static int __init cell_publish_devices(void) 159 { 160 struct device_node *root = of_find_node_by_path("/"); 161 struct device_node *np; 162 int node; 163 164 /* Publish OF platform devices for southbridge IOs */ 165 of_platform_bus_probe(NULL, cell_bus_ids, NULL); 166 167 /* On spider based blades, we need to manually create the OF 168 * platform devices for the PCI host bridges 169 */ 170 for_each_child_of_node(root, np) { 171 if (!of_node_is_type(np, "pci") && !of_node_is_type(np, "pciex")) 172 continue; 173 of_platform_device_create(np, NULL, NULL); 174 } 175 176 /* There is no device for the MIC memory controller, thus we create 177 * a platform device for it to attach the EDAC driver to. 178 */ 179 for_each_online_node(node) { 180 if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL) 181 continue; 182 platform_device_register_simple("cbe-mic", node, NULL, 0); 183 } 184 185 return 0; 186 } 187 machine_subsys_initcall(cell, cell_publish_devices); 188 189 static void __init mpic_init_IRQ(void) 190 { 191 struct device_node *dn; 192 struct mpic *mpic; 193 194 for_each_node_by_name(dn, "interrupt-controller") { 195 if (!of_device_is_compatible(dn, "CBEA,platform-open-pic")) 196 continue; 197 198 /* The MPIC driver will get everything it needs from the 199 * device-tree, just pass 0 to all arguments 200 */ 201 mpic = mpic_alloc(dn, 0, MPIC_SECONDARY | MPIC_NO_RESET, 202 0, 0, " MPIC "); 203 if (mpic == NULL) 204 continue; 205 mpic_init(mpic); 206 } 207 } 208 209 210 static void __init cell_init_irq(void) 211 { 212 iic_init_IRQ(); 213 spider_init_IRQ(); 214 mpic_init_IRQ(); 215 } 216 217 static void __init cell_set_dabrx(void) 218 { 219 mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER); 220 } 221 222 static void __init cell_setup_arch(void) 223 { 224 #ifdef CONFIG_SPU_BASE 225 spu_priv1_ops = &spu_priv1_mmio_ops; 226 spu_management_ops = &spu_management_of_ops; 227 #endif 228 229 cbe_regs_init(); 230 231 cell_set_dabrx(); 232 233 #ifdef CONFIG_CBE_RAS 234 cbe_ras_init(); 235 #endif 236 237 #ifdef CONFIG_SMP 238 smp_init_cell(); 239 #endif 240 /* init to some ~sane value until calibrate_delay() runs */ 241 loops_per_jiffy = 50000000; 242 243 /* Find and initialize PCI host bridges */ 244 init_pci_config_tokens(); 245 246 cbe_pervasive_init(); 247 #ifdef CONFIG_DUMMY_CONSOLE 248 conswitchp = &dummy_con; 249 #endif 250 251 mmio_nvram_init(); 252 } 253 254 static int __init cell_probe(void) 255 { 256 if (!of_machine_is_compatible("IBM,CBEA") && 257 !of_machine_is_compatible("IBM,CPBW-1.0")) 258 return 0; 259 260 pm_power_off = rtas_power_off; 261 262 return 1; 263 } 264 265 define_machine(cell) { 266 .name = "Cell", 267 .probe = cell_probe, 268 .setup_arch = cell_setup_arch, 269 .show_cpuinfo = cell_show_cpuinfo, 270 .restart = rtas_restart, 271 .halt = rtas_halt, 272 .get_boot_time = rtas_get_boot_time, 273 .get_rtc_time = rtas_get_rtc_time, 274 .set_rtc_time = rtas_set_rtc_time, 275 .calibrate_decr = generic_calibrate_decr, 276 .progress = cell_progress, 277 .init_IRQ = cell_init_irq, 278 .pci_setup_phb = cell_setup_phb, 279 }; 280 281 struct pci_controller_ops cell_pci_controller_ops; 282