1 /*
2  *  linux/arch/powerpc/platforms/cell/cell_setup.c
3  *
4  *  Copyright (C) 1995  Linus Torvalds
5  *  Adapted from 'alpha' version by Gary Thomas
6  *  Modified by Cort Dougan (cort@cs.nmt.edu)
7  *  Modified by PPC64 Team, IBM Corp
8  *  Modified by Cell Team, IBM Deutschland Entwicklung GmbH
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License
12  * as published by the Free Software Foundation; either version
13  * 2 of the License, or (at your option) any later version.
14  */
15 #undef DEBUG
16 
17 #include <linux/sched.h>
18 #include <linux/kernel.h>
19 #include <linux/mm.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/slab.h>
23 #include <linux/user.h>
24 #include <linux/reboot.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/irq.h>
28 #include <linux/seq_file.h>
29 #include <linux/root_dev.h>
30 #include <linux/console.h>
31 #include <linux/mutex.h>
32 #include <linux/memory_hotplug.h>
33 #include <linux/of_platform.h>
34 
35 #include <asm/mmu.h>
36 #include <asm/processor.h>
37 #include <asm/io.h>
38 #include <asm/pgtable.h>
39 #include <asm/prom.h>
40 #include <asm/rtas.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/iommu.h>
43 #include <asm/dma.h>
44 #include <asm/machdep.h>
45 #include <asm/time.h>
46 #include <asm/nvram.h>
47 #include <asm/cputable.h>
48 #include <asm/ppc-pci.h>
49 #include <asm/irq.h>
50 #include <asm/spu.h>
51 #include <asm/spu_priv1.h>
52 #include <asm/udbg.h>
53 #include <asm/mpic.h>
54 #include <asm/cell-regs.h>
55 
56 #include "interrupt.h"
57 #include "pervasive.h"
58 #include "ras.h"
59 #include "io-workarounds.h"
60 
61 #ifdef DEBUG
62 #define DBG(fmt...) udbg_printf(fmt)
63 #else
64 #define DBG(fmt...)
65 #endif
66 
67 static void cell_show_cpuinfo(struct seq_file *m)
68 {
69 	struct device_node *root;
70 	const char *model = "";
71 
72 	root = of_find_node_by_path("/");
73 	if (root)
74 		model = of_get_property(root, "model", NULL);
75 	seq_printf(m, "machine\t\t: CHRP %s\n", model);
76 	of_node_put(root);
77 }
78 
79 static void cell_progress(char *s, unsigned short hex)
80 {
81 	printk("*** %04x : %s\n", hex, s ? s : "");
82 }
83 
84 static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev)
85 {
86 	struct pci_controller *hose;
87 	const char *s;
88 	int i;
89 
90 	if (!machine_is(cell))
91 		return;
92 
93 	/* We're searching for a direct child of the PHB */
94 	if (dev->bus->self != NULL || dev->devfn != 0)
95 		return;
96 
97 	hose = pci_bus_to_host(dev->bus);
98 	if (hose == NULL)
99 		return;
100 
101 	/* Only on PCIE */
102 	if (!of_device_is_compatible(hose->dn, "pciex"))
103 		return;
104 
105 	/* And only on axon */
106 	s = of_get_property(hose->dn, "model", NULL);
107 	if (!s || strcmp(s, "Axon") != 0)
108 		return;
109 
110 	for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
111 		dev->resource[i].start = dev->resource[i].end = 0;
112 		dev->resource[i].flags = 0;
113 	}
114 
115 	printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n",
116 	       pci_name(dev));
117 }
118 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex);
119 
120 static int __devinit cell_setup_phb(struct pci_controller *phb)
121 {
122 	const char *model;
123 	struct device_node *np;
124 
125 	int rc = rtas_setup_phb(phb);
126 	if (rc)
127 		return rc;
128 
129 	np = phb->dn;
130 	model = of_get_property(np, "model", NULL);
131 	if (model == NULL || strcmp(np->name, "pci"))
132 		return 0;
133 
134 	/* Setup workarounds for spider */
135 	if (strcmp(model, "Spider"))
136 		return 0;
137 
138 	iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init,
139 				  (void *)SPIDER_PCI_REG_BASE);
140 	io_workaround_init();
141 
142 	return 0;
143 }
144 
145 static int __init cell_publish_devices(void)
146 {
147 	struct device_node *root = of_find_node_by_path("/");
148 	struct device_node *np;
149 	int node;
150 
151 	/* Publish OF platform devices for southbridge IOs */
152 	of_platform_bus_probe(NULL, NULL, NULL);
153 
154 	/* On spider based blades, we need to manually create the OF
155 	 * platform devices for the PCI host bridges
156 	 */
157 	for_each_child_of_node(root, np) {
158 		if (np->type == NULL || (strcmp(np->type, "pci") != 0 &&
159 					 strcmp(np->type, "pciex") != 0))
160 			continue;
161 		of_platform_device_create(np, NULL, NULL);
162 	}
163 
164 	/* There is no device for the MIC memory controller, thus we create
165 	 * a platform device for it to attach the EDAC driver to.
166 	 */
167 	for_each_online_node(node) {
168 		if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
169 			continue;
170 		platform_device_register_simple("cbe-mic", node, NULL, 0);
171 	}
172 
173 	return 0;
174 }
175 machine_subsys_initcall(cell, cell_publish_devices);
176 
177 static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc)
178 {
179 	struct mpic *mpic = desc->handler_data;
180 	unsigned int virq;
181 
182 	virq = mpic_get_one_irq(mpic);
183 	if (virq != NO_IRQ)
184 		generic_handle_irq(virq);
185 	desc->chip->eoi(irq);
186 }
187 
188 static void __init mpic_init_IRQ(void)
189 {
190 	struct device_node *dn;
191 	struct mpic *mpic;
192 	unsigned int virq;
193 
194 	for (dn = NULL;
195 	     (dn = of_find_node_by_name(dn, "interrupt-controller"));) {
196 		if (!of_device_is_compatible(dn, "CBEA,platform-open-pic"))
197 			continue;
198 
199 		/* The MPIC driver will get everything it needs from the
200 		 * device-tree, just pass 0 to all arguments
201 		 */
202 		mpic = mpic_alloc(dn, 0, 0, 0, 0, " MPIC     ");
203 		if (mpic == NULL)
204 			continue;
205 		mpic_init(mpic);
206 
207 		virq = irq_of_parse_and_map(dn, 0);
208 		if (virq == NO_IRQ)
209 			continue;
210 
211 		printk(KERN_INFO "%s : hooking up to IRQ %d\n",
212 		       dn->full_name, virq);
213 		set_irq_data(virq, mpic);
214 		set_irq_chained_handler(virq, cell_mpic_cascade);
215 	}
216 }
217 
218 
219 static void __init cell_init_irq(void)
220 {
221 	iic_init_IRQ();
222 	spider_init_IRQ();
223 	mpic_init_IRQ();
224 }
225 
226 static void __init cell_set_dabrx(void)
227 {
228 	mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
229 }
230 
231 static void __init cell_setup_arch(void)
232 {
233 #ifdef CONFIG_SPU_BASE
234 	spu_priv1_ops = &spu_priv1_mmio_ops;
235 	spu_management_ops = &spu_management_of_ops;
236 #endif
237 
238 	cbe_regs_init();
239 
240 	cell_set_dabrx();
241 
242 #ifdef CONFIG_CBE_RAS
243 	cbe_ras_init();
244 #endif
245 
246 #ifdef CONFIG_SMP
247 	smp_init_cell();
248 #endif
249 	/* init to some ~sane value until calibrate_delay() runs */
250 	loops_per_jiffy = 50000000;
251 
252 	/* Find and initialize PCI host bridges */
253 	init_pci_config_tokens();
254 
255 	cbe_pervasive_init();
256 #ifdef CONFIG_DUMMY_CONSOLE
257 	conswitchp = &dummy_con;
258 #endif
259 
260 	mmio_nvram_init();
261 }
262 
263 static int __init cell_probe(void)
264 {
265 	unsigned long root = of_get_flat_dt_root();
266 
267 	if (!of_flat_dt_is_compatible(root, "IBM,CBEA") &&
268 	    !of_flat_dt_is_compatible(root, "IBM,CPBW-1.0"))
269 		return 0;
270 
271 	hpte_init_native();
272 
273 	return 1;
274 }
275 
276 define_machine(cell) {
277 	.name			= "Cell",
278 	.probe			= cell_probe,
279 	.setup_arch		= cell_setup_arch,
280 	.show_cpuinfo		= cell_show_cpuinfo,
281 	.restart		= rtas_restart,
282 	.power_off		= rtas_power_off,
283 	.halt			= rtas_halt,
284 	.get_boot_time		= rtas_get_boot_time,
285 	.get_rtc_time		= rtas_get_rtc_time,
286 	.set_rtc_time		= rtas_set_rtc_time,
287 	.calibrate_decr		= generic_calibrate_decr,
288 	.progress		= cell_progress,
289 	.init_IRQ       	= cell_init_irq,
290 	.pci_setup_phb		= cell_setup_phb,
291 };
292