1 /* 2 * linux/arch/powerpc/platforms/cell/cell_setup.c 3 * 4 * Copyright (C) 1995 Linus Torvalds 5 * Adapted from 'alpha' version by Gary Thomas 6 * Modified by Cort Dougan (cort@cs.nmt.edu) 7 * Modified by PPC64 Team, IBM Corp 8 * Modified by Cell Team, IBM Deutschland Entwicklung GmbH 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * as published by the Free Software Foundation; either version 13 * 2 of the License, or (at your option) any later version. 14 */ 15 #undef DEBUG 16 17 #include <linux/sched.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/user.h> 23 #include <linux/reboot.h> 24 #include <linux/init.h> 25 #include <linux/delay.h> 26 #include <linux/irq.h> 27 #include <linux/seq_file.h> 28 #include <linux/root_dev.h> 29 #include <linux/console.h> 30 #include <linux/mutex.h> 31 #include <linux/memory_hotplug.h> 32 #include <linux/of_platform.h> 33 34 #include <asm/mmu.h> 35 #include <asm/processor.h> 36 #include <asm/io.h> 37 #include <asm/pgtable.h> 38 #include <asm/prom.h> 39 #include <asm/rtas.h> 40 #include <asm/pci-bridge.h> 41 #include <asm/iommu.h> 42 #include <asm/dma.h> 43 #include <asm/machdep.h> 44 #include <asm/time.h> 45 #include <asm/nvram.h> 46 #include <asm/cputable.h> 47 #include <asm/ppc-pci.h> 48 #include <asm/irq.h> 49 #include <asm/spu.h> 50 #include <asm/spu_priv1.h> 51 #include <asm/udbg.h> 52 #include <asm/mpic.h> 53 #include <asm/cell-regs.h> 54 55 #include "interrupt.h" 56 #include "pervasive.h" 57 #include "ras.h" 58 #include "io-workarounds.h" 59 60 #ifdef DEBUG 61 #define DBG(fmt...) udbg_printf(fmt) 62 #else 63 #define DBG(fmt...) 64 #endif 65 66 static void cell_show_cpuinfo(struct seq_file *m) 67 { 68 struct device_node *root; 69 const char *model = ""; 70 71 root = of_find_node_by_path("/"); 72 if (root) 73 model = of_get_property(root, "model", NULL); 74 seq_printf(m, "machine\t\t: CHRP %s\n", model); 75 of_node_put(root); 76 } 77 78 static void cell_progress(char *s, unsigned short hex) 79 { 80 printk("*** %04x : %s\n", hex, s ? s : ""); 81 } 82 83 static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev) 84 { 85 struct pci_controller *hose; 86 const char *s; 87 int i; 88 89 if (!machine_is(cell)) 90 return; 91 92 /* We're searching for a direct child of the PHB */ 93 if (dev->bus->self != NULL || dev->devfn != 0) 94 return; 95 96 hose = pci_bus_to_host(dev->bus); 97 if (hose == NULL) 98 return; 99 100 /* Only on PCIE */ 101 if (!of_device_is_compatible(hose->dn, "pciex")) 102 return; 103 104 /* And only on axon */ 105 s = of_get_property(hose->dn, "model", NULL); 106 if (!s || strcmp(s, "Axon") != 0) 107 return; 108 109 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 110 dev->resource[i].start = dev->resource[i].end = 0; 111 dev->resource[i].flags = 0; 112 } 113 114 printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n", 115 pci_name(dev)); 116 } 117 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex); 118 119 static int __devinit cell_setup_phb(struct pci_controller *phb) 120 { 121 const char *model; 122 struct device_node *np; 123 124 int rc = rtas_setup_phb(phb); 125 if (rc) 126 return rc; 127 128 np = phb->dn; 129 model = of_get_property(np, "model", NULL); 130 if (model == NULL || strcmp(np->name, "pci")) 131 return 0; 132 133 /* Setup workarounds for spider */ 134 if (strcmp(model, "Spider")) 135 return 0; 136 137 iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init, 138 (void *)SPIDER_PCI_REG_BASE); 139 io_workaround_init(); 140 141 return 0; 142 } 143 144 static const struct of_device_id cell_bus_ids[] __initdata = { 145 { .type = "soc", }, 146 { .compatible = "soc", }, 147 { .type = "spider", }, 148 { .type = "axon", }, 149 { .type = "plb5", }, 150 { .type = "plb4", }, 151 { .type = "opb", }, 152 { .type = "ebc", }, 153 {}, 154 }; 155 156 static int __init cell_publish_devices(void) 157 { 158 struct device_node *root = of_find_node_by_path("/"); 159 struct device_node *np; 160 int node; 161 162 /* Publish OF platform devices for southbridge IOs */ 163 of_platform_bus_probe(NULL, cell_bus_ids, NULL); 164 165 /* On spider based blades, we need to manually create the OF 166 * platform devices for the PCI host bridges 167 */ 168 for_each_child_of_node(root, np) { 169 if (np->type == NULL || (strcmp(np->type, "pci") != 0 && 170 strcmp(np->type, "pciex") != 0)) 171 continue; 172 of_platform_device_create(np, NULL, NULL); 173 } 174 175 /* There is no device for the MIC memory controller, thus we create 176 * a platform device for it to attach the EDAC driver to. 177 */ 178 for_each_online_node(node) { 179 if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL) 180 continue; 181 platform_device_register_simple("cbe-mic", node, NULL, 0); 182 } 183 184 return 0; 185 } 186 machine_subsys_initcall(cell, cell_publish_devices); 187 188 static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc) 189 { 190 struct irq_chip *chip = get_irq_desc_chip(desc); 191 struct mpic *mpic = get_irq_desc_data(desc); 192 unsigned int virq; 193 194 virq = mpic_get_one_irq(mpic); 195 if (virq != NO_IRQ) 196 generic_handle_irq(virq); 197 198 chip->irq_eoi(&desc->irq_data); 199 } 200 201 static void __init mpic_init_IRQ(void) 202 { 203 struct device_node *dn; 204 struct mpic *mpic; 205 unsigned int virq; 206 207 for (dn = NULL; 208 (dn = of_find_node_by_name(dn, "interrupt-controller"));) { 209 if (!of_device_is_compatible(dn, "CBEA,platform-open-pic")) 210 continue; 211 212 /* The MPIC driver will get everything it needs from the 213 * device-tree, just pass 0 to all arguments 214 */ 215 mpic = mpic_alloc(dn, 0, 0, 0, 0, " MPIC "); 216 if (mpic == NULL) 217 continue; 218 mpic_init(mpic); 219 220 virq = irq_of_parse_and_map(dn, 0); 221 if (virq == NO_IRQ) 222 continue; 223 224 printk(KERN_INFO "%s : hooking up to IRQ %d\n", 225 dn->full_name, virq); 226 set_irq_data(virq, mpic); 227 set_irq_chained_handler(virq, cell_mpic_cascade); 228 } 229 } 230 231 232 static void __init cell_init_irq(void) 233 { 234 iic_init_IRQ(); 235 spider_init_IRQ(); 236 mpic_init_IRQ(); 237 } 238 239 static void __init cell_set_dabrx(void) 240 { 241 mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER); 242 } 243 244 static void __init cell_setup_arch(void) 245 { 246 #ifdef CONFIG_SPU_BASE 247 spu_priv1_ops = &spu_priv1_mmio_ops; 248 spu_management_ops = &spu_management_of_ops; 249 #endif 250 251 cbe_regs_init(); 252 253 cell_set_dabrx(); 254 255 #ifdef CONFIG_CBE_RAS 256 cbe_ras_init(); 257 #endif 258 259 #ifdef CONFIG_SMP 260 smp_init_cell(); 261 #endif 262 /* init to some ~sane value until calibrate_delay() runs */ 263 loops_per_jiffy = 50000000; 264 265 /* Find and initialize PCI host bridges */ 266 init_pci_config_tokens(); 267 268 cbe_pervasive_init(); 269 #ifdef CONFIG_DUMMY_CONSOLE 270 conswitchp = &dummy_con; 271 #endif 272 273 mmio_nvram_init(); 274 } 275 276 static int __init cell_probe(void) 277 { 278 unsigned long root = of_get_flat_dt_root(); 279 280 if (!of_flat_dt_is_compatible(root, "IBM,CBEA") && 281 !of_flat_dt_is_compatible(root, "IBM,CPBW-1.0")) 282 return 0; 283 284 hpte_init_native(); 285 286 return 1; 287 } 288 289 define_machine(cell) { 290 .name = "Cell", 291 .probe = cell_probe, 292 .setup_arch = cell_setup_arch, 293 .show_cpuinfo = cell_show_cpuinfo, 294 .restart = rtas_restart, 295 .power_off = rtas_power_off, 296 .halt = rtas_halt, 297 .get_boot_time = rtas_get_boot_time, 298 .get_rtc_time = rtas_get_rtc_time, 299 .set_rtc_time = rtas_set_rtc_time, 300 .calibrate_decr = generic_calibrate_decr, 301 .progress = cell_progress, 302 .init_IRQ = cell_init_irq, 303 .pci_setup_phb = cell_setup_phb, 304 }; 305