1 /*
2  * CBE Pervasive Monitor and Debug
3  *
4  * (C) Copyright IBM Corporation 2005
5  *
6  * Authors: Maximino Aguilar (maguilar@us.ibm.com)
7  *          Michael N. Day (mnday@us.ibm.com)
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2, or (at your option)
12  * any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22  */
23 
24 #undef DEBUG
25 
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/percpu.h>
29 #include <linux/types.h>
30 #include <linux/kallsyms.h>
31 
32 #include <asm/io.h>
33 #include <asm/machdep.h>
34 #include <asm/prom.h>
35 #include <asm/pgtable.h>
36 #include <asm/reg.h>
37 #include <asm/cell-regs.h>
38 #include <asm/cpu_has_feature.h>
39 
40 #include "pervasive.h"
41 
42 static void cbe_power_save(void)
43 {
44 	unsigned long ctrl, thread_switch_control;
45 
46 	/* Ensure our interrupt state is properly tracked */
47 	if (!prep_irq_for_idle())
48 		return;
49 
50 	ctrl = mfspr(SPRN_CTRLF);
51 
52 	/* Enable DEC and EE interrupt request */
53 	thread_switch_control  = mfspr(SPRN_TSC_CELL);
54 	thread_switch_control |= TSC_CELL_EE_ENABLE | TSC_CELL_EE_BOOST;
55 
56 	switch (ctrl & CTRL_CT) {
57 	case CTRL_CT0:
58 		thread_switch_control |= TSC_CELL_DEC_ENABLE_0;
59 		break;
60 	case CTRL_CT1:
61 		thread_switch_control |= TSC_CELL_DEC_ENABLE_1;
62 		break;
63 	default:
64 		printk(KERN_WARNING "%s: unknown configuration\n",
65 			__func__);
66 		break;
67 	}
68 	mtspr(SPRN_TSC_CELL, thread_switch_control);
69 
70 	/*
71 	 * go into low thread priority, medium priority will be
72 	 * restored for us after wake-up.
73 	 */
74 	HMT_low();
75 
76 	/*
77 	 * atomically disable thread execution and runlatch.
78 	 * External and Decrementer exceptions are still handled when the
79 	 * thread is disabled but now enter in cbe_system_reset_exception()
80 	 */
81 	ctrl &= ~(CTRL_RUNLATCH | CTRL_TE);
82 	mtspr(SPRN_CTRLT, ctrl);
83 
84 	/* Re-enable interrupts in MSR */
85 	__hard_irq_enable();
86 }
87 
88 static int cbe_system_reset_exception(struct pt_regs *regs)
89 {
90 	switch (regs->msr & SRR1_WAKEMASK) {
91 	case SRR1_WAKEDEC:
92 		set_dec(1);
93 	case SRR1_WAKEEE:
94 		/*
95 		 * Handle these when interrupts get re-enabled and we take
96 		 * them as regular exceptions. We are in an NMI context
97 		 * and can't handle these here.
98 		 */
99 		break;
100 	case SRR1_WAKEMT:
101 		return cbe_sysreset_hack();
102 #ifdef CONFIG_CBE_RAS
103 	case SRR1_WAKESYSERR:
104 		cbe_system_error_exception(regs);
105 		break;
106 	case SRR1_WAKETHERM:
107 		cbe_thermal_exception(regs);
108 		break;
109 #endif /* CONFIG_CBE_RAS */
110 	default:
111 		/* do system reset */
112 		return 0;
113 	}
114 	/* everything handled */
115 	return 1;
116 }
117 
118 void __init cbe_pervasive_init(void)
119 {
120 	int cpu;
121 
122 	if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
123 		return;
124 
125 	for_each_possible_cpu(cpu) {
126 		struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu);
127 		if (!regs)
128 			continue;
129 
130 		 /* Enable Pause(0) control bit */
131 		out_be64(&regs->pmcr, in_be64(&regs->pmcr) |
132 					    CBE_PMD_PAUSE_ZERO_CONTROL);
133 	}
134 
135 	ppc_md.power_save = cbe_power_save;
136 	ppc_md.system_reset_exception = cbe_system_reset_exception;
137 }
138