1de6cc651SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2c902be71SArnd Bergmann /* 3c902be71SArnd Bergmann * CBE Pervasive Monitor and Debug 4c902be71SArnd Bergmann * 5c902be71SArnd Bergmann * (C) Copyright IBM Corporation 2005 6c902be71SArnd Bergmann * 7c902be71SArnd Bergmann * Authors: Maximino Aguilar (maguilar@us.ibm.com) 8c902be71SArnd Bergmann * Michael N. Day (mnday@us.ibm.com) 9c902be71SArnd Bergmann */ 10c902be71SArnd Bergmann 11c902be71SArnd Bergmann #undef DEBUG 12c902be71SArnd Bergmann 13c902be71SArnd Bergmann #include <linux/interrupt.h> 14c902be71SArnd Bergmann #include <linux/irq.h> 15c902be71SArnd Bergmann #include <linux/percpu.h> 16c902be71SArnd Bergmann #include <linux/types.h> 17c902be71SArnd Bergmann #include <linux/kallsyms.h> 1865fddcfcSMike Rapoport #include <linux/pgtable.h> 19c902be71SArnd Bergmann 20c902be71SArnd Bergmann #include <asm/io.h> 21c902be71SArnd Bergmann #include <asm/machdep.h> 22c902be71SArnd Bergmann #include <asm/reg.h> 23eef686a0SBenjamin Herrenschmidt #include <asm/cell-regs.h> 24b92a226eSKevin Hao #include <asm/cpu_has_feature.h> 25c902be71SArnd Bergmann 26c902be71SArnd Bergmann #include "pervasive.h" 27dcdb4f12SNicholas Piggin #include "ras.h" 28c902be71SArnd Bergmann cbe_power_save(void)29302eca18Sarnd@arndb.destatic void cbe_power_save(void) 30c902be71SArnd Bergmann { 31302eca18Sarnd@arndb.de unsigned long ctrl, thread_switch_control; 325850dd8fSBenjamin Herrenschmidt 33be2cf20aSBenjamin Herrenschmidt /* Ensure our interrupt state is properly tracked */ 34be2cf20aSBenjamin Herrenschmidt if (!prep_irq_for_idle()) 35be2cf20aSBenjamin Herrenschmidt return; 365850dd8fSBenjamin Herrenschmidt 37302eca18Sarnd@arndb.de ctrl = mfspr(SPRN_CTRLF); 38c902be71SArnd Bergmann 39c902be71SArnd Bergmann /* Enable DEC and EE interrupt request */ 40c902be71SArnd Bergmann thread_switch_control = mfspr(SPRN_TSC_CELL); 41c902be71SArnd Bergmann thread_switch_control |= TSC_CELL_EE_ENABLE | TSC_CELL_EE_BOOST; 42c902be71SArnd Bergmann 43302eca18Sarnd@arndb.de switch (ctrl & CTRL_CT) { 44c902be71SArnd Bergmann case CTRL_CT0: 45c902be71SArnd Bergmann thread_switch_control |= TSC_CELL_DEC_ENABLE_0; 46c902be71SArnd Bergmann break; 47c902be71SArnd Bergmann case CTRL_CT1: 48c902be71SArnd Bergmann thread_switch_control |= TSC_CELL_DEC_ENABLE_1; 49c902be71SArnd Bergmann break; 50c902be71SArnd Bergmann default: 51c902be71SArnd Bergmann printk(KERN_WARNING "%s: unknown configuration\n", 52e48b1b45SHarvey Harrison __func__); 53c902be71SArnd Bergmann break; 54c902be71SArnd Bergmann } 55c902be71SArnd Bergmann mtspr(SPRN_TSC_CELL, thread_switch_control); 56c902be71SArnd Bergmann 57302eca18Sarnd@arndb.de /* 58302eca18Sarnd@arndb.de * go into low thread priority, medium priority will be 59302eca18Sarnd@arndb.de * restored for us after wake-up. 60acf7d768SBenjamin Herrenschmidt */ 61c902be71SArnd Bergmann HMT_low(); 62c902be71SArnd Bergmann 63c902be71SArnd Bergmann /* 64302eca18Sarnd@arndb.de * atomically disable thread execution and runlatch. 65302eca18Sarnd@arndb.de * External and Decrementer exceptions are still handled when the 66302eca18Sarnd@arndb.de * thread is disabled but now enter in cbe_system_reset_exception() 67c902be71SArnd Bergmann */ 68c902be71SArnd Bergmann ctrl &= ~(CTRL_RUNLATCH | CTRL_TE); 69c902be71SArnd Bergmann mtspr(SPRN_CTRLT, ctrl); 70be2cf20aSBenjamin Herrenschmidt 71be2cf20aSBenjamin Herrenschmidt /* Re-enable interrupts in MSR */ 72be2cf20aSBenjamin Herrenschmidt __hard_irq_enable(); 73c902be71SArnd Bergmann } 74c902be71SArnd Bergmann cbe_system_reset_exception(struct pt_regs * regs)758fce10a3SArnd Bergmannstatic int cbe_system_reset_exception(struct pt_regs *regs) 76c902be71SArnd Bergmann { 77c902be71SArnd Bergmann switch (regs->msr & SRR1_WAKEMASK) { 78c902be71SArnd Bergmann case SRR1_WAKEDEC: 796e83985bSNicholas Piggin set_dec(1); 80*e89257e2SAnders Roxell break; 816e83985bSNicholas Piggin case SRR1_WAKEEE: 826e83985bSNicholas Piggin /* 836e83985bSNicholas Piggin * Handle these when interrupts get re-enabled and we take 846e83985bSNicholas Piggin * them as regular exceptions. We are in an NMI context 856e83985bSNicholas Piggin * and can't handle these here. 866e83985bSNicholas Piggin */ 87c902be71SArnd Bergmann break; 88c902be71SArnd Bergmann case SRR1_WAKEMT: 8970694a8bSChristian Krafft return cbe_sysreset_hack(); 90acf7d768SBenjamin Herrenschmidt #ifdef CONFIG_CBE_RAS 91acf7d768SBenjamin Herrenschmidt case SRR1_WAKESYSERR: 92acf7d768SBenjamin Herrenschmidt cbe_system_error_exception(regs); 93acf7d768SBenjamin Herrenschmidt break; 94acf7d768SBenjamin Herrenschmidt case SRR1_WAKETHERM: 95acf7d768SBenjamin Herrenschmidt cbe_thermal_exception(regs); 96acf7d768SBenjamin Herrenschmidt break; 97acf7d768SBenjamin Herrenschmidt #endif /* CONFIG_CBE_RAS */ 98c902be71SArnd Bergmann default: 99c902be71SArnd Bergmann /* do system reset */ 100c902be71SArnd Bergmann return 0; 101c902be71SArnd Bergmann } 102c902be71SArnd Bergmann /* everything handled */ 103c902be71SArnd Bergmann return 1; 104c902be71SArnd Bergmann } 105c902be71SArnd Bergmann cbe_pervasive_init(void)106acf7d768SBenjamin Herrenschmidtvoid __init cbe_pervasive_init(void) 107c902be71SArnd Bergmann { 108302eca18Sarnd@arndb.de int cpu; 1093addf55cSArnd Bergmann 110c902be71SArnd Bergmann if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO)) 111c902be71SArnd Bergmann return; 112c902be71SArnd Bergmann 113302eca18Sarnd@arndb.de for_each_possible_cpu(cpu) { 114302eca18Sarnd@arndb.de struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu); 115302eca18Sarnd@arndb.de if (!regs) 116302eca18Sarnd@arndb.de continue; 117302eca18Sarnd@arndb.de 118302eca18Sarnd@arndb.de /* Enable Pause(0) control bit */ 119302eca18Sarnd@arndb.de out_be64(®s->pmcr, in_be64(®s->pmcr) | 120302eca18Sarnd@arndb.de CBE_PMD_PAUSE_ZERO_CONTROL); 121302eca18Sarnd@arndb.de } 122302eca18Sarnd@arndb.de 123302eca18Sarnd@arndb.de ppc_md.power_save = cbe_power_save; 124c902be71SArnd Bergmann ppc_md.system_reset_exception = cbe_system_reset_exception; 125c902be71SArnd Bergmann } 126