1 /* 2 * IOMMU implementation for Cell Broadband Processor Architecture 3 * 4 * (C) Copyright IBM Corporation 2006-2008 5 * 6 * Author: Jeremy Kerr <jk@ozlabs.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #undef DEBUG 24 25 #include <linux/kernel.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/notifier.h> 29 #include <linux/of.h> 30 #include <linux/of_platform.h> 31 32 #include <asm/prom.h> 33 #include <asm/iommu.h> 34 #include <asm/machdep.h> 35 #include <asm/pci-bridge.h> 36 #include <asm/udbg.h> 37 #include <asm/lmb.h> 38 #include <asm/firmware.h> 39 #include <asm/cell-regs.h> 40 41 #include "interrupt.h" 42 43 /* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages 44 * instead of leaving them mapped to some dummy page. This can be 45 * enabled once the appropriate workarounds for spider bugs have 46 * been enabled 47 */ 48 #define CELL_IOMMU_REAL_UNMAP 49 50 /* Define CELL_IOMMU_STRICT_PROTECTION to enforce protection of 51 * IO PTEs based on the transfer direction. That can be enabled 52 * once spider-net has been fixed to pass the correct direction 53 * to the DMA mapping functions 54 */ 55 #define CELL_IOMMU_STRICT_PROTECTION 56 57 58 #define NR_IOMMUS 2 59 60 /* IOC mmap registers */ 61 #define IOC_Reg_Size 0x2000 62 63 #define IOC_IOPT_CacheInvd 0x908 64 #define IOC_IOPT_CacheInvd_NE_Mask 0xffe0000000000000ul 65 #define IOC_IOPT_CacheInvd_IOPTE_Mask 0x000003fffffffff8ul 66 #define IOC_IOPT_CacheInvd_Busy 0x0000000000000001ul 67 68 #define IOC_IOST_Origin 0x918 69 #define IOC_IOST_Origin_E 0x8000000000000000ul 70 #define IOC_IOST_Origin_HW 0x0000000000000800ul 71 #define IOC_IOST_Origin_HL 0x0000000000000400ul 72 73 #define IOC_IO_ExcpStat 0x920 74 #define IOC_IO_ExcpStat_V 0x8000000000000000ul 75 #define IOC_IO_ExcpStat_SPF_Mask 0x6000000000000000ul 76 #define IOC_IO_ExcpStat_SPF_S 0x6000000000000000ul 77 #define IOC_IO_ExcpStat_SPF_P 0x4000000000000000ul 78 #define IOC_IO_ExcpStat_ADDR_Mask 0x00000007fffff000ul 79 #define IOC_IO_ExcpStat_RW_Mask 0x0000000000000800ul 80 #define IOC_IO_ExcpStat_IOID_Mask 0x00000000000007fful 81 82 #define IOC_IO_ExcpMask 0x928 83 #define IOC_IO_ExcpMask_SFE 0x4000000000000000ul 84 #define IOC_IO_ExcpMask_PFE 0x2000000000000000ul 85 86 #define IOC_IOCmd_Offset 0x1000 87 88 #define IOC_IOCmd_Cfg 0xc00 89 #define IOC_IOCmd_Cfg_TE 0x0000800000000000ul 90 91 92 /* Segment table entries */ 93 #define IOSTE_V 0x8000000000000000ul /* valid */ 94 #define IOSTE_H 0x4000000000000000ul /* cache hint */ 95 #define IOSTE_PT_Base_RPN_Mask 0x3ffffffffffff000ul /* base RPN of IOPT */ 96 #define IOSTE_NPPT_Mask 0x0000000000000fe0ul /* no. pages in IOPT */ 97 #define IOSTE_PS_Mask 0x0000000000000007ul /* page size */ 98 #define IOSTE_PS_4K 0x0000000000000001ul /* - 4kB */ 99 #define IOSTE_PS_64K 0x0000000000000003ul /* - 64kB */ 100 #define IOSTE_PS_1M 0x0000000000000005ul /* - 1MB */ 101 #define IOSTE_PS_16M 0x0000000000000007ul /* - 16MB */ 102 103 /* Page table entries */ 104 #define IOPTE_PP_W 0x8000000000000000ul /* protection: write */ 105 #define IOPTE_PP_R 0x4000000000000000ul /* protection: read */ 106 #define IOPTE_M 0x2000000000000000ul /* coherency required */ 107 #define IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */ 108 #define IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */ 109 #define IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */ 110 #define IOPTE_H 0x0000000000000800ul /* cache hint */ 111 #define IOPTE_IOID_Mask 0x00000000000007fful /* ioid */ 112 113 114 /* IOMMU sizing */ 115 #define IO_SEGMENT_SHIFT 28 116 #define IO_PAGENO_BITS(shift) (IO_SEGMENT_SHIFT - (shift)) 117 118 /* The high bit needs to be set on every DMA address */ 119 #define SPIDER_DMA_OFFSET 0x80000000ul 120 121 struct iommu_window { 122 struct list_head list; 123 struct cbe_iommu *iommu; 124 unsigned long offset; 125 unsigned long size; 126 unsigned int ioid; 127 struct iommu_table table; 128 }; 129 130 #define NAMESIZE 8 131 struct cbe_iommu { 132 int nid; 133 char name[NAMESIZE]; 134 void __iomem *xlate_regs; 135 void __iomem *cmd_regs; 136 unsigned long *stab; 137 unsigned long *ptab; 138 void *pad_page; 139 struct list_head windows; 140 }; 141 142 /* Static array of iommus, one per node 143 * each contains a list of windows, keyed from dma_window property 144 * - on bus setup, look for a matching window, or create one 145 * - on dev setup, assign iommu_table ptr 146 */ 147 static struct cbe_iommu iommus[NR_IOMMUS]; 148 static int cbe_nr_iommus; 149 150 static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte, 151 long n_ptes) 152 { 153 unsigned long __iomem *reg; 154 unsigned long val; 155 long n; 156 157 reg = iommu->xlate_regs + IOC_IOPT_CacheInvd; 158 159 while (n_ptes > 0) { 160 /* we can invalidate up to 1 << 11 PTEs at once */ 161 n = min(n_ptes, 1l << 11); 162 val = (((n /*- 1*/) << 53) & IOC_IOPT_CacheInvd_NE_Mask) 163 | (__pa(pte) & IOC_IOPT_CacheInvd_IOPTE_Mask) 164 | IOC_IOPT_CacheInvd_Busy; 165 166 out_be64(reg, val); 167 while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy) 168 ; 169 170 n_ptes -= n; 171 pte += n; 172 } 173 } 174 175 static void tce_build_cell(struct iommu_table *tbl, long index, long npages, 176 unsigned long uaddr, enum dma_data_direction direction) 177 { 178 int i; 179 unsigned long *io_pte, base_pte; 180 struct iommu_window *window = 181 container_of(tbl, struct iommu_window, table); 182 183 /* implementing proper protection causes problems with the spidernet 184 * driver - check mapping directions later, but allow read & write by 185 * default for now.*/ 186 #ifdef CELL_IOMMU_STRICT_PROTECTION 187 /* to avoid referencing a global, we use a trick here to setup the 188 * protection bit. "prot" is setup to be 3 fields of 4 bits apprended 189 * together for each of the 3 supported direction values. It is then 190 * shifted left so that the fields matching the desired direction 191 * lands on the appropriate bits, and other bits are masked out. 192 */ 193 const unsigned long prot = 0xc48; 194 base_pte = 195 ((prot << (52 + 4 * direction)) & (IOPTE_PP_W | IOPTE_PP_R)) 196 | IOPTE_M | IOPTE_SO_RW | (window->ioid & IOPTE_IOID_Mask); 197 #else 198 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | 199 (window->ioid & IOPTE_IOID_Mask); 200 #endif 201 202 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); 203 204 for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE) 205 io_pte[i] = base_pte | (__pa(uaddr) & IOPTE_RPN_Mask); 206 207 mb(); 208 209 invalidate_tce_cache(window->iommu, io_pte, npages); 210 211 pr_debug("tce_build_cell(index=%lx,n=%lx,dir=%d,base_pte=%lx)\n", 212 index, npages, direction, base_pte); 213 } 214 215 static void tce_free_cell(struct iommu_table *tbl, long index, long npages) 216 { 217 218 int i; 219 unsigned long *io_pte, pte; 220 struct iommu_window *window = 221 container_of(tbl, struct iommu_window, table); 222 223 pr_debug("tce_free_cell(index=%lx,n=%lx)\n", index, npages); 224 225 #ifdef CELL_IOMMU_REAL_UNMAP 226 pte = 0; 227 #else 228 /* spider bridge does PCI reads after freeing - insert a mapping 229 * to a scratch page instead of an invalid entry */ 230 pte = IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | __pa(window->iommu->pad_page) 231 | (window->ioid & IOPTE_IOID_Mask); 232 #endif 233 234 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); 235 236 for (i = 0; i < npages; i++) 237 io_pte[i] = pte; 238 239 mb(); 240 241 invalidate_tce_cache(window->iommu, io_pte, npages); 242 } 243 244 static irqreturn_t ioc_interrupt(int irq, void *data) 245 { 246 unsigned long stat; 247 struct cbe_iommu *iommu = data; 248 249 stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); 250 251 /* Might want to rate limit it */ 252 printk(KERN_ERR "iommu: DMA exception 0x%016lx\n", stat); 253 printk(KERN_ERR " V=%d, SPF=[%c%c], RW=%s, IOID=0x%04x\n", 254 !!(stat & IOC_IO_ExcpStat_V), 255 (stat & IOC_IO_ExcpStat_SPF_S) ? 'S' : ' ', 256 (stat & IOC_IO_ExcpStat_SPF_P) ? 'P' : ' ', 257 (stat & IOC_IO_ExcpStat_RW_Mask) ? "Read" : "Write", 258 (unsigned int)(stat & IOC_IO_ExcpStat_IOID_Mask)); 259 printk(KERN_ERR " page=0x%016lx\n", 260 stat & IOC_IO_ExcpStat_ADDR_Mask); 261 262 /* clear interrupt */ 263 stat &= ~IOC_IO_ExcpStat_V; 264 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat); 265 266 return IRQ_HANDLED; 267 } 268 269 static int cell_iommu_find_ioc(int nid, unsigned long *base) 270 { 271 struct device_node *np; 272 struct resource r; 273 274 *base = 0; 275 276 /* First look for new style /be nodes */ 277 for_each_node_by_name(np, "ioc") { 278 if (of_node_to_nid(np) != nid) 279 continue; 280 if (of_address_to_resource(np, 0, &r)) { 281 printk(KERN_ERR "iommu: can't get address for %s\n", 282 np->full_name); 283 continue; 284 } 285 *base = r.start; 286 of_node_put(np); 287 return 0; 288 } 289 290 /* Ok, let's try the old way */ 291 for_each_node_by_type(np, "cpu") { 292 const unsigned int *nidp; 293 const unsigned long *tmp; 294 295 nidp = of_get_property(np, "node-id", NULL); 296 if (nidp && *nidp == nid) { 297 tmp = of_get_property(np, "ioc-translation", NULL); 298 if (tmp) { 299 *base = *tmp; 300 of_node_put(np); 301 return 0; 302 } 303 } 304 } 305 306 return -ENODEV; 307 } 308 309 static void cell_iommu_setup_stab(struct cbe_iommu *iommu, 310 unsigned long dbase, unsigned long dsize, 311 unsigned long fbase, unsigned long fsize) 312 { 313 struct page *page; 314 unsigned long segments, stab_size; 315 316 segments = max(dbase + dsize, fbase + fsize) >> IO_SEGMENT_SHIFT; 317 318 pr_debug("%s: iommu[%d]: segments: %lu\n", 319 __FUNCTION__, iommu->nid, segments); 320 321 /* set up the segment table */ 322 stab_size = segments * sizeof(unsigned long); 323 page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(stab_size)); 324 BUG_ON(!page); 325 iommu->stab = page_address(page); 326 memset(iommu->stab, 0, stab_size); 327 } 328 329 static unsigned long *cell_iommu_alloc_ptab(struct cbe_iommu *iommu, 330 unsigned long base, unsigned long size, unsigned long gap_base, 331 unsigned long gap_size, unsigned long page_shift) 332 { 333 struct page *page; 334 int i; 335 unsigned long reg, segments, pages_per_segment, ptab_size, 336 n_pte_pages, start_seg, *ptab; 337 338 start_seg = base >> IO_SEGMENT_SHIFT; 339 segments = size >> IO_SEGMENT_SHIFT; 340 pages_per_segment = 1ull << IO_PAGENO_BITS(page_shift); 341 /* PTEs for each segment must start on a 4K bounday */ 342 pages_per_segment = max(pages_per_segment, 343 (1 << 12) / sizeof(unsigned long)); 344 345 ptab_size = segments * pages_per_segment * sizeof(unsigned long); 346 pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __FUNCTION__, 347 iommu->nid, ptab_size, get_order(ptab_size)); 348 page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size)); 349 BUG_ON(!page); 350 351 ptab = page_address(page); 352 memset(ptab, 0, ptab_size); 353 354 /* number of 4K pages needed for a page table */ 355 n_pte_pages = (pages_per_segment * sizeof(unsigned long)) >> 12; 356 357 pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n", 358 __FUNCTION__, iommu->nid, iommu->stab, ptab, 359 n_pte_pages); 360 361 /* initialise the STEs */ 362 reg = IOSTE_V | ((n_pte_pages - 1) << 5); 363 364 switch (page_shift) { 365 case 12: reg |= IOSTE_PS_4K; break; 366 case 16: reg |= IOSTE_PS_64K; break; 367 case 20: reg |= IOSTE_PS_1M; break; 368 case 24: reg |= IOSTE_PS_16M; break; 369 default: BUG(); 370 } 371 372 gap_base = gap_base >> IO_SEGMENT_SHIFT; 373 gap_size = gap_size >> IO_SEGMENT_SHIFT; 374 375 pr_debug("Setting up IOMMU stab:\n"); 376 for (i = start_seg; i < (start_seg + segments); i++) { 377 if (i >= gap_base && i < (gap_base + gap_size)) { 378 pr_debug("\toverlap at %d, skipping\n", i); 379 continue; 380 } 381 iommu->stab[i] = reg | (__pa(ptab) + (n_pte_pages << 12) * 382 (i - start_seg)); 383 pr_debug("\t[%d] 0x%016lx\n", i, iommu->stab[i]); 384 } 385 386 return ptab; 387 } 388 389 static void cell_iommu_enable_hardware(struct cbe_iommu *iommu) 390 { 391 int ret; 392 unsigned long reg, xlate_base; 393 unsigned int virq; 394 395 if (cell_iommu_find_ioc(iommu->nid, &xlate_base)) 396 panic("%s: missing IOC register mappings for node %d\n", 397 __FUNCTION__, iommu->nid); 398 399 iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size); 400 iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset; 401 402 /* ensure that the STEs have updated */ 403 mb(); 404 405 /* setup interrupts for the iommu. */ 406 reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); 407 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, 408 reg & ~IOC_IO_ExcpStat_V); 409 out_be64(iommu->xlate_regs + IOC_IO_ExcpMask, 410 IOC_IO_ExcpMask_PFE | IOC_IO_ExcpMask_SFE); 411 412 virq = irq_create_mapping(NULL, 413 IIC_IRQ_IOEX_ATI | (iommu->nid << IIC_IRQ_NODE_SHIFT)); 414 BUG_ON(virq == NO_IRQ); 415 416 ret = request_irq(virq, ioc_interrupt, IRQF_DISABLED, 417 iommu->name, iommu); 418 BUG_ON(ret); 419 420 /* set the IOC segment table origin register (and turn on the iommu) */ 421 reg = IOC_IOST_Origin_E | __pa(iommu->stab) | IOC_IOST_Origin_HW; 422 out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg); 423 in_be64(iommu->xlate_regs + IOC_IOST_Origin); 424 425 /* turn on IO translation */ 426 reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE; 427 out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg); 428 } 429 430 static void cell_iommu_setup_hardware(struct cbe_iommu *iommu, 431 unsigned long base, unsigned long size) 432 { 433 cell_iommu_setup_stab(iommu, base, size, 0, 0); 434 iommu->ptab = cell_iommu_alloc_ptab(iommu, base, size, 0, 0, 435 IOMMU_PAGE_SHIFT); 436 cell_iommu_enable_hardware(iommu); 437 } 438 439 #if 0/* Unused for now */ 440 static struct iommu_window *find_window(struct cbe_iommu *iommu, 441 unsigned long offset, unsigned long size) 442 { 443 struct iommu_window *window; 444 445 /* todo: check for overlapping (but not equal) windows) */ 446 447 list_for_each_entry(window, &(iommu->windows), list) { 448 if (window->offset == offset && window->size == size) 449 return window; 450 } 451 452 return NULL; 453 } 454 #endif 455 456 static inline u32 cell_iommu_get_ioid(struct device_node *np) 457 { 458 const u32 *ioid; 459 460 ioid = of_get_property(np, "ioid", NULL); 461 if (ioid == NULL) { 462 printk(KERN_WARNING "iommu: missing ioid for %s using 0\n", 463 np->full_name); 464 return 0; 465 } 466 467 return *ioid; 468 } 469 470 static struct iommu_window * __init 471 cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np, 472 unsigned long offset, unsigned long size, 473 unsigned long pte_offset) 474 { 475 struct iommu_window *window; 476 struct page *page; 477 u32 ioid; 478 479 ioid = cell_iommu_get_ioid(np); 480 481 window = kmalloc_node(sizeof(*window), GFP_KERNEL, iommu->nid); 482 BUG_ON(window == NULL); 483 484 window->offset = offset; 485 window->size = size; 486 window->ioid = ioid; 487 window->iommu = iommu; 488 489 window->table.it_blocksize = 16; 490 window->table.it_base = (unsigned long)iommu->ptab; 491 window->table.it_index = iommu->nid; 492 window->table.it_offset = (offset >> IOMMU_PAGE_SHIFT) + pte_offset; 493 window->table.it_size = size >> IOMMU_PAGE_SHIFT; 494 495 iommu_init_table(&window->table, iommu->nid); 496 497 pr_debug("\tioid %d\n", window->ioid); 498 pr_debug("\tblocksize %ld\n", window->table.it_blocksize); 499 pr_debug("\tbase 0x%016lx\n", window->table.it_base); 500 pr_debug("\toffset 0x%lx\n", window->table.it_offset); 501 pr_debug("\tsize %ld\n", window->table.it_size); 502 503 list_add(&window->list, &iommu->windows); 504 505 if (offset != 0) 506 return window; 507 508 /* We need to map and reserve the first IOMMU page since it's used 509 * by the spider workaround. In theory, we only need to do that when 510 * running on spider but it doesn't really matter. 511 * 512 * This code also assumes that we have a window that starts at 0, 513 * which is the case on all spider based blades. 514 */ 515 page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0); 516 BUG_ON(!page); 517 iommu->pad_page = page_address(page); 518 clear_page(iommu->pad_page); 519 520 __set_bit(0, window->table.it_map); 521 tce_build_cell(&window->table, window->table.it_offset, 1, 522 (unsigned long)iommu->pad_page, DMA_TO_DEVICE); 523 window->table.it_hint = window->table.it_blocksize; 524 525 return window; 526 } 527 528 static struct cbe_iommu *cell_iommu_for_node(int nid) 529 { 530 int i; 531 532 for (i = 0; i < cbe_nr_iommus; i++) 533 if (iommus[i].nid == nid) 534 return &iommus[i]; 535 return NULL; 536 } 537 538 static unsigned long cell_dma_direct_offset; 539 540 static unsigned long dma_iommu_fixed_base; 541 struct dma_mapping_ops dma_iommu_fixed_ops; 542 543 static void cell_dma_dev_setup_iommu(struct device *dev) 544 { 545 struct iommu_window *window; 546 struct cbe_iommu *iommu; 547 struct dev_archdata *archdata = &dev->archdata; 548 549 /* Current implementation uses the first window available in that 550 * node's iommu. We -might- do something smarter later though it may 551 * never be necessary 552 */ 553 iommu = cell_iommu_for_node(archdata->numa_node); 554 if (iommu == NULL || list_empty(&iommu->windows)) { 555 printk(KERN_ERR "iommu: missing iommu for %s (node %d)\n", 556 archdata->of_node ? archdata->of_node->full_name : "?", 557 archdata->numa_node); 558 return; 559 } 560 window = list_entry(iommu->windows.next, struct iommu_window, list); 561 562 archdata->dma_data = &window->table; 563 } 564 565 static void cell_dma_dev_setup_fixed(struct device *dev); 566 567 static void cell_dma_dev_setup(struct device *dev) 568 { 569 struct dev_archdata *archdata = &dev->archdata; 570 571 /* Order is important here, these are not mutually exclusive */ 572 if (get_dma_ops(dev) == &dma_iommu_fixed_ops) 573 cell_dma_dev_setup_fixed(dev); 574 else if (get_pci_dma_ops() == &dma_iommu_ops) 575 cell_dma_dev_setup_iommu(dev); 576 else if (get_pci_dma_ops() == &dma_direct_ops) 577 archdata->dma_data = (void *)cell_dma_direct_offset; 578 else 579 BUG(); 580 } 581 582 static void cell_pci_dma_dev_setup(struct pci_dev *dev) 583 { 584 cell_dma_dev_setup(&dev->dev); 585 } 586 587 static int cell_of_bus_notify(struct notifier_block *nb, unsigned long action, 588 void *data) 589 { 590 struct device *dev = data; 591 592 /* We are only intereted in device addition */ 593 if (action != BUS_NOTIFY_ADD_DEVICE) 594 return 0; 595 596 /* We use the PCI DMA ops */ 597 dev->archdata.dma_ops = get_pci_dma_ops(); 598 599 cell_dma_dev_setup(dev); 600 601 return 0; 602 } 603 604 static struct notifier_block cell_of_bus_notifier = { 605 .notifier_call = cell_of_bus_notify 606 }; 607 608 static int __init cell_iommu_get_window(struct device_node *np, 609 unsigned long *base, 610 unsigned long *size) 611 { 612 const void *dma_window; 613 unsigned long index; 614 615 /* Use ibm,dma-window if available, else, hard code ! */ 616 dma_window = of_get_property(np, "ibm,dma-window", NULL); 617 if (dma_window == NULL) { 618 *base = 0; 619 *size = 0x80000000u; 620 return -ENODEV; 621 } 622 623 of_parse_dma_window(np, dma_window, &index, base, size); 624 return 0; 625 } 626 627 static struct cbe_iommu * __init cell_iommu_alloc(struct device_node *np) 628 { 629 struct cbe_iommu *iommu; 630 int nid, i; 631 632 /* Get node ID */ 633 nid = of_node_to_nid(np); 634 if (nid < 0) { 635 printk(KERN_ERR "iommu: failed to get node for %s\n", 636 np->full_name); 637 return NULL; 638 } 639 pr_debug("iommu: setting up iommu for node %d (%s)\n", 640 nid, np->full_name); 641 642 /* XXX todo: If we can have multiple windows on the same IOMMU, which 643 * isn't the case today, we probably want here to check wether the 644 * iommu for that node is already setup. 645 * However, there might be issue with getting the size right so let's 646 * ignore that for now. We might want to completely get rid of the 647 * multiple window support since the cell iommu supports per-page ioids 648 */ 649 650 if (cbe_nr_iommus >= NR_IOMMUS) { 651 printk(KERN_ERR "iommu: too many IOMMUs detected ! (%s)\n", 652 np->full_name); 653 return NULL; 654 } 655 656 /* Init base fields */ 657 i = cbe_nr_iommus++; 658 iommu = &iommus[i]; 659 iommu->stab = NULL; 660 iommu->nid = nid; 661 snprintf(iommu->name, sizeof(iommu->name), "iommu%d", i); 662 INIT_LIST_HEAD(&iommu->windows); 663 664 return iommu; 665 } 666 667 static void __init cell_iommu_init_one(struct device_node *np, 668 unsigned long offset) 669 { 670 struct cbe_iommu *iommu; 671 unsigned long base, size; 672 673 iommu = cell_iommu_alloc(np); 674 if (!iommu) 675 return; 676 677 /* Obtain a window for it */ 678 cell_iommu_get_window(np, &base, &size); 679 680 pr_debug("\ttranslating window 0x%lx...0x%lx\n", 681 base, base + size - 1); 682 683 /* Initialize the hardware */ 684 cell_iommu_setup_hardware(iommu, base, size); 685 686 /* Setup the iommu_table */ 687 cell_iommu_setup_window(iommu, np, base, size, 688 offset >> IOMMU_PAGE_SHIFT); 689 } 690 691 static void __init cell_disable_iommus(void) 692 { 693 int node; 694 unsigned long base, val; 695 void __iomem *xregs, *cregs; 696 697 /* Make sure IOC translation is disabled on all nodes */ 698 for_each_online_node(node) { 699 if (cell_iommu_find_ioc(node, &base)) 700 continue; 701 xregs = ioremap(base, IOC_Reg_Size); 702 if (xregs == NULL) 703 continue; 704 cregs = xregs + IOC_IOCmd_Offset; 705 706 pr_debug("iommu: cleaning up iommu on node %d\n", node); 707 708 out_be64(xregs + IOC_IOST_Origin, 0); 709 (void)in_be64(xregs + IOC_IOST_Origin); 710 val = in_be64(cregs + IOC_IOCmd_Cfg); 711 val &= ~IOC_IOCmd_Cfg_TE; 712 out_be64(cregs + IOC_IOCmd_Cfg, val); 713 (void)in_be64(cregs + IOC_IOCmd_Cfg); 714 715 iounmap(xregs); 716 } 717 } 718 719 static int __init cell_iommu_init_disabled(void) 720 { 721 struct device_node *np = NULL; 722 unsigned long base = 0, size; 723 724 /* When no iommu is present, we use direct DMA ops */ 725 set_pci_dma_ops(&dma_direct_ops); 726 727 /* First make sure all IOC translation is turned off */ 728 cell_disable_iommus(); 729 730 /* If we have no Axon, we set up the spider DMA magic offset */ 731 if (of_find_node_by_name(NULL, "axon") == NULL) 732 cell_dma_direct_offset = SPIDER_DMA_OFFSET; 733 734 /* Now we need to check to see where the memory is mapped 735 * in PCI space. We assume that all busses use the same dma 736 * window which is always the case so far on Cell, thus we 737 * pick up the first pci-internal node we can find and check 738 * the DMA window from there. 739 */ 740 for_each_node_by_name(np, "axon") { 741 if (np->parent == NULL || np->parent->parent != NULL) 742 continue; 743 if (cell_iommu_get_window(np, &base, &size) == 0) 744 break; 745 } 746 if (np == NULL) { 747 for_each_node_by_name(np, "pci-internal") { 748 if (np->parent == NULL || np->parent->parent != NULL) 749 continue; 750 if (cell_iommu_get_window(np, &base, &size) == 0) 751 break; 752 } 753 } 754 of_node_put(np); 755 756 /* If we found a DMA window, we check if it's big enough to enclose 757 * all of physical memory. If not, we force enable IOMMU 758 */ 759 if (np && size < lmb_end_of_DRAM()) { 760 printk(KERN_WARNING "iommu: force-enabled, dma window" 761 " (%ldMB) smaller than total memory (%ldMB)\n", 762 size >> 20, lmb_end_of_DRAM() >> 20); 763 return -ENODEV; 764 } 765 766 cell_dma_direct_offset += base; 767 768 if (cell_dma_direct_offset != 0) 769 ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup; 770 771 printk("iommu: disabled, direct DMA offset is 0x%lx\n", 772 cell_dma_direct_offset); 773 774 return 0; 775 } 776 777 /* 778 * Fixed IOMMU mapping support 779 * 780 * This code adds support for setting up a fixed IOMMU mapping on certain 781 * cell machines. For 64-bit devices this avoids the performance overhead of 782 * mapping and unmapping pages at runtime. 32-bit devices are unable to use 783 * the fixed mapping. 784 * 785 * The fixed mapping is established at boot, and maps all of physical memory 786 * 1:1 into device space at some offset. On machines with < 30 GB of memory 787 * we setup the fixed mapping immediately above the normal IOMMU window. 788 * 789 * For example a machine with 4GB of memory would end up with the normal 790 * IOMMU window from 0-2GB and the fixed mapping window from 2GB to 6GB. In 791 * this case a 64-bit device wishing to DMA to 1GB would be told to DMA to 792 * 3GB, plus any offset required by firmware. The firmware offset is encoded 793 * in the "dma-ranges" property. 794 * 795 * On machines with 30GB or more of memory, we are unable to place the fixed 796 * mapping above the normal IOMMU window as we would run out of address space. 797 * Instead we move the normal IOMMU window to coincide with the hash page 798 * table, this region does not need to be part of the fixed mapping as no 799 * device should ever be DMA'ing to it. We then setup the fixed mapping 800 * from 0 to 32GB. 801 */ 802 803 static u64 cell_iommu_get_fixed_address(struct device *dev) 804 { 805 u64 cpu_addr, size, best_size, dev_addr = OF_BAD_ADDR; 806 struct device_node *np; 807 const u32 *ranges = NULL; 808 int i, len, best, naddr, nsize, pna, range_size; 809 810 np = of_node_get(dev->archdata.of_node); 811 while (1) { 812 naddr = of_n_addr_cells(np); 813 nsize = of_n_size_cells(np); 814 np = of_get_next_parent(np); 815 if (!np) 816 break; 817 818 ranges = of_get_property(np, "dma-ranges", &len); 819 820 /* Ignore empty ranges, they imply no translation required */ 821 if (ranges && len > 0) 822 break; 823 } 824 825 if (!ranges) { 826 dev_dbg(dev, "iommu: no dma-ranges found\n"); 827 goto out; 828 } 829 830 len /= sizeof(u32); 831 832 pna = of_n_addr_cells(np); 833 range_size = naddr + nsize + pna; 834 835 /* dma-ranges format: 836 * child addr : naddr cells 837 * parent addr : pna cells 838 * size : nsize cells 839 */ 840 for (i = 0, best = -1, best_size = 0; i < len; i += range_size) { 841 cpu_addr = of_translate_dma_address(np, ranges + i + naddr); 842 size = of_read_number(ranges + i + naddr + pna, nsize); 843 844 if (cpu_addr == 0 && size > best_size) { 845 best = i; 846 best_size = size; 847 } 848 } 849 850 if (best >= 0) { 851 dev_addr = of_read_number(ranges + best, naddr); 852 } else 853 dev_dbg(dev, "iommu: no suitable range found!\n"); 854 855 out: 856 of_node_put(np); 857 858 return dev_addr; 859 } 860 861 static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask) 862 { 863 if (!dev->dma_mask || !dma_supported(dev, dma_mask)) 864 return -EIO; 865 866 if (dma_mask == DMA_BIT_MASK(64) && 867 cell_iommu_get_fixed_address(dev) != OF_BAD_ADDR) 868 { 869 dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n"); 870 set_dma_ops(dev, &dma_iommu_fixed_ops); 871 } else { 872 dev_dbg(dev, "iommu: not 64-bit, using default ops\n"); 873 set_dma_ops(dev, get_pci_dma_ops()); 874 } 875 876 cell_dma_dev_setup(dev); 877 878 *dev->dma_mask = dma_mask; 879 880 return 0; 881 } 882 883 static void cell_dma_dev_setup_fixed(struct device *dev) 884 { 885 struct dev_archdata *archdata = &dev->archdata; 886 u64 addr; 887 888 addr = cell_iommu_get_fixed_address(dev) + dma_iommu_fixed_base; 889 archdata->dma_data = (void *)addr; 890 891 dev_dbg(dev, "iommu: fixed addr = %lx\n", addr); 892 } 893 894 static void insert_16M_pte(unsigned long addr, unsigned long *ptab, 895 unsigned long base_pte) 896 { 897 unsigned long segment, offset; 898 899 segment = addr >> IO_SEGMENT_SHIFT; 900 offset = (addr >> 24) - (segment << IO_PAGENO_BITS(24)); 901 ptab = ptab + (segment * (1 << 12) / sizeof(unsigned long)); 902 903 pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n", 904 addr, ptab, segment, offset); 905 906 ptab[offset] = base_pte | (__pa(addr) & IOPTE_RPN_Mask); 907 } 908 909 static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu, 910 struct device_node *np, unsigned long dbase, unsigned long dsize, 911 unsigned long fbase, unsigned long fsize) 912 { 913 unsigned long base_pte, uaddr, ioaddr, *ptab; 914 915 ptab = cell_iommu_alloc_ptab(iommu, fbase, fsize, dbase, dsize, 24); 916 917 dma_iommu_fixed_base = fbase; 918 919 pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase); 920 921 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW 922 | (cell_iommu_get_ioid(np) & IOPTE_IOID_Mask); 923 924 for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) { 925 /* Don't touch the dynamic region */ 926 ioaddr = uaddr + fbase; 927 if (ioaddr >= dbase && ioaddr < (dbase + dsize)) { 928 pr_debug("iommu: fixed/dynamic overlap, skipping\n"); 929 continue; 930 } 931 932 insert_16M_pte(uaddr, ptab, base_pte); 933 } 934 935 mb(); 936 } 937 938 static int __init cell_iommu_fixed_mapping_init(void) 939 { 940 unsigned long dbase, dsize, fbase, fsize, hbase, hend; 941 struct cbe_iommu *iommu; 942 struct device_node *np; 943 944 /* The fixed mapping is only supported on axon machines */ 945 np = of_find_node_by_name(NULL, "axon"); 946 if (!np) { 947 pr_debug("iommu: fixed mapping disabled, no axons found\n"); 948 return -1; 949 } 950 951 /* We must have dma-ranges properties for fixed mapping to work */ 952 for (np = NULL; (np = of_find_all_nodes(np));) { 953 if (of_find_property(np, "dma-ranges", NULL)) 954 break; 955 } 956 of_node_put(np); 957 958 if (!np) { 959 pr_debug("iommu: no dma-ranges found, no fixed mapping\n"); 960 return -1; 961 } 962 963 /* The default setup is to have the fixed mapping sit after the 964 * dynamic region, so find the top of the largest IOMMU window 965 * on any axon, then add the size of RAM and that's our max value. 966 * If that is > 32GB we have to do other shennanigans. 967 */ 968 fbase = 0; 969 for_each_node_by_name(np, "axon") { 970 cell_iommu_get_window(np, &dbase, &dsize); 971 fbase = max(fbase, dbase + dsize); 972 } 973 974 fbase = _ALIGN_UP(fbase, 1 << IO_SEGMENT_SHIFT); 975 fsize = lmb_phys_mem_size(); 976 977 if ((fbase + fsize) <= 0x800000000) 978 hbase = 0; /* use the device tree window */ 979 else { 980 /* If we're over 32 GB we need to cheat. We can't map all of 981 * RAM with the fixed mapping, and also fit the dynamic 982 * region. So try to place the dynamic region where the hash 983 * table sits, drivers never need to DMA to it, we don't 984 * need a fixed mapping for that area. 985 */ 986 if (!htab_address) { 987 pr_debug("iommu: htab is NULL, on LPAR? Huh?\n"); 988 return -1; 989 } 990 hbase = __pa(htab_address); 991 hend = hbase + htab_size_bytes; 992 993 /* The window must start and end on a segment boundary */ 994 if ((hbase != _ALIGN_UP(hbase, 1 << IO_SEGMENT_SHIFT)) || 995 (hend != _ALIGN_UP(hend, 1 << IO_SEGMENT_SHIFT))) { 996 pr_debug("iommu: hash window not segment aligned\n"); 997 return -1; 998 } 999 1000 /* Check the hash window fits inside the real DMA window */ 1001 for_each_node_by_name(np, "axon") { 1002 cell_iommu_get_window(np, &dbase, &dsize); 1003 1004 if (hbase < dbase || (hend > (dbase + dsize))) { 1005 pr_debug("iommu: hash window doesn't fit in" 1006 "real DMA window\n"); 1007 return -1; 1008 } 1009 } 1010 1011 fbase = 0; 1012 } 1013 1014 /* Setup the dynamic regions */ 1015 for_each_node_by_name(np, "axon") { 1016 iommu = cell_iommu_alloc(np); 1017 BUG_ON(!iommu); 1018 1019 if (hbase == 0) 1020 cell_iommu_get_window(np, &dbase, &dsize); 1021 else { 1022 dbase = hbase; 1023 dsize = htab_size_bytes; 1024 } 1025 1026 printk(KERN_DEBUG "iommu: node %d, dynamic window 0x%lx-0x%lx " 1027 "fixed window 0x%lx-0x%lx\n", iommu->nid, dbase, 1028 dbase + dsize, fbase, fbase + fsize); 1029 1030 cell_iommu_setup_stab(iommu, dbase, dsize, fbase, fsize); 1031 iommu->ptab = cell_iommu_alloc_ptab(iommu, dbase, dsize, 0, 0, 1032 IOMMU_PAGE_SHIFT); 1033 cell_iommu_setup_fixed_ptab(iommu, np, dbase, dsize, 1034 fbase, fsize); 1035 cell_iommu_enable_hardware(iommu); 1036 cell_iommu_setup_window(iommu, np, dbase, dsize, 0); 1037 } 1038 1039 dma_iommu_fixed_ops = dma_direct_ops; 1040 dma_iommu_fixed_ops.set_dma_mask = dma_set_mask_and_switch; 1041 1042 dma_iommu_ops.set_dma_mask = dma_set_mask_and_switch; 1043 set_pci_dma_ops(&dma_iommu_ops); 1044 1045 return 0; 1046 } 1047 1048 static int iommu_fixed_disabled; 1049 1050 static int __init setup_iommu_fixed(char *str) 1051 { 1052 if (strcmp(str, "off") == 0) 1053 iommu_fixed_disabled = 1; 1054 1055 return 1; 1056 } 1057 __setup("iommu_fixed=", setup_iommu_fixed); 1058 1059 static int __init cell_iommu_init(void) 1060 { 1061 struct device_node *np; 1062 1063 /* If IOMMU is disabled or we have little enough RAM to not need 1064 * to enable it, we setup a direct mapping. 1065 * 1066 * Note: should we make sure we have the IOMMU actually disabled ? 1067 */ 1068 if (iommu_is_off || 1069 (!iommu_force_on && lmb_end_of_DRAM() <= 0x80000000ull)) 1070 if (cell_iommu_init_disabled() == 0) 1071 goto bail; 1072 1073 /* Setup various ppc_md. callbacks */ 1074 ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup; 1075 ppc_md.tce_build = tce_build_cell; 1076 ppc_md.tce_free = tce_free_cell; 1077 1078 if (!iommu_fixed_disabled && cell_iommu_fixed_mapping_init() == 0) 1079 goto bail; 1080 1081 /* Create an iommu for each /axon node. */ 1082 for_each_node_by_name(np, "axon") { 1083 if (np->parent == NULL || np->parent->parent != NULL) 1084 continue; 1085 cell_iommu_init_one(np, 0); 1086 } 1087 1088 /* Create an iommu for each toplevel /pci-internal node for 1089 * old hardware/firmware 1090 */ 1091 for_each_node_by_name(np, "pci-internal") { 1092 if (np->parent == NULL || np->parent->parent != NULL) 1093 continue; 1094 cell_iommu_init_one(np, SPIDER_DMA_OFFSET); 1095 } 1096 1097 /* Setup default PCI iommu ops */ 1098 set_pci_dma_ops(&dma_iommu_ops); 1099 1100 bail: 1101 /* Register callbacks on OF platform device addition/removal 1102 * to handle linking them to the right DMA operations 1103 */ 1104 bus_register_notifier(&of_platform_bus_type, &cell_of_bus_notifier); 1105 1106 return 0; 1107 } 1108 machine_arch_initcall(cell, cell_iommu_init); 1109 machine_arch_initcall(celleb_native, cell_iommu_init); 1110 1111