1 /*
2  * IOMMU implementation for Cell Broadband Processor Architecture
3  *
4  * (C) Copyright IBM Corporation 2006-2008
5  *
6  * Author: Jeremy Kerr <jk@ozlabs.org>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2, or (at your option)
11  * any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22 
23 #undef DEBUG
24 
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/notifier.h>
29 #include <linux/of.h>
30 #include <linux/of_platform.h>
31 #include <linux/lmb.h>
32 
33 #include <asm/prom.h>
34 #include <asm/iommu.h>
35 #include <asm/machdep.h>
36 #include <asm/pci-bridge.h>
37 #include <asm/udbg.h>
38 #include <asm/firmware.h>
39 #include <asm/cell-regs.h>
40 
41 #include "interrupt.h"
42 
43 /* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages
44  * instead of leaving them mapped to some dummy page. This can be
45  * enabled once the appropriate workarounds for spider bugs have
46  * been enabled
47  */
48 #define CELL_IOMMU_REAL_UNMAP
49 
50 /* Define CELL_IOMMU_STRICT_PROTECTION to enforce protection of
51  * IO PTEs based on the transfer direction. That can be enabled
52  * once spider-net has been fixed to pass the correct direction
53  * to the DMA mapping functions
54  */
55 #define CELL_IOMMU_STRICT_PROTECTION
56 
57 
58 #define NR_IOMMUS			2
59 
60 /* IOC mmap registers */
61 #define IOC_Reg_Size			0x2000
62 
63 #define IOC_IOPT_CacheInvd		0x908
64 #define IOC_IOPT_CacheInvd_NE_Mask	0xffe0000000000000ul
65 #define IOC_IOPT_CacheInvd_IOPTE_Mask	0x000003fffffffff8ul
66 #define IOC_IOPT_CacheInvd_Busy		0x0000000000000001ul
67 
68 #define IOC_IOST_Origin			0x918
69 #define IOC_IOST_Origin_E		0x8000000000000000ul
70 #define IOC_IOST_Origin_HW		0x0000000000000800ul
71 #define IOC_IOST_Origin_HL		0x0000000000000400ul
72 
73 #define IOC_IO_ExcpStat			0x920
74 #define IOC_IO_ExcpStat_V		0x8000000000000000ul
75 #define IOC_IO_ExcpStat_SPF_Mask	0x6000000000000000ul
76 #define IOC_IO_ExcpStat_SPF_S		0x6000000000000000ul
77 #define IOC_IO_ExcpStat_SPF_P		0x2000000000000000ul
78 #define IOC_IO_ExcpStat_ADDR_Mask	0x00000007fffff000ul
79 #define IOC_IO_ExcpStat_RW_Mask		0x0000000000000800ul
80 #define IOC_IO_ExcpStat_IOID_Mask	0x00000000000007fful
81 
82 #define IOC_IO_ExcpMask			0x928
83 #define IOC_IO_ExcpMask_SFE		0x4000000000000000ul
84 #define IOC_IO_ExcpMask_PFE		0x2000000000000000ul
85 
86 #define IOC_IOCmd_Offset		0x1000
87 
88 #define IOC_IOCmd_Cfg			0xc00
89 #define IOC_IOCmd_Cfg_TE		0x0000800000000000ul
90 
91 
92 /* Segment table entries */
93 #define IOSTE_V			0x8000000000000000ul /* valid */
94 #define IOSTE_H			0x4000000000000000ul /* cache hint */
95 #define IOSTE_PT_Base_RPN_Mask  0x3ffffffffffff000ul /* base RPN of IOPT */
96 #define IOSTE_NPPT_Mask		0x0000000000000fe0ul /* no. pages in IOPT */
97 #define IOSTE_PS_Mask		0x0000000000000007ul /* page size */
98 #define IOSTE_PS_4K		0x0000000000000001ul /*   - 4kB  */
99 #define IOSTE_PS_64K		0x0000000000000003ul /*   - 64kB */
100 #define IOSTE_PS_1M		0x0000000000000005ul /*   - 1MB  */
101 #define IOSTE_PS_16M		0x0000000000000007ul /*   - 16MB */
102 
103 
104 /* IOMMU sizing */
105 #define IO_SEGMENT_SHIFT	28
106 #define IO_PAGENO_BITS(shift)	(IO_SEGMENT_SHIFT - (shift))
107 
108 /* The high bit needs to be set on every DMA address */
109 #define SPIDER_DMA_OFFSET	0x80000000ul
110 
111 struct iommu_window {
112 	struct list_head list;
113 	struct cbe_iommu *iommu;
114 	unsigned long offset;
115 	unsigned long size;
116 	unsigned int ioid;
117 	struct iommu_table table;
118 };
119 
120 #define NAMESIZE 8
121 struct cbe_iommu {
122 	int nid;
123 	char name[NAMESIZE];
124 	void __iomem *xlate_regs;
125 	void __iomem *cmd_regs;
126 	unsigned long *stab;
127 	unsigned long *ptab;
128 	void *pad_page;
129 	struct list_head windows;
130 };
131 
132 /* Static array of iommus, one per node
133  *   each contains a list of windows, keyed from dma_window property
134  *   - on bus setup, look for a matching window, or create one
135  *   - on dev setup, assign iommu_table ptr
136  */
137 static struct cbe_iommu iommus[NR_IOMMUS];
138 static int cbe_nr_iommus;
139 
140 static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte,
141 		long n_ptes)
142 {
143 	u64 __iomem *reg;
144 	u64 val;
145 	long n;
146 
147 	reg = iommu->xlate_regs + IOC_IOPT_CacheInvd;
148 
149 	while (n_ptes > 0) {
150 		/* we can invalidate up to 1 << 11 PTEs at once */
151 		n = min(n_ptes, 1l << 11);
152 		val = (((n /*- 1*/) << 53) & IOC_IOPT_CacheInvd_NE_Mask)
153 			| (__pa(pte) & IOC_IOPT_CacheInvd_IOPTE_Mask)
154 		        | IOC_IOPT_CacheInvd_Busy;
155 
156 		out_be64(reg, val);
157 		while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy)
158 			;
159 
160 		n_ptes -= n;
161 		pte += n;
162 	}
163 }
164 
165 static int tce_build_cell(struct iommu_table *tbl, long index, long npages,
166 		unsigned long uaddr, enum dma_data_direction direction,
167 		struct dma_attrs *attrs)
168 {
169 	int i;
170 	unsigned long *io_pte, base_pte;
171 	struct iommu_window *window =
172 		container_of(tbl, struct iommu_window, table);
173 
174 	/* implementing proper protection causes problems with the spidernet
175 	 * driver - check mapping directions later, but allow read & write by
176 	 * default for now.*/
177 #ifdef CELL_IOMMU_STRICT_PROTECTION
178 	/* to avoid referencing a global, we use a trick here to setup the
179 	 * protection bit. "prot" is setup to be 3 fields of 4 bits apprended
180 	 * together for each of the 3 supported direction values. It is then
181 	 * shifted left so that the fields matching the desired direction
182 	 * lands on the appropriate bits, and other bits are masked out.
183 	 */
184 	const unsigned long prot = 0xc48;
185 	base_pte =
186 		((prot << (52 + 4 * direction)) &
187 		 (CBE_IOPTE_PP_W | CBE_IOPTE_PP_R)) |
188 		CBE_IOPTE_M | CBE_IOPTE_SO_RW |
189 		(window->ioid & CBE_IOPTE_IOID_Mask);
190 #else
191 	base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M |
192 		CBE_IOPTE_SO_RW | (window->ioid & CBE_IOPTE_IOID_Mask);
193 #endif
194 	if (unlikely(dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)))
195 		base_pte &= ~CBE_IOPTE_SO_RW;
196 
197 	io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
198 
199 	for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE)
200 		io_pte[i] = base_pte | (__pa(uaddr) & CBE_IOPTE_RPN_Mask);
201 
202 	mb();
203 
204 	invalidate_tce_cache(window->iommu, io_pte, npages);
205 
206 	pr_debug("tce_build_cell(index=%lx,n=%lx,dir=%d,base_pte=%lx)\n",
207 		 index, npages, direction, base_pte);
208 	return 0;
209 }
210 
211 static void tce_free_cell(struct iommu_table *tbl, long index, long npages)
212 {
213 
214 	int i;
215 	unsigned long *io_pte, pte;
216 	struct iommu_window *window =
217 		container_of(tbl, struct iommu_window, table);
218 
219 	pr_debug("tce_free_cell(index=%lx,n=%lx)\n", index, npages);
220 
221 #ifdef CELL_IOMMU_REAL_UNMAP
222 	pte = 0;
223 #else
224 	/* spider bridge does PCI reads after freeing - insert a mapping
225 	 * to a scratch page instead of an invalid entry */
226 	pte = CBE_IOPTE_PP_R | CBE_IOPTE_M | CBE_IOPTE_SO_RW |
227 		__pa(window->iommu->pad_page) |
228 		(window->ioid & CBE_IOPTE_IOID_Mask);
229 #endif
230 
231 	io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset);
232 
233 	for (i = 0; i < npages; i++)
234 		io_pte[i] = pte;
235 
236 	mb();
237 
238 	invalidate_tce_cache(window->iommu, io_pte, npages);
239 }
240 
241 static irqreturn_t ioc_interrupt(int irq, void *data)
242 {
243 	unsigned long stat, spf;
244 	struct cbe_iommu *iommu = data;
245 
246 	stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
247 	spf = stat & IOC_IO_ExcpStat_SPF_Mask;
248 
249 	/* Might want to rate limit it */
250 	printk(KERN_ERR "iommu: DMA exception 0x%016lx\n", stat);
251 	printk(KERN_ERR "  V=%d, SPF=[%c%c], RW=%s, IOID=0x%04x\n",
252 	       !!(stat & IOC_IO_ExcpStat_V),
253 	       (spf == IOC_IO_ExcpStat_SPF_S) ? 'S' : ' ',
254 	       (spf == IOC_IO_ExcpStat_SPF_P) ? 'P' : ' ',
255 	       (stat & IOC_IO_ExcpStat_RW_Mask) ? "Read" : "Write",
256 	       (unsigned int)(stat & IOC_IO_ExcpStat_IOID_Mask));
257 	printk(KERN_ERR "  page=0x%016lx\n",
258 	       stat & IOC_IO_ExcpStat_ADDR_Mask);
259 
260 	/* clear interrupt */
261 	stat &= ~IOC_IO_ExcpStat_V;
262 	out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat);
263 
264 	return IRQ_HANDLED;
265 }
266 
267 static int cell_iommu_find_ioc(int nid, unsigned long *base)
268 {
269 	struct device_node *np;
270 	struct resource r;
271 
272 	*base = 0;
273 
274 	/* First look for new style /be nodes */
275 	for_each_node_by_name(np, "ioc") {
276 		if (of_node_to_nid(np) != nid)
277 			continue;
278 		if (of_address_to_resource(np, 0, &r)) {
279 			printk(KERN_ERR "iommu: can't get address for %s\n",
280 			       np->full_name);
281 			continue;
282 		}
283 		*base = r.start;
284 		of_node_put(np);
285 		return 0;
286 	}
287 
288 	/* Ok, let's try the old way */
289 	for_each_node_by_type(np, "cpu") {
290 		const unsigned int *nidp;
291 		const unsigned long *tmp;
292 
293 		nidp = of_get_property(np, "node-id", NULL);
294 		if (nidp && *nidp == nid) {
295 			tmp = of_get_property(np, "ioc-translation", NULL);
296 			if (tmp) {
297 				*base = *tmp;
298 				of_node_put(np);
299 				return 0;
300 			}
301 		}
302 	}
303 
304 	return -ENODEV;
305 }
306 
307 static void cell_iommu_setup_stab(struct cbe_iommu *iommu,
308 				unsigned long dbase, unsigned long dsize,
309 				unsigned long fbase, unsigned long fsize)
310 {
311 	struct page *page;
312 	unsigned long segments, stab_size;
313 
314 	segments = max(dbase + dsize, fbase + fsize) >> IO_SEGMENT_SHIFT;
315 
316 	pr_debug("%s: iommu[%d]: segments: %lu\n",
317 			__func__, iommu->nid, segments);
318 
319 	/* set up the segment table */
320 	stab_size = segments * sizeof(unsigned long);
321 	page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(stab_size));
322 	BUG_ON(!page);
323 	iommu->stab = page_address(page);
324 	memset(iommu->stab, 0, stab_size);
325 }
326 
327 static unsigned long *cell_iommu_alloc_ptab(struct cbe_iommu *iommu,
328 		unsigned long base, unsigned long size, unsigned long gap_base,
329 		unsigned long gap_size, unsigned long page_shift)
330 {
331 	struct page *page;
332 	int i;
333 	unsigned long reg, segments, pages_per_segment, ptab_size,
334 		      n_pte_pages, start_seg, *ptab;
335 
336 	start_seg = base >> IO_SEGMENT_SHIFT;
337 	segments  = size >> IO_SEGMENT_SHIFT;
338 	pages_per_segment = 1ull << IO_PAGENO_BITS(page_shift);
339 	/* PTEs for each segment must start on a 4K bounday */
340 	pages_per_segment = max(pages_per_segment,
341 				(1 << 12) / sizeof(unsigned long));
342 
343 	ptab_size = segments * pages_per_segment * sizeof(unsigned long);
344 	pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __func__,
345 			iommu->nid, ptab_size, get_order(ptab_size));
346 	page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size));
347 	BUG_ON(!page);
348 
349 	ptab = page_address(page);
350 	memset(ptab, 0, ptab_size);
351 
352 	/* number of 4K pages needed for a page table */
353 	n_pte_pages = (pages_per_segment * sizeof(unsigned long)) >> 12;
354 
355 	pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n",
356 			__func__, iommu->nid, iommu->stab, ptab,
357 			n_pte_pages);
358 
359 	/* initialise the STEs */
360 	reg = IOSTE_V | ((n_pte_pages - 1) << 5);
361 
362 	switch (page_shift) {
363 	case 12: reg |= IOSTE_PS_4K;  break;
364 	case 16: reg |= IOSTE_PS_64K; break;
365 	case 20: reg |= IOSTE_PS_1M;  break;
366 	case 24: reg |= IOSTE_PS_16M; break;
367 	default: BUG();
368 	}
369 
370 	gap_base = gap_base >> IO_SEGMENT_SHIFT;
371 	gap_size = gap_size >> IO_SEGMENT_SHIFT;
372 
373 	pr_debug("Setting up IOMMU stab:\n");
374 	for (i = start_seg; i < (start_seg + segments); i++) {
375 		if (i >= gap_base && i < (gap_base + gap_size)) {
376 			pr_debug("\toverlap at %d, skipping\n", i);
377 			continue;
378 		}
379 		iommu->stab[i] = reg | (__pa(ptab) + (n_pte_pages << 12) *
380 					(i - start_seg));
381 		pr_debug("\t[%d] 0x%016lx\n", i, iommu->stab[i]);
382 	}
383 
384 	return ptab;
385 }
386 
387 static void cell_iommu_enable_hardware(struct cbe_iommu *iommu)
388 {
389 	int ret;
390 	unsigned long reg, xlate_base;
391 	unsigned int virq;
392 
393 	if (cell_iommu_find_ioc(iommu->nid, &xlate_base))
394 		panic("%s: missing IOC register mappings for node %d\n",
395 		      __func__, iommu->nid);
396 
397 	iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size);
398 	iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset;
399 
400 	/* ensure that the STEs have updated */
401 	mb();
402 
403 	/* setup interrupts for the iommu. */
404 	reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
405 	out_be64(iommu->xlate_regs + IOC_IO_ExcpStat,
406 			reg & ~IOC_IO_ExcpStat_V);
407 	out_be64(iommu->xlate_regs + IOC_IO_ExcpMask,
408 			IOC_IO_ExcpMask_PFE | IOC_IO_ExcpMask_SFE);
409 
410 	virq = irq_create_mapping(NULL,
411 			IIC_IRQ_IOEX_ATI | (iommu->nid << IIC_IRQ_NODE_SHIFT));
412 	BUG_ON(virq == NO_IRQ);
413 
414 	ret = request_irq(virq, ioc_interrupt, IRQF_DISABLED,
415 			iommu->name, iommu);
416 	BUG_ON(ret);
417 
418 	/* set the IOC segment table origin register (and turn on the iommu) */
419 	reg = IOC_IOST_Origin_E | __pa(iommu->stab) | IOC_IOST_Origin_HW;
420 	out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg);
421 	in_be64(iommu->xlate_regs + IOC_IOST_Origin);
422 
423 	/* turn on IO translation */
424 	reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE;
425 	out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg);
426 }
427 
428 static void cell_iommu_setup_hardware(struct cbe_iommu *iommu,
429 	unsigned long base, unsigned long size)
430 {
431 	cell_iommu_setup_stab(iommu, base, size, 0, 0);
432 	iommu->ptab = cell_iommu_alloc_ptab(iommu, base, size, 0, 0,
433 					    IOMMU_PAGE_SHIFT);
434 	cell_iommu_enable_hardware(iommu);
435 }
436 
437 #if 0/* Unused for now */
438 static struct iommu_window *find_window(struct cbe_iommu *iommu,
439 		unsigned long offset, unsigned long size)
440 {
441 	struct iommu_window *window;
442 
443 	/* todo: check for overlapping (but not equal) windows) */
444 
445 	list_for_each_entry(window, &(iommu->windows), list) {
446 		if (window->offset == offset && window->size == size)
447 			return window;
448 	}
449 
450 	return NULL;
451 }
452 #endif
453 
454 static inline u32 cell_iommu_get_ioid(struct device_node *np)
455 {
456 	const u32 *ioid;
457 
458 	ioid = of_get_property(np, "ioid", NULL);
459 	if (ioid == NULL) {
460 		printk(KERN_WARNING "iommu: missing ioid for %s using 0\n",
461 		       np->full_name);
462 		return 0;
463 	}
464 
465 	return *ioid;
466 }
467 
468 static struct iommu_window * __init
469 cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
470 			unsigned long offset, unsigned long size,
471 			unsigned long pte_offset)
472 {
473 	struct iommu_window *window;
474 	struct page *page;
475 	u32 ioid;
476 
477 	ioid = cell_iommu_get_ioid(np);
478 
479 	window = kmalloc_node(sizeof(*window), GFP_KERNEL, iommu->nid);
480 	BUG_ON(window == NULL);
481 
482 	window->offset = offset;
483 	window->size = size;
484 	window->ioid = ioid;
485 	window->iommu = iommu;
486 
487 	window->table.it_blocksize = 16;
488 	window->table.it_base = (unsigned long)iommu->ptab;
489 	window->table.it_index = iommu->nid;
490 	window->table.it_offset = (offset >> IOMMU_PAGE_SHIFT) + pte_offset;
491 	window->table.it_size = size >> IOMMU_PAGE_SHIFT;
492 
493 	iommu_init_table(&window->table, iommu->nid);
494 
495 	pr_debug("\tioid      %d\n", window->ioid);
496 	pr_debug("\tblocksize %ld\n", window->table.it_blocksize);
497 	pr_debug("\tbase      0x%016lx\n", window->table.it_base);
498 	pr_debug("\toffset    0x%lx\n", window->table.it_offset);
499 	pr_debug("\tsize      %ld\n", window->table.it_size);
500 
501 	list_add(&window->list, &iommu->windows);
502 
503 	if (offset != 0)
504 		return window;
505 
506 	/* We need to map and reserve the first IOMMU page since it's used
507 	 * by the spider workaround. In theory, we only need to do that when
508 	 * running on spider but it doesn't really matter.
509 	 *
510 	 * This code also assumes that we have a window that starts at 0,
511 	 * which is the case on all spider based blades.
512 	 */
513 	page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0);
514 	BUG_ON(!page);
515 	iommu->pad_page = page_address(page);
516 	clear_page(iommu->pad_page);
517 
518 	__set_bit(0, window->table.it_map);
519 	tce_build_cell(&window->table, window->table.it_offset, 1,
520 		       (unsigned long)iommu->pad_page, DMA_TO_DEVICE, NULL);
521 	window->table.it_hint = window->table.it_blocksize;
522 
523 	return window;
524 }
525 
526 static struct cbe_iommu *cell_iommu_for_node(int nid)
527 {
528 	int i;
529 
530 	for (i = 0; i < cbe_nr_iommus; i++)
531 		if (iommus[i].nid == nid)
532 			return &iommus[i];
533 	return NULL;
534 }
535 
536 static unsigned long cell_dma_direct_offset;
537 
538 static unsigned long dma_iommu_fixed_base;
539 
540 /* iommu_fixed_is_weak is set if booted with iommu_fixed=weak */
541 static int iommu_fixed_is_weak;
542 
543 static struct iommu_table *cell_get_iommu_table(struct device *dev)
544 {
545 	struct iommu_window *window;
546 	struct cbe_iommu *iommu;
547 	struct dev_archdata *archdata = &dev->archdata;
548 
549 	/* Current implementation uses the first window available in that
550 	 * node's iommu. We -might- do something smarter later though it may
551 	 * never be necessary
552 	 */
553 	iommu = cell_iommu_for_node(dev_to_node(dev));
554 	if (iommu == NULL || list_empty(&iommu->windows)) {
555 		printk(KERN_ERR "iommu: missing iommu for %s (node %d)\n",
556 		       archdata->of_node ? archdata->of_node->full_name : "?",
557 		       dev_to_node(dev));
558 		return NULL;
559 	}
560 	window = list_entry(iommu->windows.next, struct iommu_window, list);
561 
562 	return &window->table;
563 }
564 
565 /* A coherent allocation implies strong ordering */
566 
567 static void *dma_fixed_alloc_coherent(struct device *dev, size_t size,
568 				      dma_addr_t *dma_handle, gfp_t flag)
569 {
570 	if (iommu_fixed_is_weak)
571 		return iommu_alloc_coherent(dev, cell_get_iommu_table(dev),
572 					    size, dma_handle,
573 					    device_to_mask(dev), flag,
574 					    dev_to_node(dev));
575 	else
576 		return dma_direct_ops.alloc_coherent(dev, size, dma_handle,
577 						     flag);
578 }
579 
580 static void dma_fixed_free_coherent(struct device *dev, size_t size,
581 				    void *vaddr, dma_addr_t dma_handle)
582 {
583 	if (iommu_fixed_is_weak)
584 		iommu_free_coherent(cell_get_iommu_table(dev), size, vaddr,
585 				    dma_handle);
586 	else
587 		dma_direct_ops.free_coherent(dev, size, vaddr, dma_handle);
588 }
589 
590 static dma_addr_t dma_fixed_map_page(struct device *dev, struct page *page,
591 				     unsigned long offset, size_t size,
592 				     enum dma_data_direction direction,
593 				     struct dma_attrs *attrs)
594 {
595 	if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
596 		return dma_direct_ops.map_page(dev, page, offset, size,
597 					       direction, attrs);
598 	else
599 		return iommu_map_page(dev, cell_get_iommu_table(dev), page,
600 				      offset, size, device_to_mask(dev),
601 				      direction, attrs);
602 }
603 
604 static void dma_fixed_unmap_page(struct device *dev, dma_addr_t dma_addr,
605 				 size_t size, enum dma_data_direction direction,
606 				 struct dma_attrs *attrs)
607 {
608 	if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
609 		dma_direct_ops.unmap_page(dev, dma_addr, size, direction,
610 					  attrs);
611 	else
612 		iommu_unmap_page(cell_get_iommu_table(dev), dma_addr, size,
613 				 direction, attrs);
614 }
615 
616 static int dma_fixed_map_sg(struct device *dev, struct scatterlist *sg,
617 			   int nents, enum dma_data_direction direction,
618 			   struct dma_attrs *attrs)
619 {
620 	if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
621 		return dma_direct_ops.map_sg(dev, sg, nents, direction, attrs);
622 	else
623 		return iommu_map_sg(dev, cell_get_iommu_table(dev), sg, nents,
624 				    device_to_mask(dev), direction, attrs);
625 }
626 
627 static void dma_fixed_unmap_sg(struct device *dev, struct scatterlist *sg,
628 			       int nents, enum dma_data_direction direction,
629 			       struct dma_attrs *attrs)
630 {
631 	if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))
632 		dma_direct_ops.unmap_sg(dev, sg, nents, direction, attrs);
633 	else
634 		iommu_unmap_sg(cell_get_iommu_table(dev), sg, nents, direction,
635 			       attrs);
636 }
637 
638 static int dma_fixed_dma_supported(struct device *dev, u64 mask)
639 {
640 	return mask == DMA_BIT_MASK(64);
641 }
642 
643 static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask);
644 
645 struct dma_map_ops dma_iommu_fixed_ops = {
646 	.alloc_coherent = dma_fixed_alloc_coherent,
647 	.free_coherent  = dma_fixed_free_coherent,
648 	.map_sg         = dma_fixed_map_sg,
649 	.unmap_sg       = dma_fixed_unmap_sg,
650 	.dma_supported  = dma_fixed_dma_supported,
651 	.set_dma_mask   = dma_set_mask_and_switch,
652 	.map_page       = dma_fixed_map_page,
653 	.unmap_page     = dma_fixed_unmap_page,
654 };
655 
656 static void cell_dma_dev_setup_fixed(struct device *dev);
657 
658 static void cell_dma_dev_setup(struct device *dev)
659 {
660 	/* Order is important here, these are not mutually exclusive */
661 	if (get_dma_ops(dev) == &dma_iommu_fixed_ops)
662 		cell_dma_dev_setup_fixed(dev);
663 	else if (get_pci_dma_ops() == &dma_iommu_ops)
664 		set_iommu_table_base(dev, cell_get_iommu_table(dev));
665 	else if (get_pci_dma_ops() == &dma_direct_ops)
666 		set_dma_offset(dev, cell_dma_direct_offset);
667 	else
668 		BUG();
669 }
670 
671 static void cell_pci_dma_dev_setup(struct pci_dev *dev)
672 {
673 	cell_dma_dev_setup(&dev->dev);
674 }
675 
676 static int cell_of_bus_notify(struct notifier_block *nb, unsigned long action,
677 			      void *data)
678 {
679 	struct device *dev = data;
680 
681 	/* We are only intereted in device addition */
682 	if (action != BUS_NOTIFY_ADD_DEVICE)
683 		return 0;
684 
685 	/* We use the PCI DMA ops */
686 	dev->archdata.dma_ops = get_pci_dma_ops();
687 
688 	cell_dma_dev_setup(dev);
689 
690 	return 0;
691 }
692 
693 static struct notifier_block cell_of_bus_notifier = {
694 	.notifier_call = cell_of_bus_notify
695 };
696 
697 static int __init cell_iommu_get_window(struct device_node *np,
698 					 unsigned long *base,
699 					 unsigned long *size)
700 {
701 	const void *dma_window;
702 	unsigned long index;
703 
704 	/* Use ibm,dma-window if available, else, hard code ! */
705 	dma_window = of_get_property(np, "ibm,dma-window", NULL);
706 	if (dma_window == NULL) {
707 		*base = 0;
708 		*size = 0x80000000u;
709 		return -ENODEV;
710 	}
711 
712 	of_parse_dma_window(np, dma_window, &index, base, size);
713 	return 0;
714 }
715 
716 static struct cbe_iommu * __init cell_iommu_alloc(struct device_node *np)
717 {
718 	struct cbe_iommu *iommu;
719 	int nid, i;
720 
721 	/* Get node ID */
722 	nid = of_node_to_nid(np);
723 	if (nid < 0) {
724 		printk(KERN_ERR "iommu: failed to get node for %s\n",
725 		       np->full_name);
726 		return NULL;
727 	}
728 	pr_debug("iommu: setting up iommu for node %d (%s)\n",
729 		 nid, np->full_name);
730 
731 	/* XXX todo: If we can have multiple windows on the same IOMMU, which
732 	 * isn't the case today, we probably want here to check wether the
733 	 * iommu for that node is already setup.
734 	 * However, there might be issue with getting the size right so let's
735 	 * ignore that for now. We might want to completely get rid of the
736 	 * multiple window support since the cell iommu supports per-page ioids
737 	 */
738 
739 	if (cbe_nr_iommus >= NR_IOMMUS) {
740 		printk(KERN_ERR "iommu: too many IOMMUs detected ! (%s)\n",
741 		       np->full_name);
742 		return NULL;
743 	}
744 
745 	/* Init base fields */
746 	i = cbe_nr_iommus++;
747 	iommu = &iommus[i];
748 	iommu->stab = NULL;
749 	iommu->nid = nid;
750 	snprintf(iommu->name, sizeof(iommu->name), "iommu%d", i);
751 	INIT_LIST_HEAD(&iommu->windows);
752 
753 	return iommu;
754 }
755 
756 static void __init cell_iommu_init_one(struct device_node *np,
757 				       unsigned long offset)
758 {
759 	struct cbe_iommu *iommu;
760 	unsigned long base, size;
761 
762 	iommu = cell_iommu_alloc(np);
763 	if (!iommu)
764 		return;
765 
766 	/* Obtain a window for it */
767 	cell_iommu_get_window(np, &base, &size);
768 
769 	pr_debug("\ttranslating window 0x%lx...0x%lx\n",
770 		 base, base + size - 1);
771 
772 	/* Initialize the hardware */
773 	cell_iommu_setup_hardware(iommu, base, size);
774 
775 	/* Setup the iommu_table */
776 	cell_iommu_setup_window(iommu, np, base, size,
777 				offset >> IOMMU_PAGE_SHIFT);
778 }
779 
780 static void __init cell_disable_iommus(void)
781 {
782 	int node;
783 	unsigned long base, val;
784 	void __iomem *xregs, *cregs;
785 
786 	/* Make sure IOC translation is disabled on all nodes */
787 	for_each_online_node(node) {
788 		if (cell_iommu_find_ioc(node, &base))
789 			continue;
790 		xregs = ioremap(base, IOC_Reg_Size);
791 		if (xregs == NULL)
792 			continue;
793 		cregs = xregs + IOC_IOCmd_Offset;
794 
795 		pr_debug("iommu: cleaning up iommu on node %d\n", node);
796 
797 		out_be64(xregs + IOC_IOST_Origin, 0);
798 		(void)in_be64(xregs + IOC_IOST_Origin);
799 		val = in_be64(cregs + IOC_IOCmd_Cfg);
800 		val &= ~IOC_IOCmd_Cfg_TE;
801 		out_be64(cregs + IOC_IOCmd_Cfg, val);
802 		(void)in_be64(cregs + IOC_IOCmd_Cfg);
803 
804 		iounmap(xregs);
805 	}
806 }
807 
808 static int __init cell_iommu_init_disabled(void)
809 {
810 	struct device_node *np = NULL;
811 	unsigned long base = 0, size;
812 
813 	/* When no iommu is present, we use direct DMA ops */
814 	set_pci_dma_ops(&dma_direct_ops);
815 
816 	/* First make sure all IOC translation is turned off */
817 	cell_disable_iommus();
818 
819 	/* If we have no Axon, we set up the spider DMA magic offset */
820 	if (of_find_node_by_name(NULL, "axon") == NULL)
821 		cell_dma_direct_offset = SPIDER_DMA_OFFSET;
822 
823 	/* Now we need to check to see where the memory is mapped
824 	 * in PCI space. We assume that all busses use the same dma
825 	 * window which is always the case so far on Cell, thus we
826 	 * pick up the first pci-internal node we can find and check
827 	 * the DMA window from there.
828 	 */
829 	for_each_node_by_name(np, "axon") {
830 		if (np->parent == NULL || np->parent->parent != NULL)
831 			continue;
832 		if (cell_iommu_get_window(np, &base, &size) == 0)
833 			break;
834 	}
835 	if (np == NULL) {
836 		for_each_node_by_name(np, "pci-internal") {
837 			if (np->parent == NULL || np->parent->parent != NULL)
838 				continue;
839 			if (cell_iommu_get_window(np, &base, &size) == 0)
840 				break;
841 		}
842 	}
843 	of_node_put(np);
844 
845 	/* If we found a DMA window, we check if it's big enough to enclose
846 	 * all of physical memory. If not, we force enable IOMMU
847 	 */
848 	if (np && size < lmb_end_of_DRAM()) {
849 		printk(KERN_WARNING "iommu: force-enabled, dma window"
850 		       " (%ldMB) smaller than total memory (%lldMB)\n",
851 		       size >> 20, lmb_end_of_DRAM() >> 20);
852 		return -ENODEV;
853 	}
854 
855 	cell_dma_direct_offset += base;
856 
857 	if (cell_dma_direct_offset != 0)
858 		ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup;
859 
860 	printk("iommu: disabled, direct DMA offset is 0x%lx\n",
861 	       cell_dma_direct_offset);
862 
863 	return 0;
864 }
865 
866 /*
867  *  Fixed IOMMU mapping support
868  *
869  *  This code adds support for setting up a fixed IOMMU mapping on certain
870  *  cell machines. For 64-bit devices this avoids the performance overhead of
871  *  mapping and unmapping pages at runtime. 32-bit devices are unable to use
872  *  the fixed mapping.
873  *
874  *  The fixed mapping is established at boot, and maps all of physical memory
875  *  1:1 into device space at some offset. On machines with < 30 GB of memory
876  *  we setup the fixed mapping immediately above the normal IOMMU window.
877  *
878  *  For example a machine with 4GB of memory would end up with the normal
879  *  IOMMU window from 0-2GB and the fixed mapping window from 2GB to 6GB. In
880  *  this case a 64-bit device wishing to DMA to 1GB would be told to DMA to
881  *  3GB, plus any offset required by firmware. The firmware offset is encoded
882  *  in the "dma-ranges" property.
883  *
884  *  On machines with 30GB or more of memory, we are unable to place the fixed
885  *  mapping above the normal IOMMU window as we would run out of address space.
886  *  Instead we move the normal IOMMU window to coincide with the hash page
887  *  table, this region does not need to be part of the fixed mapping as no
888  *  device should ever be DMA'ing to it. We then setup the fixed mapping
889  *  from 0 to 32GB.
890  */
891 
892 static u64 cell_iommu_get_fixed_address(struct device *dev)
893 {
894 	u64 cpu_addr, size, best_size, dev_addr = OF_BAD_ADDR;
895 	struct device_node *np;
896 	const u32 *ranges = NULL;
897 	int i, len, best, naddr, nsize, pna, range_size;
898 
899 	np = of_node_get(dev->archdata.of_node);
900 	while (1) {
901 		naddr = of_n_addr_cells(np);
902 		nsize = of_n_size_cells(np);
903 		np = of_get_next_parent(np);
904 		if (!np)
905 			break;
906 
907 		ranges = of_get_property(np, "dma-ranges", &len);
908 
909 		/* Ignore empty ranges, they imply no translation required */
910 		if (ranges && len > 0)
911 			break;
912 	}
913 
914 	if (!ranges) {
915 		dev_dbg(dev, "iommu: no dma-ranges found\n");
916 		goto out;
917 	}
918 
919 	len /= sizeof(u32);
920 
921 	pna = of_n_addr_cells(np);
922 	range_size = naddr + nsize + pna;
923 
924 	/* dma-ranges format:
925 	 * child addr	: naddr cells
926 	 * parent addr	: pna cells
927 	 * size		: nsize cells
928 	 */
929 	for (i = 0, best = -1, best_size = 0; i < len; i += range_size) {
930 		cpu_addr = of_translate_dma_address(np, ranges + i + naddr);
931 		size = of_read_number(ranges + i + naddr + pna, nsize);
932 
933 		if (cpu_addr == 0 && size > best_size) {
934 			best = i;
935 			best_size = size;
936 		}
937 	}
938 
939 	if (best >= 0) {
940 		dev_addr = of_read_number(ranges + best, naddr);
941 	} else
942 		dev_dbg(dev, "iommu: no suitable range found!\n");
943 
944 out:
945 	of_node_put(np);
946 
947 	return dev_addr;
948 }
949 
950 static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask)
951 {
952 	if (!dev->dma_mask || !dma_supported(dev, dma_mask))
953 		return -EIO;
954 
955 	if (dma_mask == DMA_BIT_MASK(64) &&
956 		cell_iommu_get_fixed_address(dev) != OF_BAD_ADDR)
957 	{
958 		dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n");
959 		set_dma_ops(dev, &dma_iommu_fixed_ops);
960 	} else {
961 		dev_dbg(dev, "iommu: not 64-bit, using default ops\n");
962 		set_dma_ops(dev, get_pci_dma_ops());
963 	}
964 
965 	cell_dma_dev_setup(dev);
966 
967 	*dev->dma_mask = dma_mask;
968 
969 	return 0;
970 }
971 
972 static void cell_dma_dev_setup_fixed(struct device *dev)
973 {
974 	u64 addr;
975 
976 	addr = cell_iommu_get_fixed_address(dev) + dma_iommu_fixed_base;
977 	set_dma_offset(dev, addr);
978 
979 	dev_dbg(dev, "iommu: fixed addr = %llx\n", addr);
980 }
981 
982 static void insert_16M_pte(unsigned long addr, unsigned long *ptab,
983 			   unsigned long base_pte)
984 {
985 	unsigned long segment, offset;
986 
987 	segment = addr >> IO_SEGMENT_SHIFT;
988 	offset = (addr >> 24) - (segment << IO_PAGENO_BITS(24));
989 	ptab = ptab + (segment * (1 << 12) / sizeof(unsigned long));
990 
991 	pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n",
992 		  addr, ptab, segment, offset);
993 
994 	ptab[offset] = base_pte | (__pa(addr) & CBE_IOPTE_RPN_Mask);
995 }
996 
997 static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu,
998 	struct device_node *np, unsigned long dbase, unsigned long dsize,
999 	unsigned long fbase, unsigned long fsize)
1000 {
1001 	unsigned long base_pte, uaddr, ioaddr, *ptab;
1002 
1003 	ptab = cell_iommu_alloc_ptab(iommu, fbase, fsize, dbase, dsize, 24);
1004 
1005 	dma_iommu_fixed_base = fbase;
1006 
1007 	pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase);
1008 
1009 	base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M |
1010 		(cell_iommu_get_ioid(np) & CBE_IOPTE_IOID_Mask);
1011 
1012 	if (iommu_fixed_is_weak)
1013 		pr_info("IOMMU: Using weak ordering for fixed mapping\n");
1014 	else {
1015 		pr_info("IOMMU: Using strong ordering for fixed mapping\n");
1016 		base_pte |= CBE_IOPTE_SO_RW;
1017 	}
1018 
1019 	for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) {
1020 		/* Don't touch the dynamic region */
1021 		ioaddr = uaddr + fbase;
1022 		if (ioaddr >= dbase && ioaddr < (dbase + dsize)) {
1023 			pr_debug("iommu: fixed/dynamic overlap, skipping\n");
1024 			continue;
1025 		}
1026 
1027 		insert_16M_pte(uaddr, ptab, base_pte);
1028 	}
1029 
1030 	mb();
1031 }
1032 
1033 static int __init cell_iommu_fixed_mapping_init(void)
1034 {
1035 	unsigned long dbase, dsize, fbase, fsize, hbase, hend;
1036 	struct cbe_iommu *iommu;
1037 	struct device_node *np;
1038 
1039 	/* The fixed mapping is only supported on axon machines */
1040 	np = of_find_node_by_name(NULL, "axon");
1041 	if (!np) {
1042 		pr_debug("iommu: fixed mapping disabled, no axons found\n");
1043 		return -1;
1044 	}
1045 
1046 	/* We must have dma-ranges properties for fixed mapping to work */
1047 	np = of_find_node_with_property(NULL, "dma-ranges");
1048 	of_node_put(np);
1049 
1050 	if (!np) {
1051 		pr_debug("iommu: no dma-ranges found, no fixed mapping\n");
1052 		return -1;
1053 	}
1054 
1055 	/* The default setup is to have the fixed mapping sit after the
1056 	 * dynamic region, so find the top of the largest IOMMU window
1057 	 * on any axon, then add the size of RAM and that's our max value.
1058 	 * If that is > 32GB we have to do other shennanigans.
1059 	 */
1060 	fbase = 0;
1061 	for_each_node_by_name(np, "axon") {
1062 		cell_iommu_get_window(np, &dbase, &dsize);
1063 		fbase = max(fbase, dbase + dsize);
1064 	}
1065 
1066 	fbase = _ALIGN_UP(fbase, 1 << IO_SEGMENT_SHIFT);
1067 	fsize = lmb_phys_mem_size();
1068 
1069 	if ((fbase + fsize) <= 0x800000000)
1070 		hbase = 0; /* use the device tree window */
1071 	else {
1072 		/* If we're over 32 GB we need to cheat. We can't map all of
1073 		 * RAM with the fixed mapping, and also fit the dynamic
1074 		 * region. So try to place the dynamic region where the hash
1075 		 * table sits, drivers never need to DMA to it, we don't
1076 		 * need a fixed mapping for that area.
1077 		 */
1078 		if (!htab_address) {
1079 			pr_debug("iommu: htab is NULL, on LPAR? Huh?\n");
1080 			return -1;
1081 		}
1082 		hbase = __pa(htab_address);
1083 		hend  = hbase + htab_size_bytes;
1084 
1085 		/* The window must start and end on a segment boundary */
1086 		if ((hbase != _ALIGN_UP(hbase, 1 << IO_SEGMENT_SHIFT)) ||
1087 		    (hend != _ALIGN_UP(hend, 1 << IO_SEGMENT_SHIFT))) {
1088 			pr_debug("iommu: hash window not segment aligned\n");
1089 			return -1;
1090 		}
1091 
1092 		/* Check the hash window fits inside the real DMA window */
1093 		for_each_node_by_name(np, "axon") {
1094 			cell_iommu_get_window(np, &dbase, &dsize);
1095 
1096 			if (hbase < dbase || (hend > (dbase + dsize))) {
1097 				pr_debug("iommu: hash window doesn't fit in"
1098 					 "real DMA window\n");
1099 				return -1;
1100 			}
1101 		}
1102 
1103 		fbase = 0;
1104 	}
1105 
1106 	/* Setup the dynamic regions */
1107 	for_each_node_by_name(np, "axon") {
1108 		iommu = cell_iommu_alloc(np);
1109 		BUG_ON(!iommu);
1110 
1111 		if (hbase == 0)
1112 			cell_iommu_get_window(np, &dbase, &dsize);
1113 		else {
1114 			dbase = hbase;
1115 			dsize = htab_size_bytes;
1116 		}
1117 
1118 		printk(KERN_DEBUG "iommu: node %d, dynamic window 0x%lx-0x%lx "
1119 			"fixed window 0x%lx-0x%lx\n", iommu->nid, dbase,
1120 			 dbase + dsize, fbase, fbase + fsize);
1121 
1122 		cell_iommu_setup_stab(iommu, dbase, dsize, fbase, fsize);
1123 		iommu->ptab = cell_iommu_alloc_ptab(iommu, dbase, dsize, 0, 0,
1124 						    IOMMU_PAGE_SHIFT);
1125 		cell_iommu_setup_fixed_ptab(iommu, np, dbase, dsize,
1126 					     fbase, fsize);
1127 		cell_iommu_enable_hardware(iommu);
1128 		cell_iommu_setup_window(iommu, np, dbase, dsize, 0);
1129 	}
1130 
1131 	dma_iommu_ops.set_dma_mask = dma_set_mask_and_switch;
1132 	set_pci_dma_ops(&dma_iommu_ops);
1133 
1134 	return 0;
1135 }
1136 
1137 static int iommu_fixed_disabled;
1138 
1139 static int __init setup_iommu_fixed(char *str)
1140 {
1141 	struct device_node *pciep;
1142 
1143 	if (strcmp(str, "off") == 0)
1144 		iommu_fixed_disabled = 1;
1145 
1146 	/* If we can find a pcie-endpoint in the device tree assume that
1147 	 * we're on a triblade or a CAB so by default the fixed mapping
1148 	 * should be set to be weakly ordered; but only if the boot
1149 	 * option WASN'T set for strong ordering
1150 	 */
1151 	pciep = of_find_node_by_type(NULL, "pcie-endpoint");
1152 
1153 	if (strcmp(str, "weak") == 0 || (pciep && strcmp(str, "strong") != 0))
1154 		iommu_fixed_is_weak = 1;
1155 
1156 	of_node_put(pciep);
1157 
1158 	return 1;
1159 }
1160 __setup("iommu_fixed=", setup_iommu_fixed);
1161 
1162 static int __init cell_iommu_init(void)
1163 {
1164 	struct device_node *np;
1165 
1166 	/* If IOMMU is disabled or we have little enough RAM to not need
1167 	 * to enable it, we setup a direct mapping.
1168 	 *
1169 	 * Note: should we make sure we have the IOMMU actually disabled ?
1170 	 */
1171 	if (iommu_is_off ||
1172 	    (!iommu_force_on && lmb_end_of_DRAM() <= 0x80000000ull))
1173 		if (cell_iommu_init_disabled() == 0)
1174 			goto bail;
1175 
1176 	/* Setup various ppc_md. callbacks */
1177 	ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup;
1178 	ppc_md.tce_build = tce_build_cell;
1179 	ppc_md.tce_free = tce_free_cell;
1180 
1181 	if (!iommu_fixed_disabled && cell_iommu_fixed_mapping_init() == 0)
1182 		goto bail;
1183 
1184 	/* Create an iommu for each /axon node.  */
1185 	for_each_node_by_name(np, "axon") {
1186 		if (np->parent == NULL || np->parent->parent != NULL)
1187 			continue;
1188 		cell_iommu_init_one(np, 0);
1189 	}
1190 
1191 	/* Create an iommu for each toplevel /pci-internal node for
1192 	 * old hardware/firmware
1193 	 */
1194 	for_each_node_by_name(np, "pci-internal") {
1195 		if (np->parent == NULL || np->parent->parent != NULL)
1196 			continue;
1197 		cell_iommu_init_one(np, SPIDER_DMA_OFFSET);
1198 	}
1199 
1200 	/* Setup default PCI iommu ops */
1201 	set_pci_dma_ops(&dma_iommu_ops);
1202 
1203  bail:
1204 	/* Register callbacks on OF platform device addition/removal
1205 	 * to handle linking them to the right DMA operations
1206 	 */
1207 	bus_register_notifier(&of_platform_bus_type, &cell_of_bus_notifier);
1208 
1209 	return 0;
1210 }
1211 machine_arch_initcall(cell, cell_iommu_init);
1212 machine_arch_initcall(celleb_native, cell_iommu_init);
1213 
1214