1 /* 2 * IOMMU implementation for Cell Broadband Processor Architecture 3 * 4 * (C) Copyright IBM Corporation 2006-2008 5 * 6 * Author: Jeremy Kerr <jk@ozlabs.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #undef DEBUG 24 25 #include <linux/kernel.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/notifier.h> 29 #include <linux/of.h> 30 #include <linux/of_platform.h> 31 #include <linux/lmb.h> 32 33 #include <asm/prom.h> 34 #include <asm/iommu.h> 35 #include <asm/machdep.h> 36 #include <asm/pci-bridge.h> 37 #include <asm/udbg.h> 38 #include <asm/firmware.h> 39 #include <asm/cell-regs.h> 40 41 #include "interrupt.h" 42 43 /* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages 44 * instead of leaving them mapped to some dummy page. This can be 45 * enabled once the appropriate workarounds for spider bugs have 46 * been enabled 47 */ 48 #define CELL_IOMMU_REAL_UNMAP 49 50 /* Define CELL_IOMMU_STRICT_PROTECTION to enforce protection of 51 * IO PTEs based on the transfer direction. That can be enabled 52 * once spider-net has been fixed to pass the correct direction 53 * to the DMA mapping functions 54 */ 55 #define CELL_IOMMU_STRICT_PROTECTION 56 57 58 #define NR_IOMMUS 2 59 60 /* IOC mmap registers */ 61 #define IOC_Reg_Size 0x2000 62 63 #define IOC_IOPT_CacheInvd 0x908 64 #define IOC_IOPT_CacheInvd_NE_Mask 0xffe0000000000000ul 65 #define IOC_IOPT_CacheInvd_IOPTE_Mask 0x000003fffffffff8ul 66 #define IOC_IOPT_CacheInvd_Busy 0x0000000000000001ul 67 68 #define IOC_IOST_Origin 0x918 69 #define IOC_IOST_Origin_E 0x8000000000000000ul 70 #define IOC_IOST_Origin_HW 0x0000000000000800ul 71 #define IOC_IOST_Origin_HL 0x0000000000000400ul 72 73 #define IOC_IO_ExcpStat 0x920 74 #define IOC_IO_ExcpStat_V 0x8000000000000000ul 75 #define IOC_IO_ExcpStat_SPF_Mask 0x6000000000000000ul 76 #define IOC_IO_ExcpStat_SPF_S 0x6000000000000000ul 77 #define IOC_IO_ExcpStat_SPF_P 0x4000000000000000ul 78 #define IOC_IO_ExcpStat_ADDR_Mask 0x00000007fffff000ul 79 #define IOC_IO_ExcpStat_RW_Mask 0x0000000000000800ul 80 #define IOC_IO_ExcpStat_IOID_Mask 0x00000000000007fful 81 82 #define IOC_IO_ExcpMask 0x928 83 #define IOC_IO_ExcpMask_SFE 0x4000000000000000ul 84 #define IOC_IO_ExcpMask_PFE 0x2000000000000000ul 85 86 #define IOC_IOCmd_Offset 0x1000 87 88 #define IOC_IOCmd_Cfg 0xc00 89 #define IOC_IOCmd_Cfg_TE 0x0000800000000000ul 90 91 92 /* Segment table entries */ 93 #define IOSTE_V 0x8000000000000000ul /* valid */ 94 #define IOSTE_H 0x4000000000000000ul /* cache hint */ 95 #define IOSTE_PT_Base_RPN_Mask 0x3ffffffffffff000ul /* base RPN of IOPT */ 96 #define IOSTE_NPPT_Mask 0x0000000000000fe0ul /* no. pages in IOPT */ 97 #define IOSTE_PS_Mask 0x0000000000000007ul /* page size */ 98 #define IOSTE_PS_4K 0x0000000000000001ul /* - 4kB */ 99 #define IOSTE_PS_64K 0x0000000000000003ul /* - 64kB */ 100 #define IOSTE_PS_1M 0x0000000000000005ul /* - 1MB */ 101 #define IOSTE_PS_16M 0x0000000000000007ul /* - 16MB */ 102 103 /* Page table entries */ 104 #define IOPTE_PP_W 0x8000000000000000ul /* protection: write */ 105 #define IOPTE_PP_R 0x4000000000000000ul /* protection: read */ 106 #define IOPTE_M 0x2000000000000000ul /* coherency required */ 107 #define IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */ 108 #define IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */ 109 #define IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */ 110 #define IOPTE_H 0x0000000000000800ul /* cache hint */ 111 #define IOPTE_IOID_Mask 0x00000000000007fful /* ioid */ 112 113 114 /* IOMMU sizing */ 115 #define IO_SEGMENT_SHIFT 28 116 #define IO_PAGENO_BITS(shift) (IO_SEGMENT_SHIFT - (shift)) 117 118 /* The high bit needs to be set on every DMA address */ 119 #define SPIDER_DMA_OFFSET 0x80000000ul 120 121 struct iommu_window { 122 struct list_head list; 123 struct cbe_iommu *iommu; 124 unsigned long offset; 125 unsigned long size; 126 unsigned int ioid; 127 struct iommu_table table; 128 }; 129 130 #define NAMESIZE 8 131 struct cbe_iommu { 132 int nid; 133 char name[NAMESIZE]; 134 void __iomem *xlate_regs; 135 void __iomem *cmd_regs; 136 unsigned long *stab; 137 unsigned long *ptab; 138 void *pad_page; 139 struct list_head windows; 140 }; 141 142 /* Static array of iommus, one per node 143 * each contains a list of windows, keyed from dma_window property 144 * - on bus setup, look for a matching window, or create one 145 * - on dev setup, assign iommu_table ptr 146 */ 147 static struct cbe_iommu iommus[NR_IOMMUS]; 148 static int cbe_nr_iommus; 149 150 static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte, 151 long n_ptes) 152 { 153 unsigned long __iomem *reg; 154 unsigned long val; 155 long n; 156 157 reg = iommu->xlate_regs + IOC_IOPT_CacheInvd; 158 159 while (n_ptes > 0) { 160 /* we can invalidate up to 1 << 11 PTEs at once */ 161 n = min(n_ptes, 1l << 11); 162 val = (((n /*- 1*/) << 53) & IOC_IOPT_CacheInvd_NE_Mask) 163 | (__pa(pte) & IOC_IOPT_CacheInvd_IOPTE_Mask) 164 | IOC_IOPT_CacheInvd_Busy; 165 166 out_be64(reg, val); 167 while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy) 168 ; 169 170 n_ptes -= n; 171 pte += n; 172 } 173 } 174 175 static void tce_build_cell(struct iommu_table *tbl, long index, long npages, 176 unsigned long uaddr, enum dma_data_direction direction, 177 struct dma_attrs *attrs) 178 { 179 int i; 180 unsigned long *io_pte, base_pte; 181 struct iommu_window *window = 182 container_of(tbl, struct iommu_window, table); 183 184 /* implementing proper protection causes problems with the spidernet 185 * driver - check mapping directions later, but allow read & write by 186 * default for now.*/ 187 #ifdef CELL_IOMMU_STRICT_PROTECTION 188 /* to avoid referencing a global, we use a trick here to setup the 189 * protection bit. "prot" is setup to be 3 fields of 4 bits apprended 190 * together for each of the 3 supported direction values. It is then 191 * shifted left so that the fields matching the desired direction 192 * lands on the appropriate bits, and other bits are masked out. 193 */ 194 const unsigned long prot = 0xc48; 195 base_pte = 196 ((prot << (52 + 4 * direction)) & (IOPTE_PP_W | IOPTE_PP_R)) 197 | IOPTE_M | IOPTE_SO_RW | (window->ioid & IOPTE_IOID_Mask); 198 #else 199 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | 200 (window->ioid & IOPTE_IOID_Mask); 201 #endif 202 if (unlikely(dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))) 203 base_pte &= ~IOPTE_SO_RW; 204 205 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); 206 207 for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE) 208 io_pte[i] = base_pte | (__pa(uaddr) & IOPTE_RPN_Mask); 209 210 mb(); 211 212 invalidate_tce_cache(window->iommu, io_pte, npages); 213 214 pr_debug("tce_build_cell(index=%lx,n=%lx,dir=%d,base_pte=%lx)\n", 215 index, npages, direction, base_pte); 216 } 217 218 static void tce_free_cell(struct iommu_table *tbl, long index, long npages) 219 { 220 221 int i; 222 unsigned long *io_pte, pte; 223 struct iommu_window *window = 224 container_of(tbl, struct iommu_window, table); 225 226 pr_debug("tce_free_cell(index=%lx,n=%lx)\n", index, npages); 227 228 #ifdef CELL_IOMMU_REAL_UNMAP 229 pte = 0; 230 #else 231 /* spider bridge does PCI reads after freeing - insert a mapping 232 * to a scratch page instead of an invalid entry */ 233 pte = IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | __pa(window->iommu->pad_page) 234 | (window->ioid & IOPTE_IOID_Mask); 235 #endif 236 237 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); 238 239 for (i = 0; i < npages; i++) 240 io_pte[i] = pte; 241 242 mb(); 243 244 invalidate_tce_cache(window->iommu, io_pte, npages); 245 } 246 247 static irqreturn_t ioc_interrupt(int irq, void *data) 248 { 249 unsigned long stat; 250 struct cbe_iommu *iommu = data; 251 252 stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); 253 254 /* Might want to rate limit it */ 255 printk(KERN_ERR "iommu: DMA exception 0x%016lx\n", stat); 256 printk(KERN_ERR " V=%d, SPF=[%c%c], RW=%s, IOID=0x%04x\n", 257 !!(stat & IOC_IO_ExcpStat_V), 258 (stat & IOC_IO_ExcpStat_SPF_S) ? 'S' : ' ', 259 (stat & IOC_IO_ExcpStat_SPF_P) ? 'P' : ' ', 260 (stat & IOC_IO_ExcpStat_RW_Mask) ? "Read" : "Write", 261 (unsigned int)(stat & IOC_IO_ExcpStat_IOID_Mask)); 262 printk(KERN_ERR " page=0x%016lx\n", 263 stat & IOC_IO_ExcpStat_ADDR_Mask); 264 265 /* clear interrupt */ 266 stat &= ~IOC_IO_ExcpStat_V; 267 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat); 268 269 return IRQ_HANDLED; 270 } 271 272 static int cell_iommu_find_ioc(int nid, unsigned long *base) 273 { 274 struct device_node *np; 275 struct resource r; 276 277 *base = 0; 278 279 /* First look for new style /be nodes */ 280 for_each_node_by_name(np, "ioc") { 281 if (of_node_to_nid(np) != nid) 282 continue; 283 if (of_address_to_resource(np, 0, &r)) { 284 printk(KERN_ERR "iommu: can't get address for %s\n", 285 np->full_name); 286 continue; 287 } 288 *base = r.start; 289 of_node_put(np); 290 return 0; 291 } 292 293 /* Ok, let's try the old way */ 294 for_each_node_by_type(np, "cpu") { 295 const unsigned int *nidp; 296 const unsigned long *tmp; 297 298 nidp = of_get_property(np, "node-id", NULL); 299 if (nidp && *nidp == nid) { 300 tmp = of_get_property(np, "ioc-translation", NULL); 301 if (tmp) { 302 *base = *tmp; 303 of_node_put(np); 304 return 0; 305 } 306 } 307 } 308 309 return -ENODEV; 310 } 311 312 static void cell_iommu_setup_stab(struct cbe_iommu *iommu, 313 unsigned long dbase, unsigned long dsize, 314 unsigned long fbase, unsigned long fsize) 315 { 316 struct page *page; 317 unsigned long segments, stab_size; 318 319 segments = max(dbase + dsize, fbase + fsize) >> IO_SEGMENT_SHIFT; 320 321 pr_debug("%s: iommu[%d]: segments: %lu\n", 322 __func__, iommu->nid, segments); 323 324 /* set up the segment table */ 325 stab_size = segments * sizeof(unsigned long); 326 page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(stab_size)); 327 BUG_ON(!page); 328 iommu->stab = page_address(page); 329 memset(iommu->stab, 0, stab_size); 330 } 331 332 static unsigned long *cell_iommu_alloc_ptab(struct cbe_iommu *iommu, 333 unsigned long base, unsigned long size, unsigned long gap_base, 334 unsigned long gap_size, unsigned long page_shift) 335 { 336 struct page *page; 337 int i; 338 unsigned long reg, segments, pages_per_segment, ptab_size, 339 n_pte_pages, start_seg, *ptab; 340 341 start_seg = base >> IO_SEGMENT_SHIFT; 342 segments = size >> IO_SEGMENT_SHIFT; 343 pages_per_segment = 1ull << IO_PAGENO_BITS(page_shift); 344 /* PTEs for each segment must start on a 4K bounday */ 345 pages_per_segment = max(pages_per_segment, 346 (1 << 12) / sizeof(unsigned long)); 347 348 ptab_size = segments * pages_per_segment * sizeof(unsigned long); 349 pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __func__, 350 iommu->nid, ptab_size, get_order(ptab_size)); 351 page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size)); 352 BUG_ON(!page); 353 354 ptab = page_address(page); 355 memset(ptab, 0, ptab_size); 356 357 /* number of 4K pages needed for a page table */ 358 n_pte_pages = (pages_per_segment * sizeof(unsigned long)) >> 12; 359 360 pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n", 361 __func__, iommu->nid, iommu->stab, ptab, 362 n_pte_pages); 363 364 /* initialise the STEs */ 365 reg = IOSTE_V | ((n_pte_pages - 1) << 5); 366 367 switch (page_shift) { 368 case 12: reg |= IOSTE_PS_4K; break; 369 case 16: reg |= IOSTE_PS_64K; break; 370 case 20: reg |= IOSTE_PS_1M; break; 371 case 24: reg |= IOSTE_PS_16M; break; 372 default: BUG(); 373 } 374 375 gap_base = gap_base >> IO_SEGMENT_SHIFT; 376 gap_size = gap_size >> IO_SEGMENT_SHIFT; 377 378 pr_debug("Setting up IOMMU stab:\n"); 379 for (i = start_seg; i < (start_seg + segments); i++) { 380 if (i >= gap_base && i < (gap_base + gap_size)) { 381 pr_debug("\toverlap at %d, skipping\n", i); 382 continue; 383 } 384 iommu->stab[i] = reg | (__pa(ptab) + (n_pte_pages << 12) * 385 (i - start_seg)); 386 pr_debug("\t[%d] 0x%016lx\n", i, iommu->stab[i]); 387 } 388 389 return ptab; 390 } 391 392 static void cell_iommu_enable_hardware(struct cbe_iommu *iommu) 393 { 394 int ret; 395 unsigned long reg, xlate_base; 396 unsigned int virq; 397 398 if (cell_iommu_find_ioc(iommu->nid, &xlate_base)) 399 panic("%s: missing IOC register mappings for node %d\n", 400 __func__, iommu->nid); 401 402 iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size); 403 iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset; 404 405 /* ensure that the STEs have updated */ 406 mb(); 407 408 /* setup interrupts for the iommu. */ 409 reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); 410 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, 411 reg & ~IOC_IO_ExcpStat_V); 412 out_be64(iommu->xlate_regs + IOC_IO_ExcpMask, 413 IOC_IO_ExcpMask_PFE | IOC_IO_ExcpMask_SFE); 414 415 virq = irq_create_mapping(NULL, 416 IIC_IRQ_IOEX_ATI | (iommu->nid << IIC_IRQ_NODE_SHIFT)); 417 BUG_ON(virq == NO_IRQ); 418 419 ret = request_irq(virq, ioc_interrupt, IRQF_DISABLED, 420 iommu->name, iommu); 421 BUG_ON(ret); 422 423 /* set the IOC segment table origin register (and turn on the iommu) */ 424 reg = IOC_IOST_Origin_E | __pa(iommu->stab) | IOC_IOST_Origin_HW; 425 out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg); 426 in_be64(iommu->xlate_regs + IOC_IOST_Origin); 427 428 /* turn on IO translation */ 429 reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE; 430 out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg); 431 } 432 433 static void cell_iommu_setup_hardware(struct cbe_iommu *iommu, 434 unsigned long base, unsigned long size) 435 { 436 cell_iommu_setup_stab(iommu, base, size, 0, 0); 437 iommu->ptab = cell_iommu_alloc_ptab(iommu, base, size, 0, 0, 438 IOMMU_PAGE_SHIFT); 439 cell_iommu_enable_hardware(iommu); 440 } 441 442 #if 0/* Unused for now */ 443 static struct iommu_window *find_window(struct cbe_iommu *iommu, 444 unsigned long offset, unsigned long size) 445 { 446 struct iommu_window *window; 447 448 /* todo: check for overlapping (but not equal) windows) */ 449 450 list_for_each_entry(window, &(iommu->windows), list) { 451 if (window->offset == offset && window->size == size) 452 return window; 453 } 454 455 return NULL; 456 } 457 #endif 458 459 static inline u32 cell_iommu_get_ioid(struct device_node *np) 460 { 461 const u32 *ioid; 462 463 ioid = of_get_property(np, "ioid", NULL); 464 if (ioid == NULL) { 465 printk(KERN_WARNING "iommu: missing ioid for %s using 0\n", 466 np->full_name); 467 return 0; 468 } 469 470 return *ioid; 471 } 472 473 static struct iommu_window * __init 474 cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np, 475 unsigned long offset, unsigned long size, 476 unsigned long pte_offset) 477 { 478 struct iommu_window *window; 479 struct page *page; 480 u32 ioid; 481 482 ioid = cell_iommu_get_ioid(np); 483 484 window = kmalloc_node(sizeof(*window), GFP_KERNEL, iommu->nid); 485 BUG_ON(window == NULL); 486 487 window->offset = offset; 488 window->size = size; 489 window->ioid = ioid; 490 window->iommu = iommu; 491 492 window->table.it_blocksize = 16; 493 window->table.it_base = (unsigned long)iommu->ptab; 494 window->table.it_index = iommu->nid; 495 window->table.it_offset = (offset >> IOMMU_PAGE_SHIFT) + pte_offset; 496 window->table.it_size = size >> IOMMU_PAGE_SHIFT; 497 498 iommu_init_table(&window->table, iommu->nid); 499 500 pr_debug("\tioid %d\n", window->ioid); 501 pr_debug("\tblocksize %ld\n", window->table.it_blocksize); 502 pr_debug("\tbase 0x%016lx\n", window->table.it_base); 503 pr_debug("\toffset 0x%lx\n", window->table.it_offset); 504 pr_debug("\tsize %ld\n", window->table.it_size); 505 506 list_add(&window->list, &iommu->windows); 507 508 if (offset != 0) 509 return window; 510 511 /* We need to map and reserve the first IOMMU page since it's used 512 * by the spider workaround. In theory, we only need to do that when 513 * running on spider but it doesn't really matter. 514 * 515 * This code also assumes that we have a window that starts at 0, 516 * which is the case on all spider based blades. 517 */ 518 page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0); 519 BUG_ON(!page); 520 iommu->pad_page = page_address(page); 521 clear_page(iommu->pad_page); 522 523 __set_bit(0, window->table.it_map); 524 tce_build_cell(&window->table, window->table.it_offset, 1, 525 (unsigned long)iommu->pad_page, DMA_TO_DEVICE, NULL); 526 window->table.it_hint = window->table.it_blocksize; 527 528 return window; 529 } 530 531 static struct cbe_iommu *cell_iommu_for_node(int nid) 532 { 533 int i; 534 535 for (i = 0; i < cbe_nr_iommus; i++) 536 if (iommus[i].nid == nid) 537 return &iommus[i]; 538 return NULL; 539 } 540 541 static unsigned long cell_dma_direct_offset; 542 543 static unsigned long dma_iommu_fixed_base; 544 545 /* iommu_fixed_is_weak is set if booted with iommu_fixed=weak */ 546 static int iommu_fixed_is_weak; 547 548 static struct iommu_table *cell_get_iommu_table(struct device *dev) 549 { 550 struct iommu_window *window; 551 struct cbe_iommu *iommu; 552 struct dev_archdata *archdata = &dev->archdata; 553 554 /* Current implementation uses the first window available in that 555 * node's iommu. We -might- do something smarter later though it may 556 * never be necessary 557 */ 558 iommu = cell_iommu_for_node(archdata->numa_node); 559 if (iommu == NULL || list_empty(&iommu->windows)) { 560 printk(KERN_ERR "iommu: missing iommu for %s (node %d)\n", 561 archdata->of_node ? archdata->of_node->full_name : "?", 562 archdata->numa_node); 563 return NULL; 564 } 565 window = list_entry(iommu->windows.next, struct iommu_window, list); 566 567 return &window->table; 568 } 569 570 /* A coherent allocation implies strong ordering */ 571 572 static void *dma_fixed_alloc_coherent(struct device *dev, size_t size, 573 dma_addr_t *dma_handle, gfp_t flag) 574 { 575 if (iommu_fixed_is_weak) 576 return iommu_alloc_coherent(dev, cell_get_iommu_table(dev), 577 size, dma_handle, 578 device_to_mask(dev), flag, 579 dev->archdata.numa_node); 580 else 581 return dma_direct_ops.alloc_coherent(dev, size, dma_handle, 582 flag); 583 } 584 585 static void dma_fixed_free_coherent(struct device *dev, size_t size, 586 void *vaddr, dma_addr_t dma_handle) 587 { 588 if (iommu_fixed_is_weak) 589 iommu_free_coherent(cell_get_iommu_table(dev), size, vaddr, 590 dma_handle); 591 else 592 dma_direct_ops.free_coherent(dev, size, vaddr, dma_handle); 593 } 594 595 static dma_addr_t dma_fixed_map_single(struct device *dev, void *ptr, 596 size_t size, 597 enum dma_data_direction direction, 598 struct dma_attrs *attrs) 599 { 600 if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) 601 return dma_direct_ops.map_single(dev, ptr, size, direction, 602 attrs); 603 else 604 return iommu_map_single(dev, cell_get_iommu_table(dev), ptr, 605 size, device_to_mask(dev), direction, 606 attrs); 607 } 608 609 static void dma_fixed_unmap_single(struct device *dev, dma_addr_t dma_addr, 610 size_t size, 611 enum dma_data_direction direction, 612 struct dma_attrs *attrs) 613 { 614 if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) 615 dma_direct_ops.unmap_single(dev, dma_addr, size, direction, 616 attrs); 617 else 618 iommu_unmap_single(cell_get_iommu_table(dev), dma_addr, size, 619 direction, attrs); 620 } 621 622 static int dma_fixed_map_sg(struct device *dev, struct scatterlist *sg, 623 int nents, enum dma_data_direction direction, 624 struct dma_attrs *attrs) 625 { 626 if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) 627 return dma_direct_ops.map_sg(dev, sg, nents, direction, attrs); 628 else 629 return iommu_map_sg(dev, cell_get_iommu_table(dev), sg, nents, 630 device_to_mask(dev), direction, attrs); 631 } 632 633 static void dma_fixed_unmap_sg(struct device *dev, struct scatterlist *sg, 634 int nents, enum dma_data_direction direction, 635 struct dma_attrs *attrs) 636 { 637 if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) 638 dma_direct_ops.unmap_sg(dev, sg, nents, direction, attrs); 639 else 640 iommu_unmap_sg(cell_get_iommu_table(dev), sg, nents, direction, 641 attrs); 642 } 643 644 static int dma_fixed_dma_supported(struct device *dev, u64 mask) 645 { 646 return mask == DMA_64BIT_MASK; 647 } 648 649 static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask); 650 651 struct dma_mapping_ops dma_iommu_fixed_ops = { 652 .alloc_coherent = dma_fixed_alloc_coherent, 653 .free_coherent = dma_fixed_free_coherent, 654 .map_single = dma_fixed_map_single, 655 .unmap_single = dma_fixed_unmap_single, 656 .map_sg = dma_fixed_map_sg, 657 .unmap_sg = dma_fixed_unmap_sg, 658 .dma_supported = dma_fixed_dma_supported, 659 .set_dma_mask = dma_set_mask_and_switch, 660 }; 661 662 static void cell_dma_dev_setup_fixed(struct device *dev); 663 664 static void cell_dma_dev_setup(struct device *dev) 665 { 666 struct dev_archdata *archdata = &dev->archdata; 667 668 /* Order is important here, these are not mutually exclusive */ 669 if (get_dma_ops(dev) == &dma_iommu_fixed_ops) 670 cell_dma_dev_setup_fixed(dev); 671 else if (get_pci_dma_ops() == &dma_iommu_ops) 672 archdata->dma_data = cell_get_iommu_table(dev); 673 else if (get_pci_dma_ops() == &dma_direct_ops) 674 archdata->dma_data = (void *)cell_dma_direct_offset; 675 else 676 BUG(); 677 } 678 679 static void cell_pci_dma_dev_setup(struct pci_dev *dev) 680 { 681 cell_dma_dev_setup(&dev->dev); 682 } 683 684 static int cell_of_bus_notify(struct notifier_block *nb, unsigned long action, 685 void *data) 686 { 687 struct device *dev = data; 688 689 /* We are only intereted in device addition */ 690 if (action != BUS_NOTIFY_ADD_DEVICE) 691 return 0; 692 693 /* We use the PCI DMA ops */ 694 dev->archdata.dma_ops = get_pci_dma_ops(); 695 696 cell_dma_dev_setup(dev); 697 698 return 0; 699 } 700 701 static struct notifier_block cell_of_bus_notifier = { 702 .notifier_call = cell_of_bus_notify 703 }; 704 705 static int __init cell_iommu_get_window(struct device_node *np, 706 unsigned long *base, 707 unsigned long *size) 708 { 709 const void *dma_window; 710 unsigned long index; 711 712 /* Use ibm,dma-window if available, else, hard code ! */ 713 dma_window = of_get_property(np, "ibm,dma-window", NULL); 714 if (dma_window == NULL) { 715 *base = 0; 716 *size = 0x80000000u; 717 return -ENODEV; 718 } 719 720 of_parse_dma_window(np, dma_window, &index, base, size); 721 return 0; 722 } 723 724 static struct cbe_iommu * __init cell_iommu_alloc(struct device_node *np) 725 { 726 struct cbe_iommu *iommu; 727 int nid, i; 728 729 /* Get node ID */ 730 nid = of_node_to_nid(np); 731 if (nid < 0) { 732 printk(KERN_ERR "iommu: failed to get node for %s\n", 733 np->full_name); 734 return NULL; 735 } 736 pr_debug("iommu: setting up iommu for node %d (%s)\n", 737 nid, np->full_name); 738 739 /* XXX todo: If we can have multiple windows on the same IOMMU, which 740 * isn't the case today, we probably want here to check wether the 741 * iommu for that node is already setup. 742 * However, there might be issue with getting the size right so let's 743 * ignore that for now. We might want to completely get rid of the 744 * multiple window support since the cell iommu supports per-page ioids 745 */ 746 747 if (cbe_nr_iommus >= NR_IOMMUS) { 748 printk(KERN_ERR "iommu: too many IOMMUs detected ! (%s)\n", 749 np->full_name); 750 return NULL; 751 } 752 753 /* Init base fields */ 754 i = cbe_nr_iommus++; 755 iommu = &iommus[i]; 756 iommu->stab = NULL; 757 iommu->nid = nid; 758 snprintf(iommu->name, sizeof(iommu->name), "iommu%d", i); 759 INIT_LIST_HEAD(&iommu->windows); 760 761 return iommu; 762 } 763 764 static void __init cell_iommu_init_one(struct device_node *np, 765 unsigned long offset) 766 { 767 struct cbe_iommu *iommu; 768 unsigned long base, size; 769 770 iommu = cell_iommu_alloc(np); 771 if (!iommu) 772 return; 773 774 /* Obtain a window for it */ 775 cell_iommu_get_window(np, &base, &size); 776 777 pr_debug("\ttranslating window 0x%lx...0x%lx\n", 778 base, base + size - 1); 779 780 /* Initialize the hardware */ 781 cell_iommu_setup_hardware(iommu, base, size); 782 783 /* Setup the iommu_table */ 784 cell_iommu_setup_window(iommu, np, base, size, 785 offset >> IOMMU_PAGE_SHIFT); 786 } 787 788 static void __init cell_disable_iommus(void) 789 { 790 int node; 791 unsigned long base, val; 792 void __iomem *xregs, *cregs; 793 794 /* Make sure IOC translation is disabled on all nodes */ 795 for_each_online_node(node) { 796 if (cell_iommu_find_ioc(node, &base)) 797 continue; 798 xregs = ioremap(base, IOC_Reg_Size); 799 if (xregs == NULL) 800 continue; 801 cregs = xregs + IOC_IOCmd_Offset; 802 803 pr_debug("iommu: cleaning up iommu on node %d\n", node); 804 805 out_be64(xregs + IOC_IOST_Origin, 0); 806 (void)in_be64(xregs + IOC_IOST_Origin); 807 val = in_be64(cregs + IOC_IOCmd_Cfg); 808 val &= ~IOC_IOCmd_Cfg_TE; 809 out_be64(cregs + IOC_IOCmd_Cfg, val); 810 (void)in_be64(cregs + IOC_IOCmd_Cfg); 811 812 iounmap(xregs); 813 } 814 } 815 816 static int __init cell_iommu_init_disabled(void) 817 { 818 struct device_node *np = NULL; 819 unsigned long base = 0, size; 820 821 /* When no iommu is present, we use direct DMA ops */ 822 set_pci_dma_ops(&dma_direct_ops); 823 824 /* First make sure all IOC translation is turned off */ 825 cell_disable_iommus(); 826 827 /* If we have no Axon, we set up the spider DMA magic offset */ 828 if (of_find_node_by_name(NULL, "axon") == NULL) 829 cell_dma_direct_offset = SPIDER_DMA_OFFSET; 830 831 /* Now we need to check to see where the memory is mapped 832 * in PCI space. We assume that all busses use the same dma 833 * window which is always the case so far on Cell, thus we 834 * pick up the first pci-internal node we can find and check 835 * the DMA window from there. 836 */ 837 for_each_node_by_name(np, "axon") { 838 if (np->parent == NULL || np->parent->parent != NULL) 839 continue; 840 if (cell_iommu_get_window(np, &base, &size) == 0) 841 break; 842 } 843 if (np == NULL) { 844 for_each_node_by_name(np, "pci-internal") { 845 if (np->parent == NULL || np->parent->parent != NULL) 846 continue; 847 if (cell_iommu_get_window(np, &base, &size) == 0) 848 break; 849 } 850 } 851 of_node_put(np); 852 853 /* If we found a DMA window, we check if it's big enough to enclose 854 * all of physical memory. If not, we force enable IOMMU 855 */ 856 if (np && size < lmb_end_of_DRAM()) { 857 printk(KERN_WARNING "iommu: force-enabled, dma window" 858 " (%ldMB) smaller than total memory (%ldMB)\n", 859 size >> 20, lmb_end_of_DRAM() >> 20); 860 return -ENODEV; 861 } 862 863 cell_dma_direct_offset += base; 864 865 if (cell_dma_direct_offset != 0) 866 ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup; 867 868 printk("iommu: disabled, direct DMA offset is 0x%lx\n", 869 cell_dma_direct_offset); 870 871 return 0; 872 } 873 874 /* 875 * Fixed IOMMU mapping support 876 * 877 * This code adds support for setting up a fixed IOMMU mapping on certain 878 * cell machines. For 64-bit devices this avoids the performance overhead of 879 * mapping and unmapping pages at runtime. 32-bit devices are unable to use 880 * the fixed mapping. 881 * 882 * The fixed mapping is established at boot, and maps all of physical memory 883 * 1:1 into device space at some offset. On machines with < 30 GB of memory 884 * we setup the fixed mapping immediately above the normal IOMMU window. 885 * 886 * For example a machine with 4GB of memory would end up with the normal 887 * IOMMU window from 0-2GB and the fixed mapping window from 2GB to 6GB. In 888 * this case a 64-bit device wishing to DMA to 1GB would be told to DMA to 889 * 3GB, plus any offset required by firmware. The firmware offset is encoded 890 * in the "dma-ranges" property. 891 * 892 * On machines with 30GB or more of memory, we are unable to place the fixed 893 * mapping above the normal IOMMU window as we would run out of address space. 894 * Instead we move the normal IOMMU window to coincide with the hash page 895 * table, this region does not need to be part of the fixed mapping as no 896 * device should ever be DMA'ing to it. We then setup the fixed mapping 897 * from 0 to 32GB. 898 */ 899 900 static u64 cell_iommu_get_fixed_address(struct device *dev) 901 { 902 u64 cpu_addr, size, best_size, dev_addr = OF_BAD_ADDR; 903 struct device_node *np; 904 const u32 *ranges = NULL; 905 int i, len, best, naddr, nsize, pna, range_size; 906 907 np = of_node_get(dev->archdata.of_node); 908 while (1) { 909 naddr = of_n_addr_cells(np); 910 nsize = of_n_size_cells(np); 911 np = of_get_next_parent(np); 912 if (!np) 913 break; 914 915 ranges = of_get_property(np, "dma-ranges", &len); 916 917 /* Ignore empty ranges, they imply no translation required */ 918 if (ranges && len > 0) 919 break; 920 } 921 922 if (!ranges) { 923 dev_dbg(dev, "iommu: no dma-ranges found\n"); 924 goto out; 925 } 926 927 len /= sizeof(u32); 928 929 pna = of_n_addr_cells(np); 930 range_size = naddr + nsize + pna; 931 932 /* dma-ranges format: 933 * child addr : naddr cells 934 * parent addr : pna cells 935 * size : nsize cells 936 */ 937 for (i = 0, best = -1, best_size = 0; i < len; i += range_size) { 938 cpu_addr = of_translate_dma_address(np, ranges + i + naddr); 939 size = of_read_number(ranges + i + naddr + pna, nsize); 940 941 if (cpu_addr == 0 && size > best_size) { 942 best = i; 943 best_size = size; 944 } 945 } 946 947 if (best >= 0) { 948 dev_addr = of_read_number(ranges + best, naddr); 949 } else 950 dev_dbg(dev, "iommu: no suitable range found!\n"); 951 952 out: 953 of_node_put(np); 954 955 return dev_addr; 956 } 957 958 static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask) 959 { 960 if (!dev->dma_mask || !dma_supported(dev, dma_mask)) 961 return -EIO; 962 963 if (dma_mask == DMA_BIT_MASK(64) && 964 cell_iommu_get_fixed_address(dev) != OF_BAD_ADDR) 965 { 966 dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n"); 967 set_dma_ops(dev, &dma_iommu_fixed_ops); 968 } else { 969 dev_dbg(dev, "iommu: not 64-bit, using default ops\n"); 970 set_dma_ops(dev, get_pci_dma_ops()); 971 } 972 973 cell_dma_dev_setup(dev); 974 975 *dev->dma_mask = dma_mask; 976 977 return 0; 978 } 979 980 static void cell_dma_dev_setup_fixed(struct device *dev) 981 { 982 struct dev_archdata *archdata = &dev->archdata; 983 u64 addr; 984 985 addr = cell_iommu_get_fixed_address(dev) + dma_iommu_fixed_base; 986 archdata->dma_data = (void *)addr; 987 988 dev_dbg(dev, "iommu: fixed addr = %lx\n", addr); 989 } 990 991 static void insert_16M_pte(unsigned long addr, unsigned long *ptab, 992 unsigned long base_pte) 993 { 994 unsigned long segment, offset; 995 996 segment = addr >> IO_SEGMENT_SHIFT; 997 offset = (addr >> 24) - (segment << IO_PAGENO_BITS(24)); 998 ptab = ptab + (segment * (1 << 12) / sizeof(unsigned long)); 999 1000 pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n", 1001 addr, ptab, segment, offset); 1002 1003 ptab[offset] = base_pte | (__pa(addr) & IOPTE_RPN_Mask); 1004 } 1005 1006 static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu, 1007 struct device_node *np, unsigned long dbase, unsigned long dsize, 1008 unsigned long fbase, unsigned long fsize) 1009 { 1010 unsigned long base_pte, uaddr, ioaddr, *ptab; 1011 1012 ptab = cell_iommu_alloc_ptab(iommu, fbase, fsize, dbase, dsize, 24); 1013 1014 dma_iommu_fixed_base = fbase; 1015 1016 pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase); 1017 1018 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M 1019 | (cell_iommu_get_ioid(np) & IOPTE_IOID_Mask); 1020 1021 if (iommu_fixed_is_weak) 1022 pr_info("IOMMU: Using weak ordering for fixed mapping\n"); 1023 else { 1024 pr_info("IOMMU: Using strong ordering for fixed mapping\n"); 1025 base_pte |= IOPTE_SO_RW; 1026 } 1027 1028 for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) { 1029 /* Don't touch the dynamic region */ 1030 ioaddr = uaddr + fbase; 1031 if (ioaddr >= dbase && ioaddr < (dbase + dsize)) { 1032 pr_debug("iommu: fixed/dynamic overlap, skipping\n"); 1033 continue; 1034 } 1035 1036 insert_16M_pte(uaddr, ptab, base_pte); 1037 } 1038 1039 mb(); 1040 } 1041 1042 static int __init cell_iommu_fixed_mapping_init(void) 1043 { 1044 unsigned long dbase, dsize, fbase, fsize, hbase, hend; 1045 struct cbe_iommu *iommu; 1046 struct device_node *np; 1047 1048 /* The fixed mapping is only supported on axon machines */ 1049 np = of_find_node_by_name(NULL, "axon"); 1050 if (!np) { 1051 pr_debug("iommu: fixed mapping disabled, no axons found\n"); 1052 return -1; 1053 } 1054 1055 /* We must have dma-ranges properties for fixed mapping to work */ 1056 for (np = NULL; (np = of_find_all_nodes(np));) { 1057 if (of_find_property(np, "dma-ranges", NULL)) 1058 break; 1059 } 1060 of_node_put(np); 1061 1062 if (!np) { 1063 pr_debug("iommu: no dma-ranges found, no fixed mapping\n"); 1064 return -1; 1065 } 1066 1067 /* The default setup is to have the fixed mapping sit after the 1068 * dynamic region, so find the top of the largest IOMMU window 1069 * on any axon, then add the size of RAM and that's our max value. 1070 * If that is > 32GB we have to do other shennanigans. 1071 */ 1072 fbase = 0; 1073 for_each_node_by_name(np, "axon") { 1074 cell_iommu_get_window(np, &dbase, &dsize); 1075 fbase = max(fbase, dbase + dsize); 1076 } 1077 1078 fbase = _ALIGN_UP(fbase, 1 << IO_SEGMENT_SHIFT); 1079 fsize = lmb_phys_mem_size(); 1080 1081 if ((fbase + fsize) <= 0x800000000) 1082 hbase = 0; /* use the device tree window */ 1083 else { 1084 /* If we're over 32 GB we need to cheat. We can't map all of 1085 * RAM with the fixed mapping, and also fit the dynamic 1086 * region. So try to place the dynamic region where the hash 1087 * table sits, drivers never need to DMA to it, we don't 1088 * need a fixed mapping for that area. 1089 */ 1090 if (!htab_address) { 1091 pr_debug("iommu: htab is NULL, on LPAR? Huh?\n"); 1092 return -1; 1093 } 1094 hbase = __pa(htab_address); 1095 hend = hbase + htab_size_bytes; 1096 1097 /* The window must start and end on a segment boundary */ 1098 if ((hbase != _ALIGN_UP(hbase, 1 << IO_SEGMENT_SHIFT)) || 1099 (hend != _ALIGN_UP(hend, 1 << IO_SEGMENT_SHIFT))) { 1100 pr_debug("iommu: hash window not segment aligned\n"); 1101 return -1; 1102 } 1103 1104 /* Check the hash window fits inside the real DMA window */ 1105 for_each_node_by_name(np, "axon") { 1106 cell_iommu_get_window(np, &dbase, &dsize); 1107 1108 if (hbase < dbase || (hend > (dbase + dsize))) { 1109 pr_debug("iommu: hash window doesn't fit in" 1110 "real DMA window\n"); 1111 return -1; 1112 } 1113 } 1114 1115 fbase = 0; 1116 } 1117 1118 /* Setup the dynamic regions */ 1119 for_each_node_by_name(np, "axon") { 1120 iommu = cell_iommu_alloc(np); 1121 BUG_ON(!iommu); 1122 1123 if (hbase == 0) 1124 cell_iommu_get_window(np, &dbase, &dsize); 1125 else { 1126 dbase = hbase; 1127 dsize = htab_size_bytes; 1128 } 1129 1130 printk(KERN_DEBUG "iommu: node %d, dynamic window 0x%lx-0x%lx " 1131 "fixed window 0x%lx-0x%lx\n", iommu->nid, dbase, 1132 dbase + dsize, fbase, fbase + fsize); 1133 1134 cell_iommu_setup_stab(iommu, dbase, dsize, fbase, fsize); 1135 iommu->ptab = cell_iommu_alloc_ptab(iommu, dbase, dsize, 0, 0, 1136 IOMMU_PAGE_SHIFT); 1137 cell_iommu_setup_fixed_ptab(iommu, np, dbase, dsize, 1138 fbase, fsize); 1139 cell_iommu_enable_hardware(iommu); 1140 cell_iommu_setup_window(iommu, np, dbase, dsize, 0); 1141 } 1142 1143 dma_iommu_ops.set_dma_mask = dma_set_mask_and_switch; 1144 set_pci_dma_ops(&dma_iommu_ops); 1145 1146 return 0; 1147 } 1148 1149 static int iommu_fixed_disabled; 1150 1151 static int __init setup_iommu_fixed(char *str) 1152 { 1153 if (strcmp(str, "off") == 0) 1154 iommu_fixed_disabled = 1; 1155 1156 else if (strcmp(str, "weak") == 0) 1157 iommu_fixed_is_weak = 1; 1158 1159 return 1; 1160 } 1161 __setup("iommu_fixed=", setup_iommu_fixed); 1162 1163 static int __init cell_iommu_init(void) 1164 { 1165 struct device_node *np; 1166 1167 /* If IOMMU is disabled or we have little enough RAM to not need 1168 * to enable it, we setup a direct mapping. 1169 * 1170 * Note: should we make sure we have the IOMMU actually disabled ? 1171 */ 1172 if (iommu_is_off || 1173 (!iommu_force_on && lmb_end_of_DRAM() <= 0x80000000ull)) 1174 if (cell_iommu_init_disabled() == 0) 1175 goto bail; 1176 1177 /* Setup various ppc_md. callbacks */ 1178 ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup; 1179 ppc_md.tce_build = tce_build_cell; 1180 ppc_md.tce_free = tce_free_cell; 1181 1182 if (!iommu_fixed_disabled && cell_iommu_fixed_mapping_init() == 0) 1183 goto bail; 1184 1185 /* Create an iommu for each /axon node. */ 1186 for_each_node_by_name(np, "axon") { 1187 if (np->parent == NULL || np->parent->parent != NULL) 1188 continue; 1189 cell_iommu_init_one(np, 0); 1190 } 1191 1192 /* Create an iommu for each toplevel /pci-internal node for 1193 * old hardware/firmware 1194 */ 1195 for_each_node_by_name(np, "pci-internal") { 1196 if (np->parent == NULL || np->parent->parent != NULL) 1197 continue; 1198 cell_iommu_init_one(np, SPIDER_DMA_OFFSET); 1199 } 1200 1201 /* Setup default PCI iommu ops */ 1202 set_pci_dma_ops(&dma_iommu_ops); 1203 1204 bail: 1205 /* Register callbacks on OF platform device addition/removal 1206 * to handle linking them to the right DMA operations 1207 */ 1208 bus_register_notifier(&of_platform_bus_type, &cell_of_bus_notifier); 1209 1210 return 0; 1211 } 1212 machine_arch_initcall(cell, cell_iommu_init); 1213 machine_arch_initcall(celleb_native, cell_iommu_init); 1214 1215