1 #ifndef ASM_CELL_PIC_H
2 #define ASM_CELL_PIC_H
3 #ifdef __KERNEL__
4 /*
5  * Mapping of IIC pending bits into per-node interrupt numbers.
6  *
7  * Interrupt numbers are in the range 0...0x1ff where the top bit
8  * (0x100) represent the source node. Only 2 nodes are supported with
9  * the current code though it's trivial to extend that if necessary using
10  * higher level bits
11  *
12  * The bottom 8 bits are split into 2 type bits and 6 data bits that
13  * depend on the type:
14  *
15  * 00 (0x00 | data) : normal interrupt. data is (class << 4) | source
16  * 01 (0x40 | data) : IO exception. data is the exception number as
17  *                    defined by bit numbers in IIC_SR
18  * 10 (0x80 | data) : IPI. data is the IPI number (obtained from the priority)
19  *                    and node is always 0 (IPIs are per-cpu, their source is
20  *                    not relevant)
21  * 11 (0xc0 | data) : reserved
22  *
23  * In addition, interrupt number 0x80000000 is defined as always invalid
24  * (that is the node field is expected to never extend to move than 23 bits)
25  *
26  */
27 
28 enum {
29 	IIC_IRQ_INVALID		= 0x80000000u,
30 	IIC_IRQ_NODE_MASK	= 0x100,
31 	IIC_IRQ_NODE_SHIFT	= 8,
32 	IIC_IRQ_MAX		= 0x1ff,
33 	IIC_IRQ_TYPE_MASK	= 0xc0,
34 	IIC_IRQ_TYPE_NORMAL	= 0x00,
35 	IIC_IRQ_TYPE_IOEXC	= 0x40,
36 	IIC_IRQ_TYPE_IPI	= 0x80,
37 	IIC_IRQ_CLASS_SHIFT	= 4,
38 	IIC_IRQ_CLASS_0		= 0x00,
39 	IIC_IRQ_CLASS_1		= 0x10,
40 	IIC_IRQ_CLASS_2		= 0x20,
41 	IIC_SOURCE_COUNT	= 0x200,
42 
43 	/* Here are defined the various source/dest units. Avoid using those
44 	 * definitions if you can, they are mostly here for reference
45 	 */
46 	IIC_UNIT_SPU_0		= 0x4,
47 	IIC_UNIT_SPU_1		= 0x7,
48 	IIC_UNIT_SPU_2		= 0x3,
49 	IIC_UNIT_SPU_3		= 0x8,
50 	IIC_UNIT_SPU_4		= 0x2,
51 	IIC_UNIT_SPU_5		= 0x9,
52 	IIC_UNIT_SPU_6		= 0x1,
53 	IIC_UNIT_SPU_7		= 0xa,
54 	IIC_UNIT_IOC_0		= 0x0,
55 	IIC_UNIT_IOC_1		= 0xb,
56 	IIC_UNIT_THREAD_0	= 0xe, /* target only */
57 	IIC_UNIT_THREAD_1	= 0xf, /* target only */
58 	IIC_UNIT_IIC		= 0xe, /* source only (IO exceptions) */
59 
60 	/* Base numbers for the external interrupts */
61 	IIC_IRQ_EXT_IOIF0	=
62 		IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_0,
63 	IIC_IRQ_EXT_IOIF1	=
64 		IIC_IRQ_TYPE_NORMAL | IIC_IRQ_CLASS_2 | IIC_UNIT_IOC_1,
65 
66 	/* Base numbers for the IIC_ISR interrupts */
67 	IIC_IRQ_IOEX_TMI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 63,
68 	IIC_IRQ_IOEX_PMI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 62,
69 	IIC_IRQ_IOEX_ATI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 61,
70 	IIC_IRQ_IOEX_MATBFI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 60,
71 	IIC_IRQ_IOEX_ELDI	= IIC_IRQ_TYPE_IOEXC | IIC_IRQ_CLASS_1 | 59,
72 
73 	/* Which bits in IIC_ISR are edge sensitive */
74 	IIC_ISR_EDGE_MASK	= 0x4ul,
75 };
76 
77 extern void iic_init_IRQ(void);
78 extern void iic_message_pass(int cpu, int msg);
79 extern void iic_request_IPIs(void);
80 extern void iic_setup_cpu(void);
81 
82 extern u8 iic_get_target_id(int cpu);
83 
84 extern void spider_init_IRQ(void);
85 
86 extern void iic_set_interrupt_routing(int cpu, int thread, int priority);
87 
88 #endif
89 #endif /* ASM_CELL_PIC_H */
90