1 /* 2 * Cell Internal Interrupt Controller 3 * 4 * Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org) 5 * IBM, Corp. 6 * 7 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 8 * 9 * Author: Arnd Bergmann <arndb@de.ibm.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 * 25 * TODO: 26 * - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers 27 * vs node numbers in the setup code 28 * - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from 29 * a non-active node to the active node) 30 */ 31 32 #include <linux/interrupt.h> 33 #include <linux/irq.h> 34 #include <linux/module.h> 35 #include <linux/percpu.h> 36 #include <linux/types.h> 37 #include <linux/ioport.h> 38 39 #include <asm/io.h> 40 #include <asm/pgtable.h> 41 #include <asm/prom.h> 42 #include <asm/ptrace.h> 43 #include <asm/machdep.h> 44 45 #include "interrupt.h" 46 #include "cbe_regs.h" 47 48 struct iic { 49 struct cbe_iic_thread_regs __iomem *regs; 50 u8 target_id; 51 u8 eoi_stack[16]; 52 int eoi_ptr; 53 struct device_node *node; 54 }; 55 56 static DEFINE_PER_CPU(struct iic, iic); 57 #define IIC_NODE_COUNT 2 58 static struct irq_host *iic_host; 59 60 /* Convert between "pending" bits and hw irq number */ 61 static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits) 62 { 63 unsigned char unit = bits.source & 0xf; 64 unsigned char node = bits.source >> 4; 65 unsigned char class = bits.class & 3; 66 67 /* Decode IPIs */ 68 if (bits.flags & CBE_IIC_IRQ_IPI) 69 return IIC_IRQ_TYPE_IPI | (bits.prio >> 4); 70 else 71 return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit; 72 } 73 74 static void iic_mask(unsigned int irq) 75 { 76 } 77 78 static void iic_unmask(unsigned int irq) 79 { 80 } 81 82 static void iic_eoi(unsigned int irq) 83 { 84 struct iic *iic = &__get_cpu_var(iic); 85 out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]); 86 BUG_ON(iic->eoi_ptr < 0); 87 } 88 89 static struct irq_chip iic_chip = { 90 .typename = " CELL-IIC ", 91 .mask = iic_mask, 92 .unmask = iic_unmask, 93 .eoi = iic_eoi, 94 }; 95 96 97 static void iic_ioexc_eoi(unsigned int irq) 98 { 99 } 100 101 static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc) 102 { 103 struct cbe_iic_regs __iomem *node_iic = (void __iomem *)desc->handler_data; 104 unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC; 105 unsigned long bits, ack; 106 int cascade; 107 108 for (;;) { 109 bits = in_be64(&node_iic->iic_is); 110 if (bits == 0) 111 break; 112 /* pre-ack edge interrupts */ 113 ack = bits & IIC_ISR_EDGE_MASK; 114 if (ack) 115 out_be64(&node_iic->iic_is, ack); 116 /* handle them */ 117 for (cascade = 63; cascade >= 0; cascade--) 118 if (bits & (0x8000000000000000UL >> cascade)) { 119 unsigned int cirq = 120 irq_linear_revmap(iic_host, 121 base | cascade); 122 if (cirq != NO_IRQ) 123 generic_handle_irq(cirq); 124 } 125 /* post-ack level interrupts */ 126 ack = bits & ~IIC_ISR_EDGE_MASK; 127 if (ack) 128 out_be64(&node_iic->iic_is, ack); 129 } 130 desc->chip->eoi(irq); 131 } 132 133 134 static struct irq_chip iic_ioexc_chip = { 135 .typename = " CELL-IOEX", 136 .mask = iic_mask, 137 .unmask = iic_unmask, 138 .eoi = iic_ioexc_eoi, 139 }; 140 141 /* Get an IRQ number from the pending state register of the IIC */ 142 static unsigned int iic_get_irq(void) 143 { 144 struct cbe_iic_pending_bits pending; 145 struct iic *iic; 146 unsigned int virq; 147 148 iic = &__get_cpu_var(iic); 149 *(unsigned long *) &pending = 150 in_be64((unsigned long __iomem *) &iic->regs->pending_destr); 151 if (!(pending.flags & CBE_IIC_IRQ_VALID)) 152 return NO_IRQ; 153 virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending)); 154 if (virq == NO_IRQ) 155 return NO_IRQ; 156 iic->eoi_stack[++iic->eoi_ptr] = pending.prio; 157 BUG_ON(iic->eoi_ptr > 15); 158 return virq; 159 } 160 161 #ifdef CONFIG_SMP 162 163 /* Use the highest interrupt priorities for IPI */ 164 static inline int iic_ipi_to_irq(int ipi) 165 { 166 return IIC_IRQ_TYPE_IPI + 0xf - ipi; 167 } 168 169 void iic_setup_cpu(void) 170 { 171 out_be64(&__get_cpu_var(iic).regs->prio, 0xff); 172 } 173 174 void iic_cause_IPI(int cpu, int mesg) 175 { 176 out_be64(&per_cpu(iic, cpu).regs->generate, (0xf - mesg) << 4); 177 } 178 179 u8 iic_get_target_id(int cpu) 180 { 181 return per_cpu(iic, cpu).target_id; 182 } 183 EXPORT_SYMBOL_GPL(iic_get_target_id); 184 185 struct irq_host *iic_get_irq_host(int node) 186 { 187 return iic_host; 188 } 189 EXPORT_SYMBOL_GPL(iic_get_irq_host); 190 191 192 static irqreturn_t iic_ipi_action(int irq, void *dev_id) 193 { 194 int ipi = (int)(long)dev_id; 195 196 smp_message_recv(ipi); 197 198 return IRQ_HANDLED; 199 } 200 static void iic_request_ipi(int ipi, const char *name) 201 { 202 int virq; 203 204 virq = irq_create_mapping(iic_host, iic_ipi_to_irq(ipi)); 205 if (virq == NO_IRQ) { 206 printk(KERN_ERR 207 "iic: failed to map IPI %s\n", name); 208 return; 209 } 210 if (request_irq(virq, iic_ipi_action, IRQF_DISABLED, name, 211 (void *)(long)ipi)) 212 printk(KERN_ERR 213 "iic: failed to request IPI %s\n", name); 214 } 215 216 void iic_request_IPIs(void) 217 { 218 iic_request_ipi(PPC_MSG_CALL_FUNCTION, "IPI-call"); 219 iic_request_ipi(PPC_MSG_RESCHEDULE, "IPI-resched"); 220 #ifdef CONFIG_DEBUGGER 221 iic_request_ipi(PPC_MSG_DEBUGGER_BREAK, "IPI-debug"); 222 #endif /* CONFIG_DEBUGGER */ 223 } 224 225 #endif /* CONFIG_SMP */ 226 227 228 static int iic_host_match(struct irq_host *h, struct device_node *node) 229 { 230 return device_is_compatible(node, 231 "IBM,CBEA-Internal-Interrupt-Controller"); 232 } 233 234 static int iic_host_map(struct irq_host *h, unsigned int virq, 235 irq_hw_number_t hw) 236 { 237 switch (hw & IIC_IRQ_TYPE_MASK) { 238 case IIC_IRQ_TYPE_IPI: 239 set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq); 240 break; 241 case IIC_IRQ_TYPE_IOEXC: 242 set_irq_chip_and_handler(virq, &iic_ioexc_chip, 243 handle_fasteoi_irq); 244 break; 245 default: 246 set_irq_chip_and_handler(virq, &iic_chip, handle_fasteoi_irq); 247 } 248 return 0; 249 } 250 251 static int iic_host_xlate(struct irq_host *h, struct device_node *ct, 252 u32 *intspec, unsigned int intsize, 253 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 254 255 { 256 unsigned int node, ext, unit, class; 257 const u32 *val; 258 259 if (!device_is_compatible(ct, 260 "IBM,CBEA-Internal-Interrupt-Controller")) 261 return -ENODEV; 262 if (intsize != 1) 263 return -ENODEV; 264 val = get_property(ct, "#interrupt-cells", NULL); 265 if (val == NULL || *val != 1) 266 return -ENODEV; 267 268 node = intspec[0] >> 24; 269 ext = (intspec[0] >> 16) & 0xff; 270 class = (intspec[0] >> 8) & 0xff; 271 unit = intspec[0] & 0xff; 272 273 /* Check if node is in supported range */ 274 if (node > 1) 275 return -EINVAL; 276 277 /* Build up interrupt number, special case for IO exceptions */ 278 *out_hwirq = (node << IIC_IRQ_NODE_SHIFT); 279 if (unit == IIC_UNIT_IIC && class == 1) 280 *out_hwirq |= IIC_IRQ_TYPE_IOEXC | ext; 281 else 282 *out_hwirq |= IIC_IRQ_TYPE_NORMAL | 283 (class << IIC_IRQ_CLASS_SHIFT) | unit; 284 285 /* Dummy flags, ignored by iic code */ 286 *out_flags = IRQ_TYPE_EDGE_RISING; 287 288 return 0; 289 } 290 291 static struct irq_host_ops iic_host_ops = { 292 .match = iic_host_match, 293 .map = iic_host_map, 294 .xlate = iic_host_xlate, 295 }; 296 297 static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr, 298 struct device_node *node) 299 { 300 /* XXX FIXME: should locate the linux CPU number from the HW cpu 301 * number properly. We are lucky for now 302 */ 303 struct iic *iic = &per_cpu(iic, hw_cpu); 304 305 iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs)); 306 BUG_ON(iic->regs == NULL); 307 308 iic->target_id = ((hw_cpu & 2) << 3) | ((hw_cpu & 1) ? 0xf : 0xe); 309 iic->eoi_stack[0] = 0xff; 310 iic->node = of_node_get(node); 311 out_be64(&iic->regs->prio, 0); 312 313 printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n", 314 hw_cpu, iic->target_id, node->full_name); 315 } 316 317 static int __init setup_iic(void) 318 { 319 struct device_node *dn; 320 struct resource r0, r1; 321 unsigned int node, cascade, found = 0; 322 struct cbe_iic_regs __iomem *node_iic; 323 const u32 *np; 324 325 for (dn = NULL; 326 (dn = of_find_node_by_name(dn,"interrupt-controller")) != NULL;) { 327 if (!device_is_compatible(dn, 328 "IBM,CBEA-Internal-Interrupt-Controller")) 329 continue; 330 np = get_property(dn, "ibm,interrupt-server-ranges", NULL); 331 if (np == NULL) { 332 printk(KERN_WARNING "IIC: CPU association not found\n"); 333 of_node_put(dn); 334 return -ENODEV; 335 } 336 if (of_address_to_resource(dn, 0, &r0) || 337 of_address_to_resource(dn, 1, &r1)) { 338 printk(KERN_WARNING "IIC: Can't resolve addresses\n"); 339 of_node_put(dn); 340 return -ENODEV; 341 } 342 found++; 343 init_one_iic(np[0], r0.start, dn); 344 init_one_iic(np[1], r1.start, dn); 345 346 /* Setup cascade for IO exceptions. XXX cleanup tricks to get 347 * node vs CPU etc... 348 * Note that we configure the IIC_IRR here with a hard coded 349 * priority of 1. We might want to improve that later. 350 */ 351 node = np[0] >> 1; 352 node_iic = cbe_get_cpu_iic_regs(np[0]); 353 cascade = node << IIC_IRQ_NODE_SHIFT; 354 cascade |= 1 << IIC_IRQ_CLASS_SHIFT; 355 cascade |= IIC_UNIT_IIC; 356 cascade = irq_create_mapping(iic_host, cascade); 357 if (cascade == NO_IRQ) 358 continue; 359 /* 360 * irq_data is a generic pointer that gets passed back 361 * to us later, so the forced cast is fine. 362 */ 363 set_irq_data(cascade, (void __force *)node_iic); 364 set_irq_chained_handler(cascade , iic_ioexc_cascade); 365 out_be64(&node_iic->iic_ir, 366 (1 << 12) /* priority */ | 367 (node << 4) /* dest node */ | 368 IIC_UNIT_THREAD_0 /* route them to thread 0 */); 369 /* Flush pending (make sure it triggers if there is 370 * anything pending 371 */ 372 out_be64(&node_iic->iic_is, 0xfffffffffffffffful); 373 } 374 375 if (found) 376 return 0; 377 else 378 return -ENODEV; 379 } 380 381 void __init iic_init_IRQ(void) 382 { 383 /* Setup an irq host data structure */ 384 iic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, IIC_SOURCE_COUNT, 385 &iic_host_ops, IIC_IRQ_INVALID); 386 BUG_ON(iic_host == NULL); 387 irq_set_default_host(iic_host); 388 389 /* Discover and initialize iics */ 390 if (setup_iic() < 0) 391 panic("IIC: Failed to initialize !\n"); 392 393 /* Set master interrupt handling function */ 394 ppc_md.get_irq = iic_get_irq; 395 396 /* Enable on current CPU */ 397 iic_setup_cpu(); 398 } 399 400 void iic_set_interrupt_routing(int cpu, int thread, int priority) 401 { 402 struct cbe_iic_regs __iomem *iic_regs = cbe_get_cpu_iic_regs(cpu); 403 u64 iic_ir = 0; 404 int node = cpu >> 1; 405 406 /* Set which node and thread will handle the next interrupt */ 407 iic_ir |= CBE_IIC_IR_PRIO(priority) | 408 CBE_IIC_IR_DEST_NODE(node); 409 if (thread == 0) 410 iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_0); 411 else 412 iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_1); 413 out_be64(&iic_regs->iic_ir, iic_ir); 414 } 415