1config PPC_CELL
2	bool
3	default n
4
5config PPC_CELL_COMMON
6	bool
7	select PPC_CELL
8	select PPC_DCR_MMIO
9	select PPC_INDIRECT_IO
10	select PPC_NATIVE
11	select PPC_RTAS
12
13config PPC_CELL_NATIVE
14	bool
15	select PPC_CELL_COMMON
16	select PPC_OF_PLATFORM_PCI
17	select MPIC
18	select IBM_NEW_EMAC_EMAC4
19	select IBM_NEW_EMAC_RGMII
20	select IBM_NEW_EMAC_ZMII #test only
21	select IBM_NEW_EMAC_TAH  #test only
22	default n
23
24config PPC_IBM_CELL_BLADE
25	bool "IBM Cell Blade"
26	depends on PPC64 && PPC_BOOK3S
27	select PPC_CELL_NATIVE
28	select MMIO_NVRAM
29	select PPC_UDBG_16550
30	select UDBG_RTAS_CONSOLE
31
32config PPC_CELLEB
33	bool "Toshiba's Cell Reference Set 'Celleb' Architecture"
34	depends on PPC64 && PPC_BOOK3S
35	select PPC_CELL_NATIVE
36	select HAS_TXX9_SERIAL
37	select PPC_UDBG_BEAT
38	select USB_OHCI_BIG_ENDIAN_MMIO
39	select USB_EHCI_BIG_ENDIAN_MMIO
40
41config PPC_CELL_QPACE
42	bool "IBM Cell - QPACE"
43	depends on PPC64 && PPC_BOOK3S
44	select PPC_CELL_COMMON
45
46config AXON_MSI
47	bool
48	depends on PPC_IBM_CELL_BLADE && PCI_MSI
49	default y
50
51menu "Cell Broadband Engine options"
52	depends on PPC_CELL
53
54config SPU_FS
55	tristate "SPU file system"
56	default m
57	depends on PPC_CELL
58	select SPU_BASE
59	select MEMORY_HOTPLUG
60	help
61	  The SPU file system is used to access Synergistic Processing
62	  Units on machines implementing the Broadband Processor
63	  Architecture.
64
65config SPU_FS_64K_LS
66	bool "Use 64K pages to map SPE local  store"
67	# we depend on PPC_MM_SLICES for now rather than selecting
68	# it because we depend on hugetlbfs hooks being present. We
69	# will fix that when the generic code has been improved to
70	# not require hijacking hugetlbfs hooks.
71	depends on SPU_FS && PPC_MM_SLICES && !PPC_64K_PAGES
72	default y
73	select PPC_HAS_HASH_64K
74	help
75	  This option causes SPE local stores to be mapped in process
76	  address spaces using 64K pages while the rest of the kernel
77	  uses 4K pages. This can improve performances of applications
78	  using multiple SPEs by lowering the TLB pressure on them.
79
80config SPU_TRACE
81	tristate "SPU event tracing support"
82	depends on SPU_FS && MARKERS
83	help
84	  This option allows reading a trace of spu-related events through
85	  the sputrace file in procfs.
86
87config SPU_BASE
88	bool
89	default n
90
91config CBE_RAS
92	bool "RAS features for bare metal Cell BE"
93	depends on PPC_CELL_NATIVE
94	default y
95
96config PPC_IBM_CELL_RESETBUTTON
97	bool "IBM Cell Blade Pinhole reset button"
98	depends on CBE_RAS && PPC_IBM_CELL_BLADE
99	default y
100	help
101	  Support Pinhole Resetbutton on IBM Cell blades.
102	  This adds a method to trigger system reset via front panel pinhole button.
103
104config PPC_IBM_CELL_POWERBUTTON
105	tristate "IBM Cell Blade power button"
106	depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV
107	default y
108	help
109	  Support Powerbutton on IBM Cell blades.
110	  This will enable the powerbutton as an input device.
111
112config CBE_THERM
113	tristate "CBE thermal support"
114	default m
115	depends on CBE_RAS && SPU_BASE
116
117config CBE_CPUFREQ
118	tristate "CBE frequency scaling"
119	depends on CBE_RAS && CPU_FREQ
120	default m
121	help
122	  This adds the cpufreq driver for Cell BE processors.
123	  For details, take a look at <file:Documentation/cpu-freq/>.
124	  If you don't have such processor, say N
125
126config CBE_CPUFREQ_PMI_ENABLE
127	bool "CBE frequency scaling using PMI interface"
128	depends on CBE_CPUFREQ && EXPERIMENTAL
129	default n
130	help
131	  Select this, if you want to use the PMI interface
132	  to switch frequencies. Using PMI, the
133	  processor will not only be able to run at lower speed,
134	  but also at lower core voltage.
135
136config CBE_CPUFREQ_PMI
137	tristate
138	depends on CBE_CPUFREQ_PMI_ENABLE
139	default CBE_CPUFREQ
140
141config PPC_PMI
142	tristate
143	default y
144	depends on CBE_CPUFREQ_PMI || PPC_IBM_CELL_POWERBUTTON
145	help
146	  PMI (Platform Management Interrupt) is a way to
147	  communicate with the BMC (Baseboard Management Controller).
148	  It is used in some IBM Cell blades.
149
150config CBE_CPUFREQ_SPU_GOVERNOR
151	tristate "CBE frequency scaling based on SPU usage"
152	depends on SPU_FS && CPU_FREQ
153	default m
154	help
155	  This governor checks for spu usage to adjust the cpu frequency.
156	  If no spu is running on a given cpu, that cpu will be throttled to
157	  the minimal possible frequency.
158
159endmenu
160
161config OPROFILE_CELL
162	def_bool y
163	depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE
164
165