1config PPC_CELL
2	bool
3	default n
4
5config PPC_CELL_COMMON
6	bool
7	select PPC_CELL
8	select PPC_DCR_MMIO
9	select PPC_INDIRECT_PIO
10	select PPC_INDIRECT_MMIO
11	select PPC_NATIVE
12	select PPC_RTAS
13	select IRQ_EDGE_EOI_HANDLER
14
15config PPC_CELL_NATIVE
16	bool
17	select PPC_CELL_COMMON
18	select MPIC
19	select PPC_IO_WORKAROUNDS
20	select IBM_EMAC_EMAC4 if IBM_EMAC
21	select IBM_EMAC_RGMII if IBM_EMAC
22	select IBM_EMAC_ZMII if IBM_EMAC #test only
23	select IBM_EMAC_TAH if IBM_EMAC  #test only
24	default n
25
26config PPC_IBM_CELL_BLADE
27	bool "IBM Cell Blade"
28	depends on PPC64 && PPC_BOOK3S && CPU_BIG_ENDIAN
29	select PPC_CELL_NATIVE
30	select PPC_OF_PLATFORM_PCI
31	select PCI
32	select MMIO_NVRAM
33	select PPC_UDBG_16550
34	select UDBG_RTAS_CONSOLE
35
36config AXON_MSI
37	bool
38	depends on PPC_IBM_CELL_BLADE && PCI_MSI
39	default y
40
41menu "Cell Broadband Engine options"
42	depends on PPC_CELL
43
44config SPU_FS
45	tristate "SPU file system"
46	default m
47	depends on PPC_CELL
48	select SPU_BASE
49	help
50	  The SPU file system is used to access Synergistic Processing
51	  Units on machines implementing the Broadband Processor
52	  Architecture.
53
54config SPU_BASE
55	bool
56	default n
57	select PPC_COPRO_BASE
58
59config CBE_RAS
60	bool "RAS features for bare metal Cell BE"
61	depends on PPC_CELL_NATIVE
62	default y
63
64config PPC_IBM_CELL_RESETBUTTON
65	bool "IBM Cell Blade Pinhole reset button"
66	depends on CBE_RAS && PPC_IBM_CELL_BLADE
67	default y
68	help
69	  Support Pinhole Resetbutton on IBM Cell blades.
70	  This adds a method to trigger system reset via front panel pinhole button.
71
72config PPC_IBM_CELL_POWERBUTTON
73	tristate "IBM Cell Blade power button"
74	depends on PPC_IBM_CELL_BLADE && INPUT_EVDEV
75	default y
76	help
77	  Support Powerbutton on IBM Cell blades.
78	  This will enable the powerbutton as an input device.
79
80config CBE_THERM
81	tristate "CBE thermal support"
82	default m
83	depends on CBE_RAS && SPU_BASE
84
85config PPC_PMI
86	tristate
87	default y
88	depends on CPU_FREQ_CBE_PMI || PPC_IBM_CELL_POWERBUTTON
89	help
90	  PMI (Platform Management Interrupt) is a way to
91	  communicate with the BMC (Baseboard Management Controller).
92	  It is used in some IBM Cell blades.
93
94config CBE_CPUFREQ_SPU_GOVERNOR
95	tristate "CBE frequency scaling based on SPU usage"
96	depends on SPU_FS && CPU_FREQ
97	default m
98	help
99	  This governor checks for spu usage to adjust the cpu frequency.
100	  If no spu is running on a given cpu, that cpu will be throttled to
101	  the minimal possible frequency.
102
103endmenu
104
105config OPROFILE_CELL
106	def_bool y
107	depends on PPC_CELL_NATIVE && (OPROFILE = m || OPROFILE = y) && SPU_BASE
108
109