xref: /openbmc/linux/arch/powerpc/platforms/Kconfig (revision 5d0e4d78) 
1menu "Platform support"
2
3source "arch/powerpc/platforms/powernv/Kconfig"
4source "arch/powerpc/platforms/pseries/Kconfig"
5source "arch/powerpc/platforms/chrp/Kconfig"
6source "arch/powerpc/platforms/512x/Kconfig"
7source "arch/powerpc/platforms/52xx/Kconfig"
8source "arch/powerpc/platforms/powermac/Kconfig"
9source "arch/powerpc/platforms/maple/Kconfig"
10source "arch/powerpc/platforms/pasemi/Kconfig"
11source "arch/powerpc/platforms/ps3/Kconfig"
12source "arch/powerpc/platforms/cell/Kconfig"
13source "arch/powerpc/platforms/8xx/Kconfig"
14source "arch/powerpc/platforms/82xx/Kconfig"
15source "arch/powerpc/platforms/83xx/Kconfig"
16source "arch/powerpc/platforms/85xx/Kconfig"
17source "arch/powerpc/platforms/86xx/Kconfig"
18source "arch/powerpc/platforms/embedded6xx/Kconfig"
19source "arch/powerpc/platforms/44x/Kconfig"
20source "arch/powerpc/platforms/40x/Kconfig"
21source "arch/powerpc/platforms/amigaone/Kconfig"
22
23config KVM_GUEST
24	bool "KVM Guest support"
25	default n
26	select EPAPR_PARAVIRT
27	---help---
28	  This option enables various optimizations for running under the KVM
29	  hypervisor. Overhead for the kernel when not running inside KVM should
30	  be minimal.
31
32	  In case of doubt, say Y
33
34config EPAPR_PARAVIRT
35	bool "ePAPR para-virtualization support"
36	default n
37	help
38	  Enables ePAPR para-virtualization support for guests.
39
40	  In case of doubt, say Y
41
42config PPC_NATIVE
43	bool
44	depends on 6xx || PPC64
45	help
46	  Support for running natively on the hardware, i.e. without
47	  a hypervisor. This option is not user-selectable but should
48	  be selected by all platforms that need it.
49
50config PPC_OF_BOOT_TRAMPOLINE
51	bool "Support booting from Open Firmware or yaboot"
52	depends on 6xx || PPC64
53	default y
54	help
55	  Support from booting from Open Firmware or yaboot using an
56	  Open Firmware client interface. This enables the kernel to
57	  communicate with open firmware to retrieve system information
58	  such as the device tree.
59
60	  In case of doubt, say Y
61
62config PPC_DT_CPU_FTRS
63	bool "Device-tree based CPU feature discovery & setup"
64	depends on PPC_BOOK3S_64
65	default y
66	help
67	  This enables code to use a new device tree binding for describing CPU
68	  compatibility and features. Saying Y here will attempt to use the new
69	  binding if the firmware provides it. Currently only the skiboot
70	  firmware provides this binding.
71	  If you're not sure say Y.
72
73config UDBG_RTAS_CONSOLE
74	bool "RTAS based debug console"
75	depends on PPC_RTAS
76	default n
77
78config PPC_SMP_MUXED_IPI
79	bool
80	help
81	  Select this opton if your platform supports SMP and your
82	  interrupt controller provides less than 4 interrupts to each
83	  cpu.	This will enable the generic code to multiplex the 4
84	  messages on to one ipi.
85
86config IPIC
87	bool
88	default n
89
90config MPIC
91	bool
92	default n
93
94config MPIC_TIMER
95	bool "MPIC Global Timer"
96	depends on MPIC && FSL_SOC
97	default n
98	help
99	  The MPIC global timer is a hardware timer inside the
100	  Freescale PIC complying with OpenPIC standard. When the
101	  specified interval times out, the hardware timer generates
102	  an interrupt. The driver currently is only tested on fsl
103	  chip, but it can potentially support other global timers
104	  complying with the OpenPIC standard.
105
106config FSL_MPIC_TIMER_WAKEUP
107	tristate "Freescale MPIC global timer wakeup driver"
108	depends on FSL_SOC &&  MPIC_TIMER && PM
109	default n
110	help
111	  The driver provides a way to wake up the system by MPIC
112	  timer.
113	  e.g. "echo 5 > /sys/devices/system/mpic/timer_wakeup"
114
115config PPC_EPAPR_HV_PIC
116	bool
117	default n
118	select EPAPR_PARAVIRT
119
120config MPIC_WEIRD
121	bool
122	default n
123
124config MPIC_MSGR
125	bool "MPIC message register support"
126	depends on MPIC
127	default n
128	help
129	  Enables support for the MPIC message registers.  These
130	  registers are used for inter-processor communication.
131
132config PPC_I8259
133	bool
134	default n
135
136config U3_DART
137	bool
138	depends on PPC64
139	default n
140
141config PPC_RTAS
142	bool
143	default n
144
145config RTAS_ERROR_LOGGING
146	bool
147	depends on PPC_RTAS
148	default n
149
150config PPC_RTAS_DAEMON
151	bool
152	depends on PPC_RTAS
153	default n
154
155config RTAS_PROC
156	bool "Proc interface to RTAS"
157	depends on PPC_RTAS && PROC_FS
158	default y
159
160config RTAS_FLASH
161	tristate "Firmware flash interface"
162	depends on PPC64 && RTAS_PROC
163
164config MMIO_NVRAM
165	bool
166	default n
167
168config MPIC_U3_HT_IRQS
169	bool
170	default n
171
172config MPIC_BROKEN_REGREAD
173	bool
174	depends on MPIC
175	help
176	  This option enables a MPIC driver workaround for some chips
177	  that have a bug that causes some interrupt source information
178	  to not read back properly. It is safe to use on other chips as
179	  well, but enabling it uses about 8KB of memory to keep copies
180	  of the register contents in software.
181
182config EEH
183	bool
184	depends on (PPC_POWERNV || PPC_PSERIES) && PCI
185	default y
186
187config PPC_MPC106
188	bool
189	default n
190
191config PPC_970_NAP
192	bool
193	default n
194
195config PPC_P7_NAP
196	bool
197	default n
198
199config PPC_INDIRECT_PIO
200	bool
201	select GENERIC_IOMAP
202
203config PPC_INDIRECT_MMIO
204	bool
205
206config PPC_IO_WORKAROUNDS
207	bool
208
209source "drivers/cpufreq/Kconfig"
210
211menu "CPUIdle driver"
212
213source "drivers/cpuidle/Kconfig"
214
215endmenu
216
217config PPC601_SYNC_FIX
218	bool "Workarounds for PPC601 bugs"
219	depends on 6xx && PPC_PMAC
220	help
221	  Some versions of the PPC601 (the first PowerPC chip) have bugs which
222	  mean that extra synchronization instructions are required near
223	  certain instructions, typically those that make major changes to the
224	  CPU state.  These extra instructions reduce performance slightly.
225	  If you say N here, these extra instructions will not be included,
226	  resulting in a kernel which will run faster but may not run at all
227	  on some systems with the PPC601 chip.
228
229	  If in doubt, say Y here.
230
231config TAU
232	bool "On-chip CPU temperature sensor support"
233	depends on 6xx
234	help
235	  G3 and G4 processors have an on-chip temperature sensor called the
236	  'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
237	  temperature within 2-4 degrees Celsius. This option shows the current
238	  on-die temperature in /proc/cpuinfo if the cpu supports it.
239
240	  Unfortunately, on some chip revisions, this sensor is very inaccurate
241	  and in many cases, does not work at all, so don't assume the cpu
242	  temp is actually what /proc/cpuinfo says it is.
243
244config TAU_INT
245	bool "Interrupt driven TAU driver (DANGEROUS)"
246	depends on TAU
247	---help---
248	  The TAU supports an interrupt driven mode which causes an interrupt
249	  whenever the temperature goes out of range. This is the fastest way
250	  to get notified the temp has exceeded a range. With this option off,
251	  a timer is used to re-check the temperature periodically.
252
253	  However, on some cpus it appears that the TAU interrupt hardware
254	  is buggy and can cause a situation which would lead unexplained hard
255	  lockups.
256
257	  Unless you are extending the TAU driver, or enjoy kernel/hardware
258	  debugging, leave this option off.
259
260config TAU_AVERAGE
261	bool "Average high and low temp"
262	depends on TAU
263	---help---
264	  The TAU hardware can compare the temperature to an upper and lower
265	  bound.  The default behavior is to show both the upper and lower
266	  bound in /proc/cpuinfo. If the range is large, the temperature is
267	  either changing a lot, or the TAU hardware is broken (likely on some
268	  G4's). If the range is small (around 4 degrees), the temperature is
269	  relatively stable.  If you say Y here, a single temperature value,
270	  halfway between the upper and lower bounds, will be reported in
271	  /proc/cpuinfo.
272
273	  If in doubt, say N here.
274
275config QE_GPIO
276	bool "QE GPIO support"
277	depends on QUICC_ENGINE
278	select GPIOLIB
279	help
280	  Say Y here if you're going to use hardware that connects to the
281	  QE GPIOs.
282
283config CPM2
284	bool "Enable support for the CPM2 (Communications Processor Module)"
285	depends on (FSL_SOC_BOOKE && PPC32) || 8260
286	select CPM
287	select PPC_PCI_CHOICE
288	select GPIOLIB
289	help
290	  The CPM2 (Communications Processor Module) is a coprocessor on
291	  embedded CPUs made by Freescale.  Selecting this option means that
292	  you wish to build a kernel for a machine with a CPM2 coprocessor
293	  on it (826x, 827x, 8560).
294
295config AXON_RAM
296	tristate "Axon DDR2 memory device driver"
297	depends on PPC_IBM_CELL_BLADE && BLOCK
298	select DAX
299	default m
300	help
301	  It registers one block device per Axon's DDR2 memory bank found
302	  on a system. Block devices are called axonram?, their major and
303	  minor numbers are available in /proc/devices, /proc/partitions or
304	  in /sys/block/axonram?/dev.
305
306config FSL_ULI1575
307	bool
308	default n
309	select GENERIC_ISA_DMA
310	help
311	  Supports for the ULI1575 PCIe south bridge that exists on some
312	  Freescale reference boards. The boards all use the ULI in pretty
313	  much the same way.
314
315config CPM
316	bool
317	select GENERIC_ALLOCATOR
318
319config OF_RTC
320	bool
321	help
322	  Uses information from the OF or flattened device tree to instantiate
323	  platform devices for direct mapped RTC chips like the DS1742 or DS1743.
324
325config GEN_RTC
326	bool "Use the platform RTC operations from user space"
327	select RTC_CLASS
328	select RTC_DRV_GENERIC
329	help
330	  This option provides backwards compatibility with the old gen_rtc.ko
331	  module that was traditionally used for old PowerPC machines.
332	  Platforms should migrate to enabling the RTC_DRV_GENERIC by hand
333	  replacing their get_rtc_time/set_rtc_time callbacks with
334	  a proper RTC device driver.
335
336config SIMPLE_GPIO
337	bool "Support for simple, memory-mapped GPIO controllers"
338	depends on PPC
339	select GPIOLIB
340	help
341	  Say Y here to support simple, memory-mapped GPIO controllers.
342	  These are usually BCSRs used to control board's switches, LEDs,
343	  chip-selects, Ethernet/USB PHY's power and various other small
344	  on-board peripherals.
345
346config MCU_MPC8349EMITX
347	bool "MPC8349E-mITX MCU driver"
348	depends on I2C=y && PPC_83xx
349	select GPIOLIB
350	help
351	  Say Y here to enable soft power-off functionality on the Freescale
352	  boards with the MPC8349E-mITX-compatible MCU chips. This driver will
353	  also register MCU GPIOs with the generic GPIO API, so you'll able
354	  to use MCU pins as GPIOs.
355
356config XILINX_PCI
357	bool "Xilinx PCI host bridge support"
358	depends on PCI && XILINX_VIRTEX
359
360endmenu
361