1# SPDX-License-Identifier: GPL-2.0 2menu "Platform support" 3 4source "arch/powerpc/platforms/powernv/Kconfig" 5source "arch/powerpc/platforms/pseries/Kconfig" 6source "arch/powerpc/platforms/chrp/Kconfig" 7source "arch/powerpc/platforms/512x/Kconfig" 8source "arch/powerpc/platforms/52xx/Kconfig" 9source "arch/powerpc/platforms/powermac/Kconfig" 10source "arch/powerpc/platforms/maple/Kconfig" 11source "arch/powerpc/platforms/pasemi/Kconfig" 12source "arch/powerpc/platforms/ps3/Kconfig" 13source "arch/powerpc/platforms/cell/Kconfig" 14source "arch/powerpc/platforms/8xx/Kconfig" 15source "arch/powerpc/platforms/82xx/Kconfig" 16source "arch/powerpc/platforms/83xx/Kconfig" 17source "arch/powerpc/platforms/85xx/Kconfig" 18source "arch/powerpc/platforms/86xx/Kconfig" 19source "arch/powerpc/platforms/embedded6xx/Kconfig" 20source "arch/powerpc/platforms/44x/Kconfig" 21source "arch/powerpc/platforms/40x/Kconfig" 22source "arch/powerpc/platforms/amigaone/Kconfig" 23 24config KVM_GUEST 25 bool "KVM Guest support" 26 select EPAPR_PARAVIRT 27 help 28 This option enables various optimizations for running under the KVM 29 hypervisor. Overhead for the kernel when not running inside KVM should 30 be minimal. 31 32 In case of doubt, say Y 33 34config EPAPR_PARAVIRT 35 bool "ePAPR para-virtualization support" 36 help 37 Enables ePAPR para-virtualization support for guests. 38 39 In case of doubt, say Y 40 41config PPC_NATIVE 42 bool 43 depends on PPC_BOOK3S_32 || PPC64 44 help 45 Support for running natively on the hardware, i.e. without 46 a hypervisor. This option is not user-selectable but should 47 be selected by all platforms that need it. 48 49config PPC_OF_BOOT_TRAMPOLINE 50 bool "Support booting from Open Firmware or yaboot" 51 depends on PPC_BOOK3S_32 || PPC64 52 default y 53 help 54 Support from booting from Open Firmware or yaboot using an 55 Open Firmware client interface. This enables the kernel to 56 communicate with open firmware to retrieve system information 57 such as the device tree. 58 59 In case of doubt, say Y 60 61config PPC_DT_CPU_FTRS 62 bool "Device-tree based CPU feature discovery & setup" 63 depends on PPC_BOOK3S_64 64 default y 65 help 66 This enables code to use a new device tree binding for describing CPU 67 compatibility and features. Saying Y here will attempt to use the new 68 binding if the firmware provides it. Currently only the skiboot 69 firmware provides this binding. 70 If you're not sure say Y. 71 72config UDBG_RTAS_CONSOLE 73 bool "RTAS based debug console" 74 depends on PPC_RTAS 75 76config PPC_SMP_MUXED_IPI 77 bool 78 help 79 Select this option if your platform supports SMP and your 80 interrupt controller provides less than 4 interrupts to each 81 cpu. This will enable the generic code to multiplex the 4 82 messages on to one ipi. 83 84config IPIC 85 bool 86 87config MPIC 88 bool 89 90config MPIC_TIMER 91 bool "MPIC Global Timer" 92 depends on MPIC && FSL_SOC 93 help 94 The MPIC global timer is a hardware timer inside the 95 Freescale PIC complying with OpenPIC standard. When the 96 specified interval times out, the hardware timer generates 97 an interrupt. The driver currently is only tested on fsl 98 chip, but it can potentially support other global timers 99 complying with the OpenPIC standard. 100 101config FSL_MPIC_TIMER_WAKEUP 102 tristate "Freescale MPIC global timer wakeup driver" 103 depends on FSL_SOC && MPIC_TIMER && PM 104 help 105 The driver provides a way to wake up the system by MPIC 106 timer. 107 e.g. "echo 5 > /sys/devices/system/mpic/timer_wakeup" 108 109config PPC_EPAPR_HV_PIC 110 bool 111 select EPAPR_PARAVIRT 112 113config MPIC_WEIRD 114 bool 115 116config MPIC_MSGR 117 bool "MPIC message register support" 118 depends on MPIC 119 help 120 Enables support for the MPIC message registers. These 121 registers are used for inter-processor communication. 122 123config PPC_I8259 124 bool 125 126config U3_DART 127 bool 128 depends on PPC64 129 130config PPC_RTAS 131 bool 132 133config RTAS_ERROR_LOGGING 134 bool 135 depends on PPC_RTAS 136 137config PPC_RTAS_DAEMON 138 bool 139 depends on PPC_RTAS 140 141config RTAS_PROC 142 bool "Proc interface to RTAS" 143 depends on PPC_RTAS && PROC_FS 144 default y 145 146config RTAS_FLASH 147 tristate "Firmware flash interface" 148 depends on PPC64 && RTAS_PROC 149 150config MMIO_NVRAM 151 bool 152 153config MPIC_U3_HT_IRQS 154 bool 155 156config MPIC_BROKEN_REGREAD 157 bool 158 depends on MPIC 159 help 160 This option enables a MPIC driver workaround for some chips 161 that have a bug that causes some interrupt source information 162 to not read back properly. It is safe to use on other chips as 163 well, but enabling it uses about 8KB of memory to keep copies 164 of the register contents in software. 165 166config EEH 167 bool 168 depends on (PPC_POWERNV || PPC_PSERIES) && PCI 169 default y 170 171config PPC_MPC106 172 bool 173 174config PPC_970_NAP 175 bool 176 177config PPC_P7_NAP 178 bool 179 180config PPC_BOOK3S_IDLE 181 def_bool y 182 depends on (PPC_970_NAP || PPC_P7_NAP) 183 184config PPC_INDIRECT_PIO 185 bool 186 select GENERIC_IOMAP 187 188config PPC_INDIRECT_MMIO 189 bool 190 191config PPC_IO_WORKAROUNDS 192 bool 193 194source "drivers/cpufreq/Kconfig" 195 196menu "CPUIdle driver" 197 198source "drivers/cpuidle/Kconfig" 199 200endmenu 201 202config PPC601_SYNC_FIX 203 bool "Workarounds for PPC601 bugs" 204 depends on PPC_BOOK3S_601 && PPC_PMAC 205 default y 206 help 207 Some versions of the PPC601 (the first PowerPC chip) have bugs which 208 mean that extra synchronization instructions are required near 209 certain instructions, typically those that make major changes to the 210 CPU state. These extra instructions reduce performance slightly. 211 If you say N here, these extra instructions will not be included, 212 resulting in a kernel which will run faster but may not run at all 213 on some systems with the PPC601 chip. 214 215 If in doubt, say Y here. 216 217config TAU 218 bool "On-chip CPU temperature sensor support" 219 depends on PPC_BOOK3S_32 220 help 221 G3 and G4 processors have an on-chip temperature sensor called the 222 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die 223 temperature within 2-4 degrees Celsius. This option shows the current 224 on-die temperature in /proc/cpuinfo if the cpu supports it. 225 226 Unfortunately, on some chip revisions, this sensor is very inaccurate 227 and in many cases, does not work at all, so don't assume the cpu 228 temp is actually what /proc/cpuinfo says it is. 229 230config TAU_INT 231 bool "Interrupt driven TAU driver (DANGEROUS)" 232 depends on TAU 233 help 234 The TAU supports an interrupt driven mode which causes an interrupt 235 whenever the temperature goes out of range. This is the fastest way 236 to get notified the temp has exceeded a range. With this option off, 237 a timer is used to re-check the temperature periodically. 238 239 However, on some cpus it appears that the TAU interrupt hardware 240 is buggy and can cause a situation which would lead unexplained hard 241 lockups. 242 243 Unless you are extending the TAU driver, or enjoy kernel/hardware 244 debugging, leave this option off. 245 246config TAU_AVERAGE 247 bool "Average high and low temp" 248 depends on TAU 249 help 250 The TAU hardware can compare the temperature to an upper and lower 251 bound. The default behavior is to show both the upper and lower 252 bound in /proc/cpuinfo. If the range is large, the temperature is 253 either changing a lot, or the TAU hardware is broken (likely on some 254 G4's). If the range is small (around 4 degrees), the temperature is 255 relatively stable. If you say Y here, a single temperature value, 256 halfway between the upper and lower bounds, will be reported in 257 /proc/cpuinfo. 258 259 If in doubt, say N here. 260 261config QE_GPIO 262 bool "QE GPIO support" 263 depends on QUICC_ENGINE 264 select GPIOLIB 265 help 266 Say Y here if you're going to use hardware that connects to the 267 QE GPIOs. 268 269config CPM2 270 bool "Enable support for the CPM2 (Communications Processor Module)" 271 depends on (FSL_SOC_BOOKE && PPC32) || 8260 272 select CPM 273 select HAVE_PCI 274 select GPIOLIB 275 help 276 The CPM2 (Communications Processor Module) is a coprocessor on 277 embedded CPUs made by Freescale. Selecting this option means that 278 you wish to build a kernel for a machine with a CPM2 coprocessor 279 on it (826x, 827x, 8560). 280 281config FSL_ULI1575 282 bool 283 select GENERIC_ISA_DMA 284 help 285 Supports for the ULI1575 PCIe south bridge that exists on some 286 Freescale reference boards. The boards all use the ULI in pretty 287 much the same way. 288 289config CPM 290 bool 291 select GENERIC_ALLOCATOR 292 293config OF_RTC 294 bool 295 help 296 Uses information from the OF or flattened device tree to instantiate 297 platform devices for direct mapped RTC chips like the DS1742 or DS1743. 298 299config GEN_RTC 300 bool "Use the platform RTC operations from user space" 301 select RTC_CLASS 302 select RTC_DRV_GENERIC 303 help 304 This option provides backwards compatibility with the old gen_rtc.ko 305 module that was traditionally used for old PowerPC machines. 306 Platforms should migrate to enabling the RTC_DRV_GENERIC by hand 307 replacing their get_rtc_time/set_rtc_time callbacks with 308 a proper RTC device driver. 309 310config MCU_MPC8349EMITX 311 bool "MPC8349E-mITX MCU driver" 312 depends on I2C=y && PPC_83xx 313 select GPIOLIB 314 help 315 Say Y here to enable soft power-off functionality on the Freescale 316 boards with the MPC8349E-mITX-compatible MCU chips. This driver will 317 also register MCU GPIOs with the generic GPIO API, so you'll able 318 to use MCU pins as GPIOs. 319 320endmenu 321