1menu "Platform support" 2 3source "arch/powerpc/platforms/powernv/Kconfig" 4source "arch/powerpc/platforms/pseries/Kconfig" 5source "arch/powerpc/platforms/chrp/Kconfig" 6source "arch/powerpc/platforms/512x/Kconfig" 7source "arch/powerpc/platforms/52xx/Kconfig" 8source "arch/powerpc/platforms/powermac/Kconfig" 9source "arch/powerpc/platforms/prep/Kconfig" 10source "arch/powerpc/platforms/maple/Kconfig" 11source "arch/powerpc/platforms/pasemi/Kconfig" 12source "arch/powerpc/platforms/ps3/Kconfig" 13source "arch/powerpc/platforms/cell/Kconfig" 14source "arch/powerpc/platforms/8xx/Kconfig" 15source "arch/powerpc/platforms/82xx/Kconfig" 16source "arch/powerpc/platforms/83xx/Kconfig" 17source "arch/powerpc/platforms/85xx/Kconfig" 18source "arch/powerpc/platforms/86xx/Kconfig" 19source "arch/powerpc/platforms/embedded6xx/Kconfig" 20source "arch/powerpc/platforms/44x/Kconfig" 21source "arch/powerpc/platforms/40x/Kconfig" 22source "arch/powerpc/platforms/amigaone/Kconfig" 23source "arch/powerpc/platforms/wsp/Kconfig" 24 25config KVM_GUEST 26 bool "KVM Guest support" 27 default n 28 select EPAPR_PARAVIRT 29 ---help--- 30 This option enables various optimizations for running under the KVM 31 hypervisor. Overhead for the kernel when not running inside KVM should 32 be minimal. 33 34 In case of doubt, say Y 35 36config EPAPR_PARAVIRT 37 bool "ePAPR para-virtualization support" 38 default n 39 help 40 Enables ePAPR para-virtualization support for guests. 41 42 In case of doubt, say Y 43 44config PPC_NATIVE 45 bool 46 depends on 6xx || PPC64 47 help 48 Support for running natively on the hardware, i.e. without 49 a hypervisor. This option is not user-selectable but should 50 be selected by all platforms that need it. 51 52config PPC_OF_BOOT_TRAMPOLINE 53 bool "Support booting from Open Firmware or yaboot" 54 depends on 6xx || PPC64 55 default y 56 help 57 Support from booting from Open Firmware or yaboot using an 58 Open Firmware client interface. This enables the kernel to 59 communicate with open firmware to retrieve system information 60 such as the device tree. 61 62 In case of doubt, say Y 63 64config UDBG_RTAS_CONSOLE 65 bool "RTAS based debug console" 66 depends on PPC_RTAS 67 default n 68 69config PPC_SMP_MUXED_IPI 70 bool 71 help 72 Select this opton if your platform supports SMP and your 73 interrupt controller provides less than 4 interrupts to each 74 cpu. This will enable the generic code to multiplex the 4 75 messages on to one ipi. 76 77config PPC_UDBG_BEAT 78 bool "BEAT based debug console" 79 depends on PPC_CELLEB 80 default n 81 82config IPIC 83 bool 84 default n 85 86config MPIC 87 bool 88 default n 89 90config PPC_EPAPR_HV_PIC 91 bool 92 default n 93 94config MPIC_WEIRD 95 bool 96 default n 97 98config MPIC_MSGR 99 bool "MPIC message register support" 100 depends on MPIC 101 default n 102 help 103 Enables support for the MPIC message registers. These 104 registers are used for inter-processor communication. 105 106config PPC_I8259 107 bool 108 default n 109 110config U3_DART 111 bool 112 depends on PPC64 113 default n 114 115config PPC_RTAS 116 bool 117 default n 118 119config RTAS_ERROR_LOGGING 120 bool 121 depends on PPC_RTAS 122 default n 123 124config PPC_RTAS_DAEMON 125 bool 126 depends on PPC_RTAS 127 default n 128 129config RTAS_PROC 130 bool "Proc interface to RTAS" 131 depends on PPC_RTAS 132 default y 133 134config RTAS_FLASH 135 tristate "Firmware flash interface" 136 depends on PPC64 && RTAS_PROC 137 138config MMIO_NVRAM 139 bool 140 default n 141 142config MPIC_U3_HT_IRQS 143 bool 144 default n 145 146config MPIC_BROKEN_REGREAD 147 bool 148 depends on MPIC 149 help 150 This option enables a MPIC driver workaround for some chips 151 that have a bug that causes some interrupt source information 152 to not read back properly. It is safe to use on other chips as 153 well, but enabling it uses about 8KB of memory to keep copies 154 of the register contents in software. 155 156config IBMVIO 157 depends on PPC_PSERIES 158 bool 159 default y 160 161config IBMEBUS 162 depends on PPC_PSERIES 163 bool "Support for GX bus based adapters" 164 help 165 Bus device driver for GX bus based adapters. 166 167config PPC_MPC106 168 bool 169 default n 170 171config PPC_970_NAP 172 bool 173 default n 174 175config PPC_P7_NAP 176 bool 177 default n 178 179config PPC_INDIRECT_IO 180 bool 181 select GENERIC_IOMAP 182 183config PPC_INDIRECT_PIO 184 bool 185 select PPC_INDIRECT_IO 186 187config PPC_INDIRECT_MMIO 188 bool 189 select PPC_INDIRECT_IO 190 191config PPC_IO_WORKAROUNDS 192 bool 193 194source "drivers/cpufreq/Kconfig" 195 196menu "CPU Frequency drivers" 197 depends on CPU_FREQ 198 199config CPU_FREQ_PMAC 200 bool "Support for Apple PowerBooks" 201 depends on ADB_PMU && PPC32 202 select CPU_FREQ_TABLE 203 help 204 This adds support for frequency switching on Apple PowerBooks, 205 this currently includes some models of iBook & Titanium 206 PowerBook. 207 208config CPU_FREQ_PMAC64 209 bool "Support for some Apple G5s" 210 depends on PPC_PMAC && PPC64 211 select CPU_FREQ_TABLE 212 help 213 This adds support for frequency switching on Apple iMac G5, 214 and some of the more recent desktop G5 machines as well. 215 216config PPC_PASEMI_CPUFREQ 217 bool "Support for PA Semi PWRficient" 218 depends on PPC_PASEMI 219 default y 220 select CPU_FREQ_TABLE 221 help 222 This adds the support for frequency switching on PA Semi 223 PWRficient processors. 224 225endmenu 226 227menu "CPUIdle driver" 228 229source "drivers/cpuidle/Kconfig" 230 231endmenu 232 233config PPC601_SYNC_FIX 234 bool "Workarounds for PPC601 bugs" 235 depends on 6xx && (PPC_PREP || PPC_PMAC) 236 help 237 Some versions of the PPC601 (the first PowerPC chip) have bugs which 238 mean that extra synchronization instructions are required near 239 certain instructions, typically those that make major changes to the 240 CPU state. These extra instructions reduce performance slightly. 241 If you say N here, these extra instructions will not be included, 242 resulting in a kernel which will run faster but may not run at all 243 on some systems with the PPC601 chip. 244 245 If in doubt, say Y here. 246 247config TAU 248 bool "On-chip CPU temperature sensor support" 249 depends on 6xx 250 help 251 G3 and G4 processors have an on-chip temperature sensor called the 252 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die 253 temperature within 2-4 degrees Celsius. This option shows the current 254 on-die temperature in /proc/cpuinfo if the cpu supports it. 255 256 Unfortunately, on some chip revisions, this sensor is very inaccurate 257 and in many cases, does not work at all, so don't assume the cpu 258 temp is actually what /proc/cpuinfo says it is. 259 260config TAU_INT 261 bool "Interrupt driven TAU driver (DANGEROUS)" 262 depends on TAU 263 ---help--- 264 The TAU supports an interrupt driven mode which causes an interrupt 265 whenever the temperature goes out of range. This is the fastest way 266 to get notified the temp has exceeded a range. With this option off, 267 a timer is used to re-check the temperature periodically. 268 269 However, on some cpus it appears that the TAU interrupt hardware 270 is buggy and can cause a situation which would lead unexplained hard 271 lockups. 272 273 Unless you are extending the TAU driver, or enjoy kernel/hardware 274 debugging, leave this option off. 275 276config TAU_AVERAGE 277 bool "Average high and low temp" 278 depends on TAU 279 ---help--- 280 The TAU hardware can compare the temperature to an upper and lower 281 bound. The default behavior is to show both the upper and lower 282 bound in /proc/cpuinfo. If the range is large, the temperature is 283 either changing a lot, or the TAU hardware is broken (likely on some 284 G4's). If the range is small (around 4 degrees), the temperature is 285 relatively stable. If you say Y here, a single temperature value, 286 halfway between the upper and lower bounds, will be reported in 287 /proc/cpuinfo. 288 289 If in doubt, say N here. 290 291config QUICC_ENGINE 292 bool "Freescale QUICC Engine (QE) Support" 293 depends on FSL_SOC && PPC32 294 select PPC_LIB_RHEAP 295 select CRC32 296 help 297 The QUICC Engine (QE) is a new generation of communications 298 coprocessors on Freescale embedded CPUs (akin to CPM in older chips). 299 Selecting this option means that you wish to build a kernel 300 for a machine with a QE coprocessor. 301 302config QE_GPIO 303 bool "QE GPIO support" 304 depends on QUICC_ENGINE 305 select GENERIC_GPIO 306 select ARCH_REQUIRE_GPIOLIB 307 help 308 Say Y here if you're going to use hardware that connects to the 309 QE GPIOs. 310 311config CPM2 312 bool "Enable support for the CPM2 (Communications Processor Module)" 313 depends on (FSL_SOC_BOOKE && PPC32) || 8260 314 select CPM 315 select PPC_LIB_RHEAP 316 select PPC_PCI_CHOICE 317 select ARCH_REQUIRE_GPIOLIB 318 select GENERIC_GPIO 319 help 320 The CPM2 (Communications Processor Module) is a coprocessor on 321 embedded CPUs made by Freescale. Selecting this option means that 322 you wish to build a kernel for a machine with a CPM2 coprocessor 323 on it (826x, 827x, 8560). 324 325config AXON_RAM 326 tristate "Axon DDR2 memory device driver" 327 depends on PPC_IBM_CELL_BLADE && BLOCK 328 default m 329 help 330 It registers one block device per Axon's DDR2 memory bank found 331 on a system. Block devices are called axonram?, their major and 332 minor numbers are available in /proc/devices, /proc/partitions or 333 in /sys/block/axonram?/dev. 334 335config FSL_ULI1575 336 bool 337 default n 338 select GENERIC_ISA_DMA 339 help 340 Supports for the ULI1575 PCIe south bridge that exists on some 341 Freescale reference boards. The boards all use the ULI in pretty 342 much the same way. 343 344config CPM 345 bool 346 select PPC_CLOCK 347 348config OF_RTC 349 bool 350 help 351 Uses information from the OF or flattened device tree to instantiate 352 platform devices for direct mapped RTC chips like the DS1742 or DS1743. 353 354source "arch/powerpc/sysdev/bestcomm/Kconfig" 355 356config SIMPLE_GPIO 357 bool "Support for simple, memory-mapped GPIO controllers" 358 depends on PPC 359 select GENERIC_GPIO 360 select ARCH_REQUIRE_GPIOLIB 361 help 362 Say Y here to support simple, memory-mapped GPIO controllers. 363 These are usually BCSRs used to control board's switches, LEDs, 364 chip-selects, Ethernet/USB PHY's power and various other small 365 on-board peripherals. 366 367config MCU_MPC8349EMITX 368 bool "MPC8349E-mITX MCU driver" 369 depends on I2C=y && PPC_83xx 370 select GENERIC_GPIO 371 select ARCH_REQUIRE_GPIOLIB 372 help 373 Say Y here to enable soft power-off functionality on the Freescale 374 boards with the MPC8349E-mITX-compatible MCU chips. This driver will 375 also register MCU GPIOs with the generic GPIO API, so you'll able 376 to use MCU pins as GPIOs. 377 378config XILINX_PCI 379 bool "Xilinx PCI host bridge support" 380 depends on PCI && XILINX_VIRTEX 381 382endmenu 383