1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 1995 Linus Torvalds 4 * Adapted from 'alpha' version by Gary Thomas 5 * Modified by Cort Dougan (cort@cs.nmt.edu) 6 * Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net) 7 * Further modified for generic 8xx by Dan. 8 */ 9 10 /* 11 * bootup setup stuff.. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/interrupt.h> 16 #include <linux/init.h> 17 #include <linux/time.h> 18 #include <linux/rtc.h> 19 #include <linux/fsl_devices.h> 20 21 #include <asm/io.h> 22 #include <asm/8xx_immap.h> 23 #include <asm/prom.h> 24 #include <asm/fs_pd.h> 25 #include <mm/mmu_decl.h> 26 27 #include "pic.h" 28 29 #include "mpc8xx.h" 30 31 extern int cpm_pic_init(void); 32 extern int cpm_get_irq(void); 33 34 /* A place holder for time base interrupts, if they are ever enabled. */ 35 static irqreturn_t timebase_interrupt(int irq, void *dev) 36 { 37 printk ("timebase_interrupt()\n"); 38 39 return IRQ_HANDLED; 40 } 41 42 /* per-board overridable init_internal_rtc() function. */ 43 void __init __attribute__ ((weak)) 44 init_internal_rtc(void) 45 { 46 sit8xx_t __iomem *sys_tmr = immr_map(im_sit); 47 48 /* Disable the RTC one second and alarm interrupts. */ 49 clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE)); 50 51 /* Enable the RTC */ 52 setbits16(&sys_tmr->sit_rtcsc, (RTCSC_RTF | RTCSC_RTE)); 53 immr_unmap(sys_tmr); 54 } 55 56 static int __init get_freq(char *name, unsigned long *val) 57 { 58 struct device_node *cpu; 59 const unsigned int *fp; 60 int found = 0; 61 62 /* The cpu node should have timebase and clock frequency properties */ 63 cpu = of_get_cpu_node(0, NULL); 64 65 if (cpu) { 66 fp = of_get_property(cpu, name, NULL); 67 if (fp) { 68 found = 1; 69 *val = *fp; 70 } 71 72 of_node_put(cpu); 73 } 74 75 return found; 76 } 77 78 /* The decrementer counts at the system (internal) clock frequency divided by 79 * sixteen, or external oscillator divided by four. We force the processor 80 * to use system clock divided by sixteen. 81 */ 82 void __init mpc8xx_calibrate_decr(void) 83 { 84 struct device_node *cpu; 85 cark8xx_t __iomem *clk_r1; 86 car8xx_t __iomem *clk_r2; 87 sitk8xx_t __iomem *sys_tmr1; 88 sit8xx_t __iomem *sys_tmr2; 89 int irq, virq; 90 91 clk_r1 = immr_map(im_clkrstk); 92 93 /* Unlock the SCCR. */ 94 out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY); 95 out_be32(&clk_r1->cark_sccrk, KAPWR_KEY); 96 immr_unmap(clk_r1); 97 98 /* Force all 8xx processors to use divide by 16 processor clock. */ 99 clk_r2 = immr_map(im_clkrst); 100 setbits32(&clk_r2->car_sccr, 0x02000000); 101 immr_unmap(clk_r2); 102 103 /* Processor frequency is MHz. 104 */ 105 ppc_proc_freq = 50000000; 106 if (!get_freq("clock-frequency", &ppc_proc_freq)) 107 printk(KERN_ERR "WARNING: Estimating processor frequency " 108 "(not found)\n"); 109 110 ppc_tb_freq = ppc_proc_freq / 16; 111 printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq); 112 113 /* Perform some more timer/timebase initialization. This used 114 * to be done elsewhere, but other changes caused it to get 115 * called more than once....that is a bad thing. 116 * 117 * First, unlock all of the registers we are going to modify. 118 * To protect them from corruption during power down, registers 119 * that are maintained by keep alive power are "locked". To 120 * modify these registers we have to write the key value to 121 * the key location associated with the register. 122 * Some boards power up with these unlocked, while others 123 * are locked. Writing anything (including the unlock code?) 124 * to the unlocked registers will lock them again. So, here 125 * we guarantee the registers are locked, then we unlock them 126 * for our use. 127 */ 128 sys_tmr1 = immr_map(im_sitk); 129 out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY); 130 out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY); 131 out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY); 132 out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY); 133 out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY); 134 out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY); 135 immr_unmap(sys_tmr1); 136 137 init_internal_rtc(); 138 139 /* Enabling the decrementer also enables the timebase interrupts 140 * (or from the other point of view, to get decrementer interrupts 141 * we have to enable the timebase). The decrementer interrupt 142 * is wired into the vector table, nothing to do here for that. 143 */ 144 cpu = of_get_cpu_node(0, NULL); 145 virq= irq_of_parse_and_map(cpu, 0); 146 of_node_put(cpu); 147 irq = virq_to_hw(virq); 148 149 sys_tmr2 = immr_map(im_sit); 150 out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) | 151 (TBSCR_TBF | TBSCR_TBE)); 152 immr_unmap(sys_tmr2); 153 154 if (request_irq(virq, timebase_interrupt, IRQF_NO_THREAD, "tbint", 155 NULL)) 156 panic("Could not allocate timer IRQ!"); 157 } 158 159 /* The RTC on the MPC8xx is an internal register. 160 * We want to protect this during power down, so we need to unlock, 161 * modify, and re-lock. 162 */ 163 164 int mpc8xx_set_rtc_time(struct rtc_time *tm) 165 { 166 sitk8xx_t __iomem *sys_tmr1; 167 sit8xx_t __iomem *sys_tmr2; 168 time64_t time; 169 170 sys_tmr1 = immr_map(im_sitk); 171 sys_tmr2 = immr_map(im_sit); 172 time = rtc_tm_to_time64(tm); 173 174 out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY); 175 out_be32(&sys_tmr2->sit_rtc, (u32)time); 176 out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY); 177 178 immr_unmap(sys_tmr2); 179 immr_unmap(sys_tmr1); 180 return 0; 181 } 182 183 void mpc8xx_get_rtc_time(struct rtc_time *tm) 184 { 185 unsigned long data; 186 sit8xx_t __iomem *sys_tmr = immr_map(im_sit); 187 188 /* Get time from the RTC. */ 189 data = in_be32(&sys_tmr->sit_rtc); 190 rtc_time64_to_tm(data, tm); 191 immr_unmap(sys_tmr); 192 return; 193 } 194 195 void __noreturn mpc8xx_restart(char *cmd) 196 { 197 car8xx_t __iomem *clk_r = immr_map(im_clkrst); 198 199 200 local_irq_disable(); 201 202 setbits32(&clk_r->car_plprcr, 0x00000080); 203 /* Clear the ME bit in MSR to cause checkstop on machine check 204 */ 205 mtmsr(mfmsr() & ~0x1000); 206 207 in_8(&clk_r->res[0]); 208 panic("Restart failed\n"); 209 } 210 211 static void cpm_cascade(struct irq_desc *desc) 212 { 213 generic_handle_irq(cpm_get_irq()); 214 } 215 216 /* Initialize the internal interrupt controllers. The number of 217 * interrupts supported can vary with the processor type, and the 218 * 82xx family can have up to 64. 219 * External interrupts can be either edge or level triggered, and 220 * need to be initialized by the appropriate driver. 221 */ 222 void __init mpc8xx_pics_init(void) 223 { 224 int irq; 225 226 if (mpc8xx_pic_init()) { 227 printk(KERN_ERR "Failed interrupt 8xx controller initialization\n"); 228 return; 229 } 230 231 irq = cpm_pic_init(); 232 if (irq) 233 irq_set_chained_handler(irq, cpm_cascade); 234 } 235