1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * General Purpose functions for the global management of the 4 * Communication Processor Module. 5 * Copyright (c) 1997 Dan error_act (dmalek@jlc.net) 6 * 7 * In addition to the individual control of the communication 8 * channels, there are a few functions that globally affect the 9 * communication processor. 10 * 11 * Buffer descriptors must be allocated from the dual ported memory 12 * space. The allocator for that is here. When the communication 13 * process is reset, we reclaim the memory available. There is 14 * currently no deallocator for this memory. 15 * The amount of space available is platform dependent. On the 16 * MBX, the EPPC software loads additional microcode into the 17 * communication processor, and uses some of the DP ram for this 18 * purpose. Current, the first 512 bytes and the last 256 bytes of 19 * memory are used. Right now I am conservative and only use the 20 * memory that can never be used for microcode. If there are 21 * applications that require more DP ram, we can expand the boundaries 22 * but then we have to be careful of any downloaded microcode. 23 */ 24 #include <linux/errno.h> 25 #include <linux/sched.h> 26 #include <linux/kernel.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/param.h> 29 #include <linux/string.h> 30 #include <linux/mm.h> 31 #include <linux/interrupt.h> 32 #include <linux/irq.h> 33 #include <linux/module.h> 34 #include <linux/spinlock.h> 35 #include <linux/slab.h> 36 #include <asm/page.h> 37 #include <asm/8xx_immap.h> 38 #include <asm/cpm1.h> 39 #include <asm/io.h> 40 #include <asm/rheap.h> 41 #include <asm/prom.h> 42 #include <asm/cpm.h> 43 44 #include <asm/fs_pd.h> 45 46 #ifdef CONFIG_8xx_GPIO 47 #include <linux/of_gpio.h> 48 #endif 49 50 #define CPM_MAP_SIZE (0x4000) 51 52 cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */ 53 immap_t __iomem *mpc8xx_immr = (void __iomem *)VIRT_IMMR_BASE; 54 static cpic8xx_t __iomem *cpic_reg; 55 56 static struct irq_domain *cpm_pic_host; 57 58 static void cpm_mask_irq(struct irq_data *d) 59 { 60 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); 61 62 clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); 63 } 64 65 static void cpm_unmask_irq(struct irq_data *d) 66 { 67 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); 68 69 setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); 70 } 71 72 static void cpm_end_irq(struct irq_data *d) 73 { 74 unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d); 75 76 out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec)); 77 } 78 79 static struct irq_chip cpm_pic = { 80 .name = "CPM PIC", 81 .irq_mask = cpm_mask_irq, 82 .irq_unmask = cpm_unmask_irq, 83 .irq_eoi = cpm_end_irq, 84 }; 85 86 int cpm_get_irq(void) 87 { 88 int cpm_vec; 89 90 /* 91 * Get the vector by setting the ACK bit and then reading 92 * the register. 93 */ 94 out_be16(&cpic_reg->cpic_civr, 1); 95 cpm_vec = in_be16(&cpic_reg->cpic_civr); 96 cpm_vec >>= 11; 97 98 return irq_linear_revmap(cpm_pic_host, cpm_vec); 99 } 100 101 static int cpm_pic_host_map(struct irq_domain *h, unsigned int virq, 102 irq_hw_number_t hw) 103 { 104 pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw); 105 106 irq_set_status_flags(virq, IRQ_LEVEL); 107 irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq); 108 return 0; 109 } 110 111 /* 112 * The CPM can generate the error interrupt when there is a race condition 113 * between generating and masking interrupts. All we have to do is ACK it 114 * and return. This is a no-op function so we don't need any special 115 * tests in the interrupt handler. 116 */ 117 static irqreturn_t cpm_error_interrupt(int irq, void *dev) 118 { 119 return IRQ_HANDLED; 120 } 121 122 static const struct irq_domain_ops cpm_pic_host_ops = { 123 .map = cpm_pic_host_map, 124 }; 125 126 unsigned int __init cpm_pic_init(void) 127 { 128 struct device_node *np = NULL; 129 struct resource res; 130 unsigned int sirq = 0, hwirq, eirq; 131 int ret; 132 133 pr_debug("cpm_pic_init\n"); 134 135 np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic"); 136 if (np == NULL) 137 np = of_find_compatible_node(NULL, "cpm-pic", "CPM"); 138 if (np == NULL) { 139 printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n"); 140 return sirq; 141 } 142 143 ret = of_address_to_resource(np, 0, &res); 144 if (ret) 145 goto end; 146 147 cpic_reg = ioremap(res.start, resource_size(&res)); 148 if (cpic_reg == NULL) 149 goto end; 150 151 sirq = irq_of_parse_and_map(np, 0); 152 if (!sirq) 153 goto end; 154 155 /* Initialize the CPM interrupt controller. */ 156 hwirq = (unsigned int)virq_to_hw(sirq); 157 out_be32(&cpic_reg->cpic_cicr, 158 (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | 159 ((hwirq/2) << 13) | CICR_HP_MASK); 160 161 out_be32(&cpic_reg->cpic_cimr, 0); 162 163 cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL); 164 if (cpm_pic_host == NULL) { 165 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n"); 166 sirq = 0; 167 goto end; 168 } 169 170 /* Install our own error handler. */ 171 np = of_find_compatible_node(NULL, NULL, "fsl,cpm1"); 172 if (np == NULL) 173 np = of_find_node_by_type(NULL, "cpm"); 174 if (np == NULL) { 175 printk(KERN_ERR "CPM PIC init: can not find cpm node\n"); 176 goto end; 177 } 178 179 eirq = irq_of_parse_and_map(np, 0); 180 if (!eirq) 181 goto end; 182 183 if (request_irq(eirq, cpm_error_interrupt, IRQF_NO_THREAD, "error", 184 NULL)) 185 printk(KERN_ERR "Could not allocate CPM error IRQ!"); 186 187 setbits32(&cpic_reg->cpic_cicr, CICR_IEN); 188 189 end: 190 of_node_put(np); 191 return sirq; 192 } 193 194 void __init cpm_reset(void) 195 { 196 sysconf8xx_t __iomem *siu_conf; 197 198 cpmp = &mpc8xx_immr->im_cpm; 199 200 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM 201 /* Perform a reset. */ 202 out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG); 203 204 /* Wait for it. */ 205 while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG); 206 #endif 207 208 #ifdef CONFIG_UCODE_PATCH 209 cpm_load_patch(cpmp); 210 #endif 211 212 /* 213 * Set SDMA Bus Request priority 5. 214 * On 860T, this also enables FEC priority 6. I am not sure 215 * this is what we really want for some applications, but the 216 * manual recommends it. 217 * Bit 25, FAM can also be set to use FEC aggressive mode (860T). 218 */ 219 siu_conf = immr_map(im_siu_conf); 220 if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */ 221 out_be32(&siu_conf->sc_sdcr, 0x40); 222 else 223 out_be32(&siu_conf->sc_sdcr, 1); 224 immr_unmap(siu_conf); 225 } 226 227 static DEFINE_SPINLOCK(cmd_lock); 228 229 #define MAX_CR_CMD_LOOPS 10000 230 231 int cpm_command(u32 command, u8 opcode) 232 { 233 int i, ret; 234 unsigned long flags; 235 236 if (command & 0xffffff0f) 237 return -EINVAL; 238 239 spin_lock_irqsave(&cmd_lock, flags); 240 241 ret = 0; 242 out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8)); 243 for (i = 0; i < MAX_CR_CMD_LOOPS; i++) 244 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0) 245 goto out; 246 247 printk(KERN_ERR "%s(): Not able to issue CPM command\n", __func__); 248 ret = -EIO; 249 out: 250 spin_unlock_irqrestore(&cmd_lock, flags); 251 return ret; 252 } 253 EXPORT_SYMBOL(cpm_command); 254 255 /* 256 * Set a baud rate generator. This needs lots of work. There are 257 * four BRGs, any of which can be wired to any channel. 258 * The internal baud rate clock is the system clock divided by 16. 259 * This assumes the baudrate is 16x oversampled by the uart. 260 */ 261 #define BRG_INT_CLK (get_brgfreq()) 262 #define BRG_UART_CLK (BRG_INT_CLK/16) 263 #define BRG_UART_CLK_DIV16 (BRG_UART_CLK/16) 264 265 void 266 cpm_setbrg(uint brg, uint rate) 267 { 268 u32 __iomem *bp; 269 270 /* This is good enough to get SMCs running..... */ 271 bp = &cpmp->cp_brgc1; 272 bp += brg; 273 /* 274 * The BRG has a 12-bit counter. For really slow baud rates (or 275 * really fast processors), we may have to further divide by 16. 276 */ 277 if (((BRG_UART_CLK / rate) - 1) < 4096) 278 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN); 279 else 280 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) | 281 CPM_BRG_EN | CPM_BRG_DIV16); 282 } 283 284 struct cpm_ioport16 { 285 __be16 dir, par, odr_sor, dat, intr; 286 __be16 res[3]; 287 }; 288 289 struct cpm_ioport32b { 290 __be32 dir, par, odr, dat; 291 }; 292 293 struct cpm_ioport32e { 294 __be32 dir, par, sor, odr, dat; 295 }; 296 297 static void __init cpm1_set_pin32(int port, int pin, int flags) 298 { 299 struct cpm_ioport32e __iomem *iop; 300 pin = 1 << (31 - pin); 301 302 if (port == CPM_PORTB) 303 iop = (struct cpm_ioport32e __iomem *) 304 &mpc8xx_immr->im_cpm.cp_pbdir; 305 else 306 iop = (struct cpm_ioport32e __iomem *) 307 &mpc8xx_immr->im_cpm.cp_pedir; 308 309 if (flags & CPM_PIN_OUTPUT) 310 setbits32(&iop->dir, pin); 311 else 312 clrbits32(&iop->dir, pin); 313 314 if (!(flags & CPM_PIN_GPIO)) 315 setbits32(&iop->par, pin); 316 else 317 clrbits32(&iop->par, pin); 318 319 if (port == CPM_PORTB) { 320 if (flags & CPM_PIN_OPENDRAIN) 321 setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); 322 else 323 clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin); 324 } 325 326 if (port == CPM_PORTE) { 327 if (flags & CPM_PIN_SECONDARY) 328 setbits32(&iop->sor, pin); 329 else 330 clrbits32(&iop->sor, pin); 331 332 if (flags & CPM_PIN_OPENDRAIN) 333 setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); 334 else 335 clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin); 336 } 337 } 338 339 static void __init cpm1_set_pin16(int port, int pin, int flags) 340 { 341 struct cpm_ioport16 __iomem *iop = 342 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport; 343 344 pin = 1 << (15 - pin); 345 346 if (port != 0) 347 iop += port - 1; 348 349 if (flags & CPM_PIN_OUTPUT) 350 setbits16(&iop->dir, pin); 351 else 352 clrbits16(&iop->dir, pin); 353 354 if (!(flags & CPM_PIN_GPIO)) 355 setbits16(&iop->par, pin); 356 else 357 clrbits16(&iop->par, pin); 358 359 if (port == CPM_PORTA) { 360 if (flags & CPM_PIN_OPENDRAIN) 361 setbits16(&iop->odr_sor, pin); 362 else 363 clrbits16(&iop->odr_sor, pin); 364 } 365 if (port == CPM_PORTC) { 366 if (flags & CPM_PIN_SECONDARY) 367 setbits16(&iop->odr_sor, pin); 368 else 369 clrbits16(&iop->odr_sor, pin); 370 if (flags & CPM_PIN_FALLEDGE) 371 setbits16(&iop->intr, pin); 372 else 373 clrbits16(&iop->intr, pin); 374 } 375 } 376 377 void __init cpm1_set_pin(enum cpm_port port, int pin, int flags) 378 { 379 if (port == CPM_PORTB || port == CPM_PORTE) 380 cpm1_set_pin32(port, pin, flags); 381 else 382 cpm1_set_pin16(port, pin, flags); 383 } 384 385 int __init cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode) 386 { 387 int shift; 388 int i, bits = 0; 389 u32 __iomem *reg; 390 u32 mask = 7; 391 392 u8 clk_map[][3] = { 393 {CPM_CLK_SCC1, CPM_BRG1, 0}, 394 {CPM_CLK_SCC1, CPM_BRG2, 1}, 395 {CPM_CLK_SCC1, CPM_BRG3, 2}, 396 {CPM_CLK_SCC1, CPM_BRG4, 3}, 397 {CPM_CLK_SCC1, CPM_CLK1, 4}, 398 {CPM_CLK_SCC1, CPM_CLK2, 5}, 399 {CPM_CLK_SCC1, CPM_CLK3, 6}, 400 {CPM_CLK_SCC1, CPM_CLK4, 7}, 401 402 {CPM_CLK_SCC2, CPM_BRG1, 0}, 403 {CPM_CLK_SCC2, CPM_BRG2, 1}, 404 {CPM_CLK_SCC2, CPM_BRG3, 2}, 405 {CPM_CLK_SCC2, CPM_BRG4, 3}, 406 {CPM_CLK_SCC2, CPM_CLK1, 4}, 407 {CPM_CLK_SCC2, CPM_CLK2, 5}, 408 {CPM_CLK_SCC2, CPM_CLK3, 6}, 409 {CPM_CLK_SCC2, CPM_CLK4, 7}, 410 411 {CPM_CLK_SCC3, CPM_BRG1, 0}, 412 {CPM_CLK_SCC3, CPM_BRG2, 1}, 413 {CPM_CLK_SCC3, CPM_BRG3, 2}, 414 {CPM_CLK_SCC3, CPM_BRG4, 3}, 415 {CPM_CLK_SCC3, CPM_CLK5, 4}, 416 {CPM_CLK_SCC3, CPM_CLK6, 5}, 417 {CPM_CLK_SCC3, CPM_CLK7, 6}, 418 {CPM_CLK_SCC3, CPM_CLK8, 7}, 419 420 {CPM_CLK_SCC4, CPM_BRG1, 0}, 421 {CPM_CLK_SCC4, CPM_BRG2, 1}, 422 {CPM_CLK_SCC4, CPM_BRG3, 2}, 423 {CPM_CLK_SCC4, CPM_BRG4, 3}, 424 {CPM_CLK_SCC4, CPM_CLK5, 4}, 425 {CPM_CLK_SCC4, CPM_CLK6, 5}, 426 {CPM_CLK_SCC4, CPM_CLK7, 6}, 427 {CPM_CLK_SCC4, CPM_CLK8, 7}, 428 429 {CPM_CLK_SMC1, CPM_BRG1, 0}, 430 {CPM_CLK_SMC1, CPM_BRG2, 1}, 431 {CPM_CLK_SMC1, CPM_BRG3, 2}, 432 {CPM_CLK_SMC1, CPM_BRG4, 3}, 433 {CPM_CLK_SMC1, CPM_CLK1, 4}, 434 {CPM_CLK_SMC1, CPM_CLK2, 5}, 435 {CPM_CLK_SMC1, CPM_CLK3, 6}, 436 {CPM_CLK_SMC1, CPM_CLK4, 7}, 437 438 {CPM_CLK_SMC2, CPM_BRG1, 0}, 439 {CPM_CLK_SMC2, CPM_BRG2, 1}, 440 {CPM_CLK_SMC2, CPM_BRG3, 2}, 441 {CPM_CLK_SMC2, CPM_BRG4, 3}, 442 {CPM_CLK_SMC2, CPM_CLK5, 4}, 443 {CPM_CLK_SMC2, CPM_CLK6, 5}, 444 {CPM_CLK_SMC2, CPM_CLK7, 6}, 445 {CPM_CLK_SMC2, CPM_CLK8, 7}, 446 }; 447 448 switch (target) { 449 case CPM_CLK_SCC1: 450 reg = &mpc8xx_immr->im_cpm.cp_sicr; 451 shift = 0; 452 break; 453 454 case CPM_CLK_SCC2: 455 reg = &mpc8xx_immr->im_cpm.cp_sicr; 456 shift = 8; 457 break; 458 459 case CPM_CLK_SCC3: 460 reg = &mpc8xx_immr->im_cpm.cp_sicr; 461 shift = 16; 462 break; 463 464 case CPM_CLK_SCC4: 465 reg = &mpc8xx_immr->im_cpm.cp_sicr; 466 shift = 24; 467 break; 468 469 case CPM_CLK_SMC1: 470 reg = &mpc8xx_immr->im_cpm.cp_simode; 471 shift = 12; 472 break; 473 474 case CPM_CLK_SMC2: 475 reg = &mpc8xx_immr->im_cpm.cp_simode; 476 shift = 28; 477 break; 478 479 default: 480 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n"); 481 return -EINVAL; 482 } 483 484 for (i = 0; i < ARRAY_SIZE(clk_map); i++) { 485 if (clk_map[i][0] == target && clk_map[i][1] == clock) { 486 bits = clk_map[i][2]; 487 break; 488 } 489 } 490 491 if (i == ARRAY_SIZE(clk_map)) { 492 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n"); 493 return -EINVAL; 494 } 495 496 bits <<= shift; 497 mask <<= shift; 498 499 if (reg == &mpc8xx_immr->im_cpm.cp_sicr) { 500 if (mode == CPM_CLK_RTX) { 501 bits |= bits << 3; 502 mask |= mask << 3; 503 } else if (mode == CPM_CLK_RX) { 504 bits <<= 3; 505 mask <<= 3; 506 } 507 } 508 509 out_be32(reg, (in_be32(reg) & ~mask) | bits); 510 511 return 0; 512 } 513 514 /* 515 * GPIO LIB API implementation 516 */ 517 #ifdef CONFIG_8xx_GPIO 518 519 struct cpm1_gpio16_chip { 520 struct of_mm_gpio_chip mm_gc; 521 spinlock_t lock; 522 523 /* shadowed data register to clear/set bits safely */ 524 u16 cpdata; 525 526 /* IRQ associated with Pins when relevant */ 527 int irq[16]; 528 }; 529 530 static void cpm1_gpio16_save_regs(struct of_mm_gpio_chip *mm_gc) 531 { 532 struct cpm1_gpio16_chip *cpm1_gc = 533 container_of(mm_gc, struct cpm1_gpio16_chip, mm_gc); 534 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 535 536 cpm1_gc->cpdata = in_be16(&iop->dat); 537 } 538 539 static int cpm1_gpio16_get(struct gpio_chip *gc, unsigned int gpio) 540 { 541 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 542 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 543 u16 pin_mask; 544 545 pin_mask = 1 << (15 - gpio); 546 547 return !!(in_be16(&iop->dat) & pin_mask); 548 } 549 550 static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask, 551 int value) 552 { 553 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 554 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 555 556 if (value) 557 cpm1_gc->cpdata |= pin_mask; 558 else 559 cpm1_gc->cpdata &= ~pin_mask; 560 561 out_be16(&iop->dat, cpm1_gc->cpdata); 562 } 563 564 static void cpm1_gpio16_set(struct gpio_chip *gc, unsigned int gpio, int value) 565 { 566 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 567 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 568 unsigned long flags; 569 u16 pin_mask = 1 << (15 - gpio); 570 571 spin_lock_irqsave(&cpm1_gc->lock, flags); 572 573 __cpm1_gpio16_set(mm_gc, pin_mask, value); 574 575 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 576 } 577 578 static int cpm1_gpio16_to_irq(struct gpio_chip *gc, unsigned int gpio) 579 { 580 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 581 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 582 583 return cpm1_gc->irq[gpio] ? : -ENXIO; 584 } 585 586 static int cpm1_gpio16_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 587 { 588 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 589 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 590 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 591 unsigned long flags; 592 u16 pin_mask = 1 << (15 - gpio); 593 594 spin_lock_irqsave(&cpm1_gc->lock, flags); 595 596 setbits16(&iop->dir, pin_mask); 597 __cpm1_gpio16_set(mm_gc, pin_mask, val); 598 599 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 600 601 return 0; 602 } 603 604 static int cpm1_gpio16_dir_in(struct gpio_chip *gc, unsigned int gpio) 605 { 606 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 607 struct cpm1_gpio16_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 608 struct cpm_ioport16 __iomem *iop = mm_gc->regs; 609 unsigned long flags; 610 u16 pin_mask = 1 << (15 - gpio); 611 612 spin_lock_irqsave(&cpm1_gc->lock, flags); 613 614 clrbits16(&iop->dir, pin_mask); 615 616 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 617 618 return 0; 619 } 620 621 int cpm1_gpiochip_add16(struct device *dev) 622 { 623 struct device_node *np = dev->of_node; 624 struct cpm1_gpio16_chip *cpm1_gc; 625 struct of_mm_gpio_chip *mm_gc; 626 struct gpio_chip *gc; 627 u16 mask; 628 629 cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL); 630 if (!cpm1_gc) 631 return -ENOMEM; 632 633 spin_lock_init(&cpm1_gc->lock); 634 635 if (!of_property_read_u16(np, "fsl,cpm1-gpio-irq-mask", &mask)) { 636 int i, j; 637 638 for (i = 0, j = 0; i < 16; i++) 639 if (mask & (1 << (15 - i))) 640 cpm1_gc->irq[i] = irq_of_parse_and_map(np, j++); 641 } 642 643 mm_gc = &cpm1_gc->mm_gc; 644 gc = &mm_gc->gc; 645 646 mm_gc->save_regs = cpm1_gpio16_save_regs; 647 gc->ngpio = 16; 648 gc->direction_input = cpm1_gpio16_dir_in; 649 gc->direction_output = cpm1_gpio16_dir_out; 650 gc->get = cpm1_gpio16_get; 651 gc->set = cpm1_gpio16_set; 652 gc->to_irq = cpm1_gpio16_to_irq; 653 gc->parent = dev; 654 gc->owner = THIS_MODULE; 655 656 return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc); 657 } 658 659 struct cpm1_gpio32_chip { 660 struct of_mm_gpio_chip mm_gc; 661 spinlock_t lock; 662 663 /* shadowed data register to clear/set bits safely */ 664 u32 cpdata; 665 }; 666 667 static void cpm1_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc) 668 { 669 struct cpm1_gpio32_chip *cpm1_gc = 670 container_of(mm_gc, struct cpm1_gpio32_chip, mm_gc); 671 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 672 673 cpm1_gc->cpdata = in_be32(&iop->dat); 674 } 675 676 static int cpm1_gpio32_get(struct gpio_chip *gc, unsigned int gpio) 677 { 678 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 679 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 680 u32 pin_mask; 681 682 pin_mask = 1 << (31 - gpio); 683 684 return !!(in_be32(&iop->dat) & pin_mask); 685 } 686 687 static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, 688 int value) 689 { 690 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 691 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 692 693 if (value) 694 cpm1_gc->cpdata |= pin_mask; 695 else 696 cpm1_gc->cpdata &= ~pin_mask; 697 698 out_be32(&iop->dat, cpm1_gc->cpdata); 699 } 700 701 static void cpm1_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value) 702 { 703 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 704 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 705 unsigned long flags; 706 u32 pin_mask = 1 << (31 - gpio); 707 708 spin_lock_irqsave(&cpm1_gc->lock, flags); 709 710 __cpm1_gpio32_set(mm_gc, pin_mask, value); 711 712 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 713 } 714 715 static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 716 { 717 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 718 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 719 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 720 unsigned long flags; 721 u32 pin_mask = 1 << (31 - gpio); 722 723 spin_lock_irqsave(&cpm1_gc->lock, flags); 724 725 setbits32(&iop->dir, pin_mask); 726 __cpm1_gpio32_set(mm_gc, pin_mask, val); 727 728 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 729 730 return 0; 731 } 732 733 static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio) 734 { 735 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc); 736 struct cpm1_gpio32_chip *cpm1_gc = gpiochip_get_data(&mm_gc->gc); 737 struct cpm_ioport32b __iomem *iop = mm_gc->regs; 738 unsigned long flags; 739 u32 pin_mask = 1 << (31 - gpio); 740 741 spin_lock_irqsave(&cpm1_gc->lock, flags); 742 743 clrbits32(&iop->dir, pin_mask); 744 745 spin_unlock_irqrestore(&cpm1_gc->lock, flags); 746 747 return 0; 748 } 749 750 int cpm1_gpiochip_add32(struct device *dev) 751 { 752 struct device_node *np = dev->of_node; 753 struct cpm1_gpio32_chip *cpm1_gc; 754 struct of_mm_gpio_chip *mm_gc; 755 struct gpio_chip *gc; 756 757 cpm1_gc = kzalloc(sizeof(*cpm1_gc), GFP_KERNEL); 758 if (!cpm1_gc) 759 return -ENOMEM; 760 761 spin_lock_init(&cpm1_gc->lock); 762 763 mm_gc = &cpm1_gc->mm_gc; 764 gc = &mm_gc->gc; 765 766 mm_gc->save_regs = cpm1_gpio32_save_regs; 767 gc->ngpio = 32; 768 gc->direction_input = cpm1_gpio32_dir_in; 769 gc->direction_output = cpm1_gpio32_dir_out; 770 gc->get = cpm1_gpio32_get; 771 gc->set = cpm1_gpio32_set; 772 gc->parent = dev; 773 gc->owner = THIS_MODULE; 774 775 return of_mm_gpiochip_add_data(np, mm_gc, cpm1_gc); 776 } 777 778 #endif /* CONFIG_8xx_GPIO */ 779