1 /*
2  * GE PPC9A board support
3  *
4  * Author: Martyn Welch <martyn.welch@ge.com>
5  *
6  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
7  *
8  * This program is free software; you can redistribute  it and/or modify it
9  * under  the terms of  the GNU General  Public License as published by the
10  * Free Software Foundation;  either version 2 of the  License, or (at your
11  * option) any later version.
12  *
13  * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
14  * Copyright 2006 Freescale Semiconductor Inc.
15  *
16  * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
17  */
18 
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/delay.h>
24 #include <linux/seq_file.h>
25 #include <linux/of_platform.h>
26 
27 #include <asm/time.h>
28 #include <asm/machdep.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/prom.h>
31 #include <mm/mmu_decl.h>
32 #include <asm/udbg.h>
33 
34 #include <asm/mpic.h>
35 #include <asm/nvram.h>
36 
37 #include <sysdev/fsl_pci.h>
38 #include <sysdev/fsl_soc.h>
39 #include <sysdev/ge/ge_pic.h>
40 
41 #include "mpc86xx.h"
42 
43 #undef DEBUG
44 
45 #ifdef DEBUG
46 #define DBG (fmt...) do { printk(KERN_ERR "PPC9A: " fmt); } while (0)
47 #else
48 #define DBG (fmt...) do { } while (0)
49 #endif
50 
51 void __iomem *ppc9a_regs;
52 
53 static void __init gef_ppc9a_init_irq(void)
54 {
55 	struct device_node *cascade_node = NULL;
56 
57 	mpc86xx_init_irq();
58 
59 	/*
60 	 * There is a simple interrupt handler in the main FPGA, this needs
61 	 * to be cascaded into the MPIC
62 	 */
63 	cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic-1.00");
64 	if (!cascade_node) {
65 		printk(KERN_WARNING "PPC9A: No FPGA PIC\n");
66 		return;
67 	}
68 
69 	gef_pic_init(cascade_node);
70 	of_node_put(cascade_node);
71 }
72 
73 static void __init gef_ppc9a_setup_arch(void)
74 {
75 	struct device_node *regs;
76 
77 	printk(KERN_INFO "GE Intelligent Platforms PPC9A 6U VME SBC\n");
78 
79 #ifdef CONFIG_SMP
80 	mpc86xx_smp_init();
81 #endif
82 
83 	fsl_pci_assign_primary();
84 
85 	/* Remap basic board registers */
86 	regs = of_find_compatible_node(NULL, NULL, "gef,ppc9a-fpga-regs");
87 	if (regs) {
88 		ppc9a_regs = of_iomap(regs, 0);
89 		if (ppc9a_regs == NULL)
90 			printk(KERN_WARNING "Unable to map board registers\n");
91 		of_node_put(regs);
92 	}
93 
94 #if defined(CONFIG_MMIO_NVRAM)
95 	mmio_nvram_init();
96 #endif
97 }
98 
99 /* Return the PCB revision */
100 static unsigned int gef_ppc9a_get_pcb_rev(void)
101 {
102 	unsigned int reg;
103 
104 	reg = ioread32be(ppc9a_regs);
105 	return (reg >> 16) & 0xff;
106 }
107 
108 /* Return the board (software) revision */
109 static unsigned int gef_ppc9a_get_board_rev(void)
110 {
111 	unsigned int reg;
112 
113 	reg = ioread32be(ppc9a_regs);
114 	return (reg >> 8) & 0xff;
115 }
116 
117 /* Return the FPGA revision */
118 static unsigned int gef_ppc9a_get_fpga_rev(void)
119 {
120 	unsigned int reg;
121 
122 	reg = ioread32be(ppc9a_regs);
123 	return reg & 0xf;
124 }
125 
126 /* Return VME Geographical Address */
127 static unsigned int gef_ppc9a_get_vme_geo_addr(void)
128 {
129 	unsigned int reg;
130 
131 	reg = ioread32be(ppc9a_regs + 0x4);
132 	return reg & 0x1f;
133 }
134 
135 /* Return VME System Controller Status */
136 static unsigned int gef_ppc9a_get_vme_is_syscon(void)
137 {
138 	unsigned int reg;
139 
140 	reg = ioread32be(ppc9a_regs + 0x4);
141 	return (reg >> 9) & 0x1;
142 }
143 
144 static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
145 {
146 	uint svid = mfspr(SPRN_SVR);
147 
148 	seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
149 
150 	seq_printf(m, "Revision\t: %u%c\n", gef_ppc9a_get_pcb_rev(),
151 		('A' + gef_ppc9a_get_board_rev()));
152 	seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev());
153 
154 	seq_printf(m, "SVR\t\t: 0x%x\n", svid);
155 
156 	seq_printf(m, "VME geo. addr\t: %u\n", gef_ppc9a_get_vme_geo_addr());
157 
158 	seq_printf(m, "VME syscon\t: %s\n",
159 		gef_ppc9a_get_vme_is_syscon() ? "yes" : "no");
160 }
161 
162 static void gef_ppc9a_nec_fixup(struct pci_dev *pdev)
163 {
164 	unsigned int val;
165 
166 	/* Do not do the fixup on other platforms! */
167 	if (!machine_is(gef_ppc9a))
168 		return;
169 
170 	printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
171 
172 	/* Ensure ports 1, 2, 3, 4 & 5 are enabled */
173 	pci_read_config_dword(pdev, 0xe0, &val);
174 	pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x5);
175 
176 	/* System clock is 48-MHz Oscillator and EHCI Enabled. */
177 	pci_write_config_dword(pdev, 0xe4, 1 << 5);
178 }
179 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
180 	gef_ppc9a_nec_fixup);
181 
182 /*
183  * Called very early, device-tree isn't unflattened
184  *
185  * This function is called to determine whether the BSP is compatible with the
186  * supplied device-tree, which is assumed to be the correct one for the actual
187  * board. It is expected thati, in the future, a kernel may support multiple
188  * boards.
189  */
190 static int __init gef_ppc9a_probe(void)
191 {
192 	if (of_machine_is_compatible("gef,ppc9a"))
193 		return 1;
194 
195 	return 0;
196 }
197 
198 machine_arch_initcall(gef_ppc9a, mpc86xx_common_publish_devices);
199 
200 define_machine(gef_ppc9a) {
201 	.name			= "GE PPC9A",
202 	.probe			= gef_ppc9a_probe,
203 	.setup_arch		= gef_ppc9a_setup_arch,
204 	.init_IRQ		= gef_ppc9a_init_irq,
205 	.show_cpuinfo		= gef_ppc9a_show_cpuinfo,
206 	.get_irq		= mpic_get_irq,
207 	.time_init		= mpc86xx_time_init,
208 	.calibrate_decr		= generic_calibrate_decr,
209 	.progress		= udbg_progress,
210 #ifdef CONFIG_PCI
211 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
212 #endif
213 };
214