1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc. 4 * 5 * Author: Michael Johnston <michael.johnston@freescale.com> 6 * 7 * Description: 8 * TWR-P102x Board Setup 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/errno.h> 14 #include <linux/fsl/guts.h> 15 #include <linux/pci.h> 16 #include <linux/of_platform.h> 17 18 #include <asm/pci-bridge.h> 19 #include <asm/udbg.h> 20 #include <asm/mpic.h> 21 #include <soc/fsl/qe/qe.h> 22 #include <soc/fsl/qe/qe_ic.h> 23 24 #include <sysdev/fsl_soc.h> 25 #include <sysdev/fsl_pci.h> 26 #include "smp.h" 27 28 #include "mpc85xx.h" 29 30 static void __init twr_p1025_pic_init(void) 31 { 32 struct mpic *mpic; 33 34 #ifdef CONFIG_QUICC_ENGINE 35 struct device_node *np; 36 #endif 37 38 mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | 39 MPIC_SINGLE_DEST_CPU, 40 0, 256, " OpenPIC "); 41 42 BUG_ON(mpic == NULL); 43 mpic_init(mpic); 44 45 #ifdef CONFIG_QUICC_ENGINE 46 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); 47 if (np) { 48 qe_ic_init(np, 0, qe_ic_cascade_low_mpic, 49 qe_ic_cascade_high_mpic); 50 of_node_put(np); 51 } else 52 pr_err("Could not find qe-ic node\n"); 53 #endif 54 } 55 56 /* ************************************************************************ 57 * 58 * Setup the architecture 59 * 60 */ 61 static void __init twr_p1025_setup_arch(void) 62 { 63 #ifdef CONFIG_QUICC_ENGINE 64 struct device_node *np; 65 #endif 66 67 if (ppc_md.progress) 68 ppc_md.progress("twr_p1025_setup_arch()", 0); 69 70 mpc85xx_smp_init(); 71 72 fsl_pci_assign_primary(); 73 74 #ifdef CONFIG_QUICC_ENGINE 75 mpc85xx_qe_par_io_init(); 76 77 #if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE) 78 if (machine_is(twr_p1025)) { 79 struct ccsr_guts __iomem *guts; 80 81 np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts"); 82 if (np) { 83 guts = of_iomap(np, 0); 84 if (!guts) 85 pr_err("twr_p1025: could not map global utilities register\n"); 86 else { 87 /* P1025 has pins muxed for QE and other functions. To 88 * enable QE UEC mode, we need to set bit QE0 for UCC1 89 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 90 * and QE12 for QE MII management signals in PMUXCR 91 * register. 92 * Set QE mux bits in PMUXCR */ 93 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | 94 MPC85xx_PMUXCR_QE(3) | 95 MPC85xx_PMUXCR_QE(9) | 96 MPC85xx_PMUXCR_QE(12)); 97 iounmap(guts); 98 99 #if IS_ENABLED(CONFIG_SERIAL_QE) 100 /* On P1025TWR board, the UCC7 acted as UART port. 101 * However, The UCC7's CTS pin is low level in default, 102 * it will impact the transmission in full duplex 103 * communication. So disable the Flow control pin PA18. 104 * The UCC7 UART just can use RXD and TXD pins. 105 */ 106 par_io_config_pin(0, 18, 0, 0, 0, 0); 107 #endif 108 /* Drive PB29 to CPLD low - CPLD will then change 109 * muxing from LBC to QE */ 110 par_io_config_pin(1, 29, 1, 0, 0, 0); 111 par_io_data_set(1, 29, 0); 112 } 113 of_node_put(np); 114 } 115 } 116 #endif 117 #endif /* CONFIG_QUICC_ENGINE */ 118 119 pr_info("TWR-P1025 board from Freescale Semiconductor\n"); 120 } 121 122 machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices); 123 124 static int __init twr_p1025_probe(void) 125 { 126 return of_machine_is_compatible("fsl,TWR-P1025"); 127 } 128 129 define_machine(twr_p1025) { 130 .name = "TWR-P1025", 131 .probe = twr_p1025_probe, 132 .setup_arch = twr_p1025_setup_arch, 133 .init_IRQ = twr_p1025_pic_init, 134 #ifdef CONFIG_PCI 135 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 136 #endif 137 .get_irq = mpic_get_irq, 138 .calibrate_decr = generic_calibrate_decr, 139 .progress = udbg_progress, 140 }; 141