1 /* 2 * Author: Andy Fleming <afleming@freescale.com> 3 * Kumar Gala <galak@kernel.crashing.org> 4 * 5 * Copyright 2006-2008, 2011-2012 Freescale Semiconductor Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/stddef.h> 14 #include <linux/kernel.h> 15 #include <linux/init.h> 16 #include <linux/delay.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/kexec.h> 20 #include <linux/highmem.h> 21 #include <linux/cpu.h> 22 23 #include <asm/machdep.h> 24 #include <asm/pgtable.h> 25 #include <asm/page.h> 26 #include <asm/mpic.h> 27 #include <asm/cacheflush.h> 28 #include <asm/dbell.h> 29 #include <asm/fsl_guts.h> 30 #include <asm/code-patching.h> 31 32 #include <sysdev/fsl_soc.h> 33 #include <sysdev/mpic.h> 34 #include "smp.h" 35 36 struct epapr_spin_table { 37 u32 addr_h; 38 u32 addr_l; 39 u32 r3_h; 40 u32 r3_l; 41 u32 reserved; 42 u32 pir; 43 }; 44 45 static struct ccsr_guts __iomem *guts; 46 static u64 timebase; 47 static int tb_req; 48 static int tb_valid; 49 50 static void mpc85xx_timebase_freeze(int freeze) 51 { 52 uint32_t mask; 53 54 mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1; 55 if (freeze) 56 setbits32(&guts->devdisr, mask); 57 else 58 clrbits32(&guts->devdisr, mask); 59 60 in_be32(&guts->devdisr); 61 } 62 63 static void mpc85xx_give_timebase(void) 64 { 65 unsigned long flags; 66 67 local_irq_save(flags); 68 69 while (!tb_req) 70 barrier(); 71 tb_req = 0; 72 73 mpc85xx_timebase_freeze(1); 74 #ifdef CONFIG_PPC64 75 /* 76 * e5500/e6500 have a workaround for erratum A-006958 in place 77 * that will reread the timebase until TBL is non-zero. 78 * That would be a bad thing when the timebase is frozen. 79 * 80 * Thus, we read it manually, and instead of checking that 81 * TBL is non-zero, we ensure that TB does not change. We don't 82 * do that for the main mftb implementation, because it requires 83 * a scratch register 84 */ 85 { 86 u64 prev; 87 88 asm volatile("mfspr %0, %1" : "=r" (timebase) : 89 "i" (SPRN_TBRL)); 90 91 do { 92 prev = timebase; 93 asm volatile("mfspr %0, %1" : "=r" (timebase) : 94 "i" (SPRN_TBRL)); 95 } while (prev != timebase); 96 } 97 #else 98 timebase = get_tb(); 99 #endif 100 mb(); 101 tb_valid = 1; 102 103 while (tb_valid) 104 barrier(); 105 106 mpc85xx_timebase_freeze(0); 107 108 local_irq_restore(flags); 109 } 110 111 static void mpc85xx_take_timebase(void) 112 { 113 unsigned long flags; 114 115 local_irq_save(flags); 116 117 tb_req = 1; 118 while (!tb_valid) 119 barrier(); 120 121 set_tb(timebase >> 32, timebase & 0xffffffff); 122 isync(); 123 tb_valid = 0; 124 125 local_irq_restore(flags); 126 } 127 128 #ifdef CONFIG_HOTPLUG_CPU 129 static void smp_85xx_mach_cpu_die(void) 130 { 131 unsigned int cpu = smp_processor_id(); 132 u32 tmp; 133 134 local_irq_disable(); 135 idle_task_exit(); 136 generic_set_cpu_dead(cpu); 137 mb(); 138 139 mtspr(SPRN_TCR, 0); 140 141 __flush_disable_L1(); 142 tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP; 143 mtspr(SPRN_HID0, tmp); 144 isync(); 145 146 /* Enter NAP mode. */ 147 tmp = mfmsr(); 148 tmp |= MSR_WE; 149 mb(); 150 mtmsr(tmp); 151 isync(); 152 153 while (1) 154 ; 155 } 156 #endif 157 158 static inline void flush_spin_table(void *spin_table) 159 { 160 flush_dcache_range((ulong)spin_table, 161 (ulong)spin_table + sizeof(struct epapr_spin_table)); 162 } 163 164 static inline u32 read_spin_table_addr_l(void *spin_table) 165 { 166 flush_dcache_range((ulong)spin_table, 167 (ulong)spin_table + sizeof(struct epapr_spin_table)); 168 return in_be32(&((struct epapr_spin_table *)spin_table)->addr_l); 169 } 170 171 static int smp_85xx_kick_cpu(int nr) 172 { 173 unsigned long flags; 174 const u64 *cpu_rel_addr; 175 __iomem struct epapr_spin_table *spin_table; 176 struct device_node *np; 177 int hw_cpu = get_hard_smp_processor_id(nr); 178 int ioremappable; 179 int ret = 0; 180 181 WARN_ON(nr < 0 || nr >= NR_CPUS); 182 WARN_ON(hw_cpu < 0 || hw_cpu >= NR_CPUS); 183 184 pr_debug("smp_85xx_kick_cpu: kick CPU #%d\n", nr); 185 186 np = of_get_cpu_node(nr, NULL); 187 cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL); 188 189 if (cpu_rel_addr == NULL) { 190 printk(KERN_ERR "No cpu-release-addr for cpu %d\n", nr); 191 return -ENOENT; 192 } 193 194 /* 195 * A secondary core could be in a spinloop in the bootpage 196 * (0xfffff000), somewhere in highmem, or somewhere in lowmem. 197 * The bootpage and highmem can be accessed via ioremap(), but 198 * we need to directly access the spinloop if its in lowmem. 199 */ 200 ioremappable = *cpu_rel_addr > virt_to_phys(high_memory); 201 202 /* Map the spin table */ 203 if (ioremappable) 204 spin_table = ioremap_prot(*cpu_rel_addr, 205 sizeof(struct epapr_spin_table), _PAGE_COHERENT); 206 else 207 spin_table = phys_to_virt(*cpu_rel_addr); 208 209 local_irq_save(flags); 210 #ifdef CONFIG_PPC32 211 #ifdef CONFIG_HOTPLUG_CPU 212 /* Corresponding to generic_set_cpu_dead() */ 213 generic_set_cpu_up(nr); 214 215 if (system_state == SYSTEM_RUNNING) { 216 /* 217 * To keep it compatible with old boot program which uses 218 * cache-inhibit spin table, we need to flush the cache 219 * before accessing spin table to invalidate any staled data. 220 * We also need to flush the cache after writing to spin 221 * table to push data out. 222 */ 223 flush_spin_table(spin_table); 224 out_be32(&spin_table->addr_l, 0); 225 flush_spin_table(spin_table); 226 227 /* 228 * We don't set the BPTR register here since it already points 229 * to the boot page properly. 230 */ 231 mpic_reset_core(nr); 232 233 /* 234 * wait until core is ready... 235 * We need to invalidate the stale data, in case the boot 236 * loader uses a cache-inhibited spin table. 237 */ 238 if (!spin_event_timeout( 239 read_spin_table_addr_l(spin_table) == 1, 240 10000, 100)) { 241 pr_err("%s: timeout waiting for core %d to reset\n", 242 __func__, hw_cpu); 243 ret = -ENOENT; 244 goto out; 245 } 246 247 /* clear the acknowledge status */ 248 __secondary_hold_acknowledge = -1; 249 } 250 #endif 251 flush_spin_table(spin_table); 252 out_be32(&spin_table->pir, hw_cpu); 253 out_be32(&spin_table->addr_l, __pa(__early_start)); 254 flush_spin_table(spin_table); 255 256 /* Wait a bit for the CPU to ack. */ 257 if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu, 258 10000, 100)) { 259 pr_err("%s: timeout waiting for core %d to ack\n", 260 __func__, hw_cpu); 261 ret = -ENOENT; 262 goto out; 263 } 264 out: 265 #else 266 smp_generic_kick_cpu(nr); 267 268 flush_spin_table(spin_table); 269 out_be32(&spin_table->pir, hw_cpu); 270 out_be64((u64 *)(&spin_table->addr_h), 271 __pa(ppc_function_entry(generic_secondary_smp_init))); 272 flush_spin_table(spin_table); 273 #endif 274 275 local_irq_restore(flags); 276 277 if (ioremappable) 278 iounmap(spin_table); 279 280 return ret; 281 } 282 283 struct smp_ops_t smp_85xx_ops = { 284 .kick_cpu = smp_85xx_kick_cpu, 285 .cpu_bootable = smp_generic_cpu_bootable, 286 #ifdef CONFIG_HOTPLUG_CPU 287 .cpu_disable = generic_cpu_disable, 288 .cpu_die = generic_cpu_die, 289 #endif 290 #ifdef CONFIG_KEXEC 291 .give_timebase = smp_generic_give_timebase, 292 .take_timebase = smp_generic_take_timebase, 293 #endif 294 }; 295 296 #ifdef CONFIG_KEXEC 297 atomic_t kexec_down_cpus = ATOMIC_INIT(0); 298 299 void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary) 300 { 301 local_irq_disable(); 302 303 if (secondary) { 304 atomic_inc(&kexec_down_cpus); 305 /* loop forever */ 306 while (1); 307 } 308 } 309 310 static void mpc85xx_smp_kexec_down(void *arg) 311 { 312 if (ppc_md.kexec_cpu_down) 313 ppc_md.kexec_cpu_down(0,1); 314 } 315 316 static void map_and_flush(unsigned long paddr) 317 { 318 struct page *page = pfn_to_page(paddr >> PAGE_SHIFT); 319 unsigned long kaddr = (unsigned long)kmap(page); 320 321 flush_dcache_range(kaddr, kaddr + PAGE_SIZE); 322 kunmap(page); 323 } 324 325 /** 326 * Before we reset the other cores, we need to flush relevant cache 327 * out to memory so we don't get anything corrupted, some of these flushes 328 * are performed out of an overabundance of caution as interrupts are not 329 * disabled yet and we can switch cores 330 */ 331 static void mpc85xx_smp_flush_dcache_kexec(struct kimage *image) 332 { 333 kimage_entry_t *ptr, entry; 334 unsigned long paddr; 335 int i; 336 337 if (image->type == KEXEC_TYPE_DEFAULT) { 338 /* normal kexec images are stored in temporary pages */ 339 for (ptr = &image->head; (entry = *ptr) && !(entry & IND_DONE); 340 ptr = (entry & IND_INDIRECTION) ? 341 phys_to_virt(entry & PAGE_MASK) : ptr + 1) { 342 if (!(entry & IND_DESTINATION)) { 343 map_and_flush(entry); 344 } 345 } 346 /* flush out last IND_DONE page */ 347 map_and_flush(entry); 348 } else { 349 /* crash type kexec images are copied to the crash region */ 350 for (i = 0; i < image->nr_segments; i++) { 351 struct kexec_segment *seg = &image->segment[i]; 352 for (paddr = seg->mem; paddr < seg->mem + seg->memsz; 353 paddr += PAGE_SIZE) { 354 map_and_flush(paddr); 355 } 356 } 357 } 358 359 /* also flush the kimage struct to be passed in as well */ 360 flush_dcache_range((unsigned long)image, 361 (unsigned long)image + sizeof(*image)); 362 } 363 364 static void mpc85xx_smp_machine_kexec(struct kimage *image) 365 { 366 int timeout = INT_MAX; 367 int i, num_cpus = num_present_cpus(); 368 369 mpc85xx_smp_flush_dcache_kexec(image); 370 371 if (image->type == KEXEC_TYPE_DEFAULT) 372 smp_call_function(mpc85xx_smp_kexec_down, NULL, 0); 373 374 while ( (atomic_read(&kexec_down_cpus) != (num_cpus - 1)) && 375 ( timeout > 0 ) ) 376 { 377 timeout--; 378 } 379 380 if ( !timeout ) 381 printk(KERN_ERR "Unable to bring down secondary cpu(s)"); 382 383 for_each_online_cpu(i) 384 { 385 if ( i == smp_processor_id() ) continue; 386 mpic_reset_core(i); 387 } 388 389 default_machine_kexec(image); 390 } 391 #endif /* CONFIG_KEXEC */ 392 393 static void smp_85xx_basic_setup(int cpu_nr) 394 { 395 if (cpu_has_feature(CPU_FTR_DBELL)) 396 doorbell_setup_this_cpu(); 397 } 398 399 static void smp_85xx_setup_cpu(int cpu_nr) 400 { 401 mpic_setup_this_cpu(); 402 smp_85xx_basic_setup(cpu_nr); 403 } 404 405 static const struct of_device_id mpc85xx_smp_guts_ids[] = { 406 { .compatible = "fsl,mpc8572-guts", }, 407 { .compatible = "fsl,p1020-guts", }, 408 { .compatible = "fsl,p1021-guts", }, 409 { .compatible = "fsl,p1022-guts", }, 410 { .compatible = "fsl,p1023-guts", }, 411 { .compatible = "fsl,p2020-guts", }, 412 {}, 413 }; 414 415 void __init mpc85xx_smp_init(void) 416 { 417 struct device_node *np; 418 419 420 np = of_find_node_by_type(NULL, "open-pic"); 421 if (np) { 422 smp_85xx_ops.probe = smp_mpic_probe; 423 smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu; 424 smp_85xx_ops.message_pass = smp_mpic_message_pass; 425 } else 426 smp_85xx_ops.setup_cpu = smp_85xx_basic_setup; 427 428 if (cpu_has_feature(CPU_FTR_DBELL)) { 429 /* 430 * If left NULL, .message_pass defaults to 431 * smp_muxed_ipi_message_pass 432 */ 433 smp_85xx_ops.message_pass = NULL; 434 smp_85xx_ops.cause_ipi = doorbell_cause_ipi; 435 smp_85xx_ops.probe = NULL; 436 } 437 438 np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids); 439 if (np) { 440 guts = of_iomap(np, 0); 441 of_node_put(np); 442 if (!guts) { 443 pr_err("%s: Could not map guts node address\n", 444 __func__); 445 return; 446 } 447 smp_85xx_ops.give_timebase = mpc85xx_give_timebase; 448 smp_85xx_ops.take_timebase = mpc85xx_take_timebase; 449 #ifdef CONFIG_HOTPLUG_CPU 450 ppc_md.cpu_die = smp_85xx_mach_cpu_die; 451 #endif 452 } 453 454 smp_ops = &smp_85xx_ops; 455 456 #ifdef CONFIG_KEXEC 457 ppc_md.kexec_cpu_down = mpc85xx_smp_kexec_cpu_down; 458 ppc_md.machine_kexec = mpc85xx_smp_machine_kexec; 459 #endif 460 } 461