1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC85xx RDB Board Setup 4 * 5 * Copyright 2009,2012-2013 Freescale Semiconductor Inc. 6 */ 7 8 #include <linux/stddef.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/kdev_t.h> 12 #include <linux/delay.h> 13 #include <linux/seq_file.h> 14 #include <linux/interrupt.h> 15 #include <linux/of_platform.h> 16 #include <linux/fsl/guts.h> 17 18 #include <asm/time.h> 19 #include <asm/machdep.h> 20 #include <asm/pci-bridge.h> 21 #include <mm/mmu_decl.h> 22 #include <asm/prom.h> 23 #include <asm/udbg.h> 24 #include <asm/mpic.h> 25 #include <soc/fsl/qe/qe.h> 26 #include <soc/fsl/qe/qe_ic.h> 27 28 #include <sysdev/fsl_soc.h> 29 #include <sysdev/fsl_pci.h> 30 #include "smp.h" 31 32 #include "mpc85xx.h" 33 34 #undef DEBUG 35 36 #ifdef DEBUG 37 #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) 38 #else 39 #define DBG(fmt, args...) 40 #endif 41 42 43 void __init mpc85xx_rdb_pic_init(void) 44 { 45 struct mpic *mpic; 46 47 #ifdef CONFIG_QUICC_ENGINE 48 struct device_node *np; 49 #endif 50 51 if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) { 52 mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET | 53 MPIC_BIG_ENDIAN | 54 MPIC_SINGLE_DEST_CPU, 55 0, 256, " OpenPIC "); 56 } else { 57 mpic = mpic_alloc(NULL, 0, 58 MPIC_BIG_ENDIAN | 59 MPIC_SINGLE_DEST_CPU, 60 0, 256, " OpenPIC "); 61 } 62 63 BUG_ON(mpic == NULL); 64 mpic_init(mpic); 65 66 #ifdef CONFIG_QUICC_ENGINE 67 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); 68 if (np) { 69 qe_ic_init(np, 0, qe_ic_cascade_low_mpic, 70 qe_ic_cascade_high_mpic); 71 of_node_put(np); 72 73 } else 74 pr_err("%s: Could not find qe-ic node\n", __func__); 75 #endif 76 77 } 78 79 /* 80 * Setup the architecture 81 */ 82 static void __init mpc85xx_rdb_setup_arch(void) 83 { 84 if (ppc_md.progress) 85 ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); 86 87 mpc85xx_smp_init(); 88 89 fsl_pci_assign_primary(); 90 91 #ifdef CONFIG_QUICC_ENGINE 92 mpc85xx_qe_init(); 93 mpc85xx_qe_par_io_init(); 94 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) 95 if (machine_is(p1025_rdb)) { 96 struct device_node *np; 97 98 struct ccsr_guts __iomem *guts; 99 100 np = of_find_node_by_name(NULL, "global-utilities"); 101 if (np) { 102 guts = of_iomap(np, 0); 103 if (!guts) { 104 105 pr_err("mpc85xx-rdb: could not map global utilities register\n"); 106 107 } else { 108 /* P1025 has pins muxed for QE and other functions. To 109 * enable QE UEC mode, we need to set bit QE0 for UCC1 110 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 111 * and QE12 for QE MII management singals in PMUXCR 112 * register. 113 */ 114 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | 115 MPC85xx_PMUXCR_QE(3) | 116 MPC85xx_PMUXCR_QE(9) | 117 MPC85xx_PMUXCR_QE(12)); 118 iounmap(guts); 119 } 120 of_node_put(np); 121 } 122 123 } 124 #endif 125 #endif /* CONFIG_QUICC_ENGINE */ 126 127 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); 128 } 129 130 machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices); 131 machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices); 132 machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices); 133 machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices); 134 machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices); 135 machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices); 136 machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); 137 machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); 138 machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices); 139 machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices); 140 141 /* 142 * Called very early, device-tree isn't unflattened 143 */ 144 static int __init p2020_rdb_probe(void) 145 { 146 if (of_machine_is_compatible("fsl,P2020RDB")) 147 return 1; 148 return 0; 149 } 150 151 static int __init p1020_rdb_probe(void) 152 { 153 if (of_machine_is_compatible("fsl,P1020RDB")) 154 return 1; 155 return 0; 156 } 157 158 static int __init p1020_rdb_pc_probe(void) 159 { 160 return of_machine_is_compatible("fsl,P1020RDB-PC"); 161 } 162 163 static int __init p1020_rdb_pd_probe(void) 164 { 165 return of_machine_is_compatible("fsl,P1020RDB-PD"); 166 } 167 168 static int __init p1021_rdb_pc_probe(void) 169 { 170 if (of_machine_is_compatible("fsl,P1021RDB-PC")) 171 return 1; 172 return 0; 173 } 174 175 static int __init p2020_rdb_pc_probe(void) 176 { 177 if (of_machine_is_compatible("fsl,P2020RDB-PC")) 178 return 1; 179 return 0; 180 } 181 182 static int __init p1025_rdb_probe(void) 183 { 184 return of_machine_is_compatible("fsl,P1025RDB"); 185 } 186 187 static int __init p1020_mbg_pc_probe(void) 188 { 189 return of_machine_is_compatible("fsl,P1020MBG-PC"); 190 } 191 192 static int __init p1020_utm_pc_probe(void) 193 { 194 return of_machine_is_compatible("fsl,P1020UTM-PC"); 195 } 196 197 static int __init p1024_rdb_probe(void) 198 { 199 return of_machine_is_compatible("fsl,P1024RDB"); 200 } 201 202 define_machine(p2020_rdb) { 203 .name = "P2020 RDB", 204 .probe = p2020_rdb_probe, 205 .setup_arch = mpc85xx_rdb_setup_arch, 206 .init_IRQ = mpc85xx_rdb_pic_init, 207 #ifdef CONFIG_PCI 208 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 209 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 210 #endif 211 .get_irq = mpic_get_irq, 212 .calibrate_decr = generic_calibrate_decr, 213 .progress = udbg_progress, 214 }; 215 216 define_machine(p1020_rdb) { 217 .name = "P1020 RDB", 218 .probe = p1020_rdb_probe, 219 .setup_arch = mpc85xx_rdb_setup_arch, 220 .init_IRQ = mpc85xx_rdb_pic_init, 221 #ifdef CONFIG_PCI 222 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 223 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 224 #endif 225 .get_irq = mpic_get_irq, 226 .calibrate_decr = generic_calibrate_decr, 227 .progress = udbg_progress, 228 }; 229 230 define_machine(p1021_rdb_pc) { 231 .name = "P1021 RDB-PC", 232 .probe = p1021_rdb_pc_probe, 233 .setup_arch = mpc85xx_rdb_setup_arch, 234 .init_IRQ = mpc85xx_rdb_pic_init, 235 #ifdef CONFIG_PCI 236 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 237 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 238 #endif 239 .get_irq = mpic_get_irq, 240 .calibrate_decr = generic_calibrate_decr, 241 .progress = udbg_progress, 242 }; 243 244 define_machine(p2020_rdb_pc) { 245 .name = "P2020RDB-PC", 246 .probe = p2020_rdb_pc_probe, 247 .setup_arch = mpc85xx_rdb_setup_arch, 248 .init_IRQ = mpc85xx_rdb_pic_init, 249 #ifdef CONFIG_PCI 250 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 251 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 252 #endif 253 .get_irq = mpic_get_irq, 254 .calibrate_decr = generic_calibrate_decr, 255 .progress = udbg_progress, 256 }; 257 258 define_machine(p1025_rdb) { 259 .name = "P1025 RDB", 260 .probe = p1025_rdb_probe, 261 .setup_arch = mpc85xx_rdb_setup_arch, 262 .init_IRQ = mpc85xx_rdb_pic_init, 263 #ifdef CONFIG_PCI 264 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 265 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 266 #endif 267 .get_irq = mpic_get_irq, 268 .calibrate_decr = generic_calibrate_decr, 269 .progress = udbg_progress, 270 }; 271 272 define_machine(p1020_mbg_pc) { 273 .name = "P1020 MBG-PC", 274 .probe = p1020_mbg_pc_probe, 275 .setup_arch = mpc85xx_rdb_setup_arch, 276 .init_IRQ = mpc85xx_rdb_pic_init, 277 #ifdef CONFIG_PCI 278 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 279 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 280 #endif 281 .get_irq = mpic_get_irq, 282 .calibrate_decr = generic_calibrate_decr, 283 .progress = udbg_progress, 284 }; 285 286 define_machine(p1020_utm_pc) { 287 .name = "P1020 UTM-PC", 288 .probe = p1020_utm_pc_probe, 289 .setup_arch = mpc85xx_rdb_setup_arch, 290 .init_IRQ = mpc85xx_rdb_pic_init, 291 #ifdef CONFIG_PCI 292 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 293 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 294 #endif 295 .get_irq = mpic_get_irq, 296 .calibrate_decr = generic_calibrate_decr, 297 .progress = udbg_progress, 298 }; 299 300 define_machine(p1020_rdb_pc) { 301 .name = "P1020RDB-PC", 302 .probe = p1020_rdb_pc_probe, 303 .setup_arch = mpc85xx_rdb_setup_arch, 304 .init_IRQ = mpc85xx_rdb_pic_init, 305 #ifdef CONFIG_PCI 306 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 307 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 308 #endif 309 .get_irq = mpic_get_irq, 310 .calibrate_decr = generic_calibrate_decr, 311 .progress = udbg_progress, 312 }; 313 314 define_machine(p1020_rdb_pd) { 315 .name = "P1020RDB-PD", 316 .probe = p1020_rdb_pd_probe, 317 .setup_arch = mpc85xx_rdb_setup_arch, 318 .init_IRQ = mpc85xx_rdb_pic_init, 319 #ifdef CONFIG_PCI 320 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 321 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 322 #endif 323 .get_irq = mpic_get_irq, 324 .calibrate_decr = generic_calibrate_decr, 325 .progress = udbg_progress, 326 }; 327 328 define_machine(p1024_rdb) { 329 .name = "P1024 RDB", 330 .probe = p1024_rdb_probe, 331 .setup_arch = mpc85xx_rdb_setup_arch, 332 .init_IRQ = mpc85xx_rdb_pic_init, 333 #ifdef CONFIG_PCI 334 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 335 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 336 #endif 337 .get_irq = mpic_get_irq, 338 .calibrate_decr = generic_calibrate_decr, 339 .progress = udbg_progress, 340 }; 341