1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC85xx RDB Board Setup 4 * 5 * Copyright 2009,2012-2013 Freescale Semiconductor Inc. 6 */ 7 8 #include <linux/stddef.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/kdev_t.h> 12 #include <linux/delay.h> 13 #include <linux/seq_file.h> 14 #include <linux/interrupt.h> 15 #include <linux/of_platform.h> 16 #include <linux/fsl/guts.h> 17 18 #include <asm/time.h> 19 #include <asm/machdep.h> 20 #include <asm/pci-bridge.h> 21 #include <mm/mmu_decl.h> 22 #include <asm/udbg.h> 23 #include <asm/mpic.h> 24 #include <soc/fsl/qe/qe.h> 25 26 #include <sysdev/fsl_soc.h> 27 #include <sysdev/fsl_pci.h> 28 #include "smp.h" 29 30 #include "mpc85xx.h" 31 32 static void __init mpc85xx_rdb_pic_init(void) 33 { 34 struct mpic *mpic; 35 int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU; 36 37 if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) 38 flags |= MPIC_NO_RESET; 39 40 mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC "); 41 42 if (WARN_ON(!mpic)) 43 return; 44 45 mpic_init(mpic); 46 } 47 48 /* 49 * Setup the architecture 50 */ 51 static void __init mpc85xx_rdb_setup_arch(void) 52 { 53 if (ppc_md.progress) 54 ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); 55 56 mpc85xx_smp_init(); 57 58 fsl_pci_assign_primary(); 59 60 mpc85xx_qe_par_io_init(); 61 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) 62 if (machine_is(p1025_rdb)) { 63 struct device_node *np; 64 65 struct ccsr_guts __iomem *guts; 66 67 np = of_find_node_by_name(NULL, "global-utilities"); 68 if (np) { 69 guts = of_iomap(np, 0); 70 if (!guts) { 71 72 pr_err("mpc85xx-rdb: could not map global utilities register\n"); 73 74 } else { 75 /* P1025 has pins muxed for QE and other functions. To 76 * enable QE UEC mode, we need to set bit QE0 for UCC1 77 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 78 * and QE12 for QE MII management singals in PMUXCR 79 * register. 80 */ 81 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | 82 MPC85xx_PMUXCR_QE(3) | 83 MPC85xx_PMUXCR_QE(9) | 84 MPC85xx_PMUXCR_QE(12)); 85 iounmap(guts); 86 } 87 of_node_put(np); 88 } 89 90 } 91 #endif 92 93 pr_info("MPC85xx RDB board from Freescale Semiconductor\n"); 94 } 95 96 machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices); 97 machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices); 98 machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices); 99 machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices); 100 machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); 101 machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); 102 machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices); 103 machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices); 104 105 define_machine(p1020_rdb) { 106 .name = "P1020 RDB", 107 .compatible = "fsl,P1020RDB", 108 .setup_arch = mpc85xx_rdb_setup_arch, 109 .init_IRQ = mpc85xx_rdb_pic_init, 110 #ifdef CONFIG_PCI 111 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 112 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 113 #endif 114 .get_irq = mpic_get_irq, 115 .progress = udbg_progress, 116 }; 117 118 define_machine(p1021_rdb_pc) { 119 .name = "P1021 RDB-PC", 120 .compatible = "fsl,P1021RDB-PC", 121 .setup_arch = mpc85xx_rdb_setup_arch, 122 .init_IRQ = mpc85xx_rdb_pic_init, 123 #ifdef CONFIG_PCI 124 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 125 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 126 #endif 127 .get_irq = mpic_get_irq, 128 .progress = udbg_progress, 129 }; 130 131 define_machine(p1025_rdb) { 132 .name = "P1025 RDB", 133 .compatible = "fsl,P1025RDB", 134 .setup_arch = mpc85xx_rdb_setup_arch, 135 .init_IRQ = mpc85xx_rdb_pic_init, 136 #ifdef CONFIG_PCI 137 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 138 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 139 #endif 140 .get_irq = mpic_get_irq, 141 .progress = udbg_progress, 142 }; 143 144 define_machine(p1020_mbg_pc) { 145 .name = "P1020 MBG-PC", 146 .compatible = "fsl,P1020MBG-PC", 147 .setup_arch = mpc85xx_rdb_setup_arch, 148 .init_IRQ = mpc85xx_rdb_pic_init, 149 #ifdef CONFIG_PCI 150 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 151 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 152 #endif 153 .get_irq = mpic_get_irq, 154 .progress = udbg_progress, 155 }; 156 157 define_machine(p1020_utm_pc) { 158 .name = "P1020 UTM-PC", 159 .compatible = "fsl,P1020UTM-PC", 160 .setup_arch = mpc85xx_rdb_setup_arch, 161 .init_IRQ = mpc85xx_rdb_pic_init, 162 #ifdef CONFIG_PCI 163 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 164 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 165 #endif 166 .get_irq = mpic_get_irq, 167 .progress = udbg_progress, 168 }; 169 170 define_machine(p1020_rdb_pc) { 171 .name = "P1020RDB-PC", 172 .compatible = "fsl,P1020RDB-PC", 173 .setup_arch = mpc85xx_rdb_setup_arch, 174 .init_IRQ = mpc85xx_rdb_pic_init, 175 #ifdef CONFIG_PCI 176 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 177 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 178 #endif 179 .get_irq = mpic_get_irq, 180 .progress = udbg_progress, 181 }; 182 183 define_machine(p1020_rdb_pd) { 184 .name = "P1020RDB-PD", 185 .compatible = "fsl,P1020RDB-PD", 186 .setup_arch = mpc85xx_rdb_setup_arch, 187 .init_IRQ = mpc85xx_rdb_pic_init, 188 #ifdef CONFIG_PCI 189 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 190 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 191 #endif 192 .get_irq = mpic_get_irq, 193 .progress = udbg_progress, 194 }; 195 196 define_machine(p1024_rdb) { 197 .name = "P1024 RDB", 198 .compatible = "fsl,P1024RDB", 199 .setup_arch = mpc85xx_rdb_setup_arch, 200 .init_IRQ = mpc85xx_rdb_pic_init, 201 #ifdef CONFIG_PCI 202 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 203 .pcibios_fixup_phb = fsl_pcibios_fixup_phb, 204 #endif 205 .get_irq = mpic_get_irq, 206 .progress = udbg_progress, 207 }; 208