1 /* 2 * MPC85xx RDB Board Setup 3 * 4 * Copyright 2009,2012 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12 #include <linux/stddef.h> 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/kdev_t.h> 16 #include <linux/delay.h> 17 #include <linux/seq_file.h> 18 #include <linux/interrupt.h> 19 #include <linux/of_platform.h> 20 21 #include <asm/time.h> 22 #include <asm/machdep.h> 23 #include <asm/pci-bridge.h> 24 #include <mm/mmu_decl.h> 25 #include <asm/prom.h> 26 #include <asm/udbg.h> 27 #include <asm/mpic.h> 28 #include <asm/qe.h> 29 #include <asm/qe_ic.h> 30 #include <asm/fsl_guts.h> 31 32 #include <sysdev/fsl_soc.h> 33 #include <sysdev/fsl_pci.h> 34 #include "smp.h" 35 36 #include "mpc85xx.h" 37 38 #undef DEBUG 39 40 #ifdef DEBUG 41 #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) 42 #else 43 #define DBG(fmt, args...) 44 #endif 45 46 47 void __init mpc85xx_rdb_pic_init(void) 48 { 49 struct mpic *mpic; 50 unsigned long root = of_get_flat_dt_root(); 51 52 #ifdef CONFIG_QUICC_ENGINE 53 struct device_node *np; 54 #endif 55 56 if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) { 57 mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET | 58 MPIC_BIG_ENDIAN | 59 MPIC_SINGLE_DEST_CPU, 60 0, 256, " OpenPIC "); 61 } else { 62 mpic = mpic_alloc(NULL, 0, 63 MPIC_BIG_ENDIAN | 64 MPIC_SINGLE_DEST_CPU, 65 0, 256, " OpenPIC "); 66 } 67 68 BUG_ON(mpic == NULL); 69 mpic_init(mpic); 70 71 #ifdef CONFIG_QUICC_ENGINE 72 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); 73 if (np) { 74 qe_ic_init(np, 0, qe_ic_cascade_low_mpic, 75 qe_ic_cascade_high_mpic); 76 of_node_put(np); 77 78 } else 79 pr_err("%s: Could not find qe-ic node\n", __func__); 80 #endif 81 82 } 83 84 /* 85 * Setup the architecture 86 */ 87 static void __init mpc85xx_rdb_setup_arch(void) 88 { 89 #ifdef CONFIG_QUICC_ENGINE 90 struct device_node *np; 91 #endif 92 93 if (ppc_md.progress) 94 ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); 95 96 mpc85xx_smp_init(); 97 98 fsl_pci_assign_primary(); 99 100 #ifdef CONFIG_QUICC_ENGINE 101 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 102 if (!np) { 103 pr_err("%s: Could not find Quicc Engine node\n", __func__); 104 goto qe_fail; 105 } 106 107 qe_reset(); 108 of_node_put(np); 109 110 np = of_find_node_by_name(NULL, "par_io"); 111 if (np) { 112 struct device_node *ucc; 113 114 par_io_init(np); 115 of_node_put(np); 116 117 for_each_node_by_name(ucc, "ucc") 118 par_io_of_config(ucc); 119 120 } 121 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) 122 if (machine_is(p1025_rdb)) { 123 124 struct ccsr_guts __iomem *guts; 125 126 np = of_find_node_by_name(NULL, "global-utilities"); 127 if (np) { 128 guts = of_iomap(np, 0); 129 if (!guts) { 130 131 pr_err("mpc85xx-rdb: could not map global utilities register\n"); 132 133 } else { 134 /* P1025 has pins muxed for QE and other functions. To 135 * enable QE UEC mode, we need to set bit QE0 for UCC1 136 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 137 * and QE12 for QE MII management singals in PMUXCR 138 * register. 139 */ 140 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | 141 MPC85xx_PMUXCR_QE(3) | 142 MPC85xx_PMUXCR_QE(9) | 143 MPC85xx_PMUXCR_QE(12)); 144 iounmap(guts); 145 } 146 of_node_put(np); 147 } 148 149 } 150 #endif 151 152 qe_fail: 153 #endif /* CONFIG_QUICC_ENGINE */ 154 155 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); 156 } 157 158 machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices); 159 machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices); 160 machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices); 161 machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices); 162 machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices); 163 machine_arch_initcall(p1020_rdb_pd, mpc85xx_common_publish_devices); 164 machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); 165 machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); 166 machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices); 167 machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices); 168 169 /* 170 * Called very early, device-tree isn't unflattened 171 */ 172 static int __init p2020_rdb_probe(void) 173 { 174 unsigned long root = of_get_flat_dt_root(); 175 176 if (of_flat_dt_is_compatible(root, "fsl,P2020RDB")) 177 return 1; 178 return 0; 179 } 180 181 static int __init p1020_rdb_probe(void) 182 { 183 unsigned long root = of_get_flat_dt_root(); 184 185 if (of_flat_dt_is_compatible(root, "fsl,P1020RDB")) 186 return 1; 187 return 0; 188 } 189 190 static int __init p1020_rdb_pc_probe(void) 191 { 192 unsigned long root = of_get_flat_dt_root(); 193 194 return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PC"); 195 } 196 197 static int __init p1020_rdb_pd_probe(void) 198 { 199 unsigned long root = of_get_flat_dt_root(); 200 201 return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PD"); 202 } 203 204 static int __init p1021_rdb_pc_probe(void) 205 { 206 unsigned long root = of_get_flat_dt_root(); 207 208 if (of_flat_dt_is_compatible(root, "fsl,P1021RDB-PC")) 209 return 1; 210 return 0; 211 } 212 213 static int __init p2020_rdb_pc_probe(void) 214 { 215 unsigned long root = of_get_flat_dt_root(); 216 217 if (of_flat_dt_is_compatible(root, "fsl,P2020RDB-PC")) 218 return 1; 219 return 0; 220 } 221 222 static int __init p1025_rdb_probe(void) 223 { 224 unsigned long root = of_get_flat_dt_root(); 225 226 return of_flat_dt_is_compatible(root, "fsl,P1025RDB"); 227 } 228 229 static int __init p1020_mbg_pc_probe(void) 230 { 231 unsigned long root = of_get_flat_dt_root(); 232 233 return of_flat_dt_is_compatible(root, "fsl,P1020MBG-PC"); 234 } 235 236 static int __init p1020_utm_pc_probe(void) 237 { 238 unsigned long root = of_get_flat_dt_root(); 239 240 return of_flat_dt_is_compatible(root, "fsl,P1020UTM-PC"); 241 } 242 243 static int __init p1024_rdb_probe(void) 244 { 245 unsigned long root = of_get_flat_dt_root(); 246 247 return of_flat_dt_is_compatible(root, "fsl,P1024RDB"); 248 } 249 250 define_machine(p2020_rdb) { 251 .name = "P2020 RDB", 252 .probe = p2020_rdb_probe, 253 .setup_arch = mpc85xx_rdb_setup_arch, 254 .init_IRQ = mpc85xx_rdb_pic_init, 255 #ifdef CONFIG_PCI 256 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 257 #endif 258 .get_irq = mpic_get_irq, 259 .restart = fsl_rstcr_restart, 260 .calibrate_decr = generic_calibrate_decr, 261 .progress = udbg_progress, 262 }; 263 264 define_machine(p1020_rdb) { 265 .name = "P1020 RDB", 266 .probe = p1020_rdb_probe, 267 .setup_arch = mpc85xx_rdb_setup_arch, 268 .init_IRQ = mpc85xx_rdb_pic_init, 269 #ifdef CONFIG_PCI 270 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 271 #endif 272 .get_irq = mpic_get_irq, 273 .restart = fsl_rstcr_restart, 274 .calibrate_decr = generic_calibrate_decr, 275 .progress = udbg_progress, 276 }; 277 278 define_machine(p1021_rdb_pc) { 279 .name = "P1021 RDB-PC", 280 .probe = p1021_rdb_pc_probe, 281 .setup_arch = mpc85xx_rdb_setup_arch, 282 .init_IRQ = mpc85xx_rdb_pic_init, 283 #ifdef CONFIG_PCI 284 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 285 #endif 286 .get_irq = mpic_get_irq, 287 .restart = fsl_rstcr_restart, 288 .calibrate_decr = generic_calibrate_decr, 289 .progress = udbg_progress, 290 }; 291 292 define_machine(p2020_rdb_pc) { 293 .name = "P2020RDB-PC", 294 .probe = p2020_rdb_pc_probe, 295 .setup_arch = mpc85xx_rdb_setup_arch, 296 .init_IRQ = mpc85xx_rdb_pic_init, 297 #ifdef CONFIG_PCI 298 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 299 #endif 300 .get_irq = mpic_get_irq, 301 .restart = fsl_rstcr_restart, 302 .calibrate_decr = generic_calibrate_decr, 303 .progress = udbg_progress, 304 }; 305 306 define_machine(p1025_rdb) { 307 .name = "P1025 RDB", 308 .probe = p1025_rdb_probe, 309 .setup_arch = mpc85xx_rdb_setup_arch, 310 .init_IRQ = mpc85xx_rdb_pic_init, 311 #ifdef CONFIG_PCI 312 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 313 #endif 314 .get_irq = mpic_get_irq, 315 .restart = fsl_rstcr_restart, 316 .calibrate_decr = generic_calibrate_decr, 317 .progress = udbg_progress, 318 }; 319 320 define_machine(p1020_mbg_pc) { 321 .name = "P1020 MBG-PC", 322 .probe = p1020_mbg_pc_probe, 323 .setup_arch = mpc85xx_rdb_setup_arch, 324 .init_IRQ = mpc85xx_rdb_pic_init, 325 #ifdef CONFIG_PCI 326 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 327 #endif 328 .get_irq = mpic_get_irq, 329 .restart = fsl_rstcr_restart, 330 .calibrate_decr = generic_calibrate_decr, 331 .progress = udbg_progress, 332 }; 333 334 define_machine(p1020_utm_pc) { 335 .name = "P1020 UTM-PC", 336 .probe = p1020_utm_pc_probe, 337 .setup_arch = mpc85xx_rdb_setup_arch, 338 .init_IRQ = mpc85xx_rdb_pic_init, 339 #ifdef CONFIG_PCI 340 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 341 #endif 342 .get_irq = mpic_get_irq, 343 .restart = fsl_rstcr_restart, 344 .calibrate_decr = generic_calibrate_decr, 345 .progress = udbg_progress, 346 }; 347 348 define_machine(p1020_rdb_pc) { 349 .name = "P1020RDB-PC", 350 .probe = p1020_rdb_pc_probe, 351 .setup_arch = mpc85xx_rdb_setup_arch, 352 .init_IRQ = mpc85xx_rdb_pic_init, 353 #ifdef CONFIG_PCI 354 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 355 #endif 356 .get_irq = mpic_get_irq, 357 .restart = fsl_rstcr_restart, 358 .calibrate_decr = generic_calibrate_decr, 359 .progress = udbg_progress, 360 }; 361 362 define_machine(p1020_rdb_pd) { 363 .name = "P1020RDB-PD", 364 .probe = p1020_rdb_pd_probe, 365 .setup_arch = mpc85xx_rdb_setup_arch, 366 .init_IRQ = mpc85xx_rdb_pic_init, 367 #ifdef CONFIG_PCI 368 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 369 #endif 370 .get_irq = mpic_get_irq, 371 .restart = fsl_rstcr_restart, 372 .calibrate_decr = generic_calibrate_decr, 373 .progress = udbg_progress, 374 }; 375 376 define_machine(p1024_rdb) { 377 .name = "P1024 RDB", 378 .probe = p1024_rdb_probe, 379 .setup_arch = mpc85xx_rdb_setup_arch, 380 .init_IRQ = mpc85xx_rdb_pic_init, 381 #ifdef CONFIG_PCI 382 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 383 #endif 384 .get_irq = mpic_get_irq, 385 .restart = fsl_rstcr_restart, 386 .calibrate_decr = generic_calibrate_decr, 387 .progress = udbg_progress, 388 }; 389