1 /* 2 * MPC85xx RDB Board Setup 3 * 4 * Copyright 2009,2012 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12 #include <linux/stddef.h> 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/kdev_t.h> 16 #include <linux/delay.h> 17 #include <linux/seq_file.h> 18 #include <linux/interrupt.h> 19 #include <linux/of_platform.h> 20 21 #include <asm/time.h> 22 #include <asm/machdep.h> 23 #include <asm/pci-bridge.h> 24 #include <mm/mmu_decl.h> 25 #include <asm/prom.h> 26 #include <asm/udbg.h> 27 #include <asm/mpic.h> 28 #include <asm/qe.h> 29 #include <asm/qe_ic.h> 30 #include <asm/fsl_guts.h> 31 32 #include <sysdev/fsl_soc.h> 33 #include <sysdev/fsl_pci.h> 34 #include "smp.h" 35 36 #include "mpc85xx.h" 37 38 #undef DEBUG 39 40 #ifdef DEBUG 41 #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) 42 #else 43 #define DBG(fmt, args...) 44 #endif 45 46 47 void __init mpc85xx_rdb_pic_init(void) 48 { 49 struct mpic *mpic; 50 unsigned long root = of_get_flat_dt_root(); 51 52 #ifdef CONFIG_QUICC_ENGINE 53 struct device_node *np; 54 #endif 55 56 if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) { 57 mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET | 58 MPIC_BIG_ENDIAN | 59 MPIC_SINGLE_DEST_CPU, 60 0, 256, " OpenPIC "); 61 } else { 62 mpic = mpic_alloc(NULL, 0, 63 MPIC_BIG_ENDIAN | 64 MPIC_SINGLE_DEST_CPU, 65 0, 256, " OpenPIC "); 66 } 67 68 BUG_ON(mpic == NULL); 69 mpic_init(mpic); 70 71 #ifdef CONFIG_QUICC_ENGINE 72 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic"); 73 if (np) { 74 qe_ic_init(np, 0, qe_ic_cascade_low_mpic, 75 qe_ic_cascade_high_mpic); 76 of_node_put(np); 77 78 } else 79 pr_err("%s: Could not find qe-ic node\n", __func__); 80 #endif 81 82 } 83 84 /* 85 * Setup the architecture 86 */ 87 static void __init mpc85xx_rdb_setup_arch(void) 88 { 89 #ifdef CONFIG_QUICC_ENGINE 90 struct device_node *np; 91 #endif 92 93 if (ppc_md.progress) 94 ppc_md.progress("mpc85xx_rdb_setup_arch()", 0); 95 96 mpc85xx_smp_init(); 97 98 fsl_pci_assign_primary(); 99 100 #ifdef CONFIG_QUICC_ENGINE 101 np = of_find_compatible_node(NULL, NULL, "fsl,qe"); 102 if (!np) { 103 pr_err("%s: Could not find Quicc Engine node\n", __func__); 104 goto qe_fail; 105 } 106 107 qe_reset(); 108 of_node_put(np); 109 110 np = of_find_node_by_name(NULL, "par_io"); 111 if (np) { 112 struct device_node *ucc; 113 114 par_io_init(np); 115 of_node_put(np); 116 117 for_each_node_by_name(ucc, "ucc") 118 par_io_of_config(ucc); 119 120 } 121 #if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE) 122 if (machine_is(p1025_rdb)) { 123 124 struct ccsr_guts __iomem *guts; 125 126 np = of_find_node_by_name(NULL, "global-utilities"); 127 if (np) { 128 guts = of_iomap(np, 0); 129 if (!guts) { 130 131 pr_err("mpc85xx-rdb: could not map global utilities register\n"); 132 133 } else { 134 /* P1025 has pins muxed for QE and other functions. To 135 * enable QE UEC mode, we need to set bit QE0 for UCC1 136 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 137 * and QE12 for QE MII management singals in PMUXCR 138 * register. 139 */ 140 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) | 141 MPC85xx_PMUXCR_QE(3) | 142 MPC85xx_PMUXCR_QE(9) | 143 MPC85xx_PMUXCR_QE(12)); 144 iounmap(guts); 145 } 146 of_node_put(np); 147 } 148 149 } 150 #endif 151 152 qe_fail: 153 #endif /* CONFIG_QUICC_ENGINE */ 154 155 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); 156 } 157 158 machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices); 159 machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices); 160 machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices); 161 machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices); 162 machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices); 163 machine_arch_initcall(p1020_utm_pc, mpc85xx_common_publish_devices); 164 machine_arch_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices); 165 machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices); 166 machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices); 167 168 /* 169 * Called very early, device-tree isn't unflattened 170 */ 171 static int __init p2020_rdb_probe(void) 172 { 173 unsigned long root = of_get_flat_dt_root(); 174 175 if (of_flat_dt_is_compatible(root, "fsl,P2020RDB")) 176 return 1; 177 return 0; 178 } 179 180 static int __init p1020_rdb_probe(void) 181 { 182 unsigned long root = of_get_flat_dt_root(); 183 184 if (of_flat_dt_is_compatible(root, "fsl,P1020RDB")) 185 return 1; 186 return 0; 187 } 188 189 static int __init p1020_rdb_pc_probe(void) 190 { 191 unsigned long root = of_get_flat_dt_root(); 192 193 return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PC"); 194 } 195 196 static int __init p1021_rdb_pc_probe(void) 197 { 198 unsigned long root = of_get_flat_dt_root(); 199 200 if (of_flat_dt_is_compatible(root, "fsl,P1021RDB-PC")) 201 return 1; 202 return 0; 203 } 204 205 static int __init p2020_rdb_pc_probe(void) 206 { 207 unsigned long root = of_get_flat_dt_root(); 208 209 if (of_flat_dt_is_compatible(root, "fsl,P2020RDB-PC")) 210 return 1; 211 return 0; 212 } 213 214 static int __init p1025_rdb_probe(void) 215 { 216 unsigned long root = of_get_flat_dt_root(); 217 218 return of_flat_dt_is_compatible(root, "fsl,P1025RDB"); 219 } 220 221 static int __init p1020_mbg_pc_probe(void) 222 { 223 unsigned long root = of_get_flat_dt_root(); 224 225 return of_flat_dt_is_compatible(root, "fsl,P1020MBG-PC"); 226 } 227 228 static int __init p1020_utm_pc_probe(void) 229 { 230 unsigned long root = of_get_flat_dt_root(); 231 232 return of_flat_dt_is_compatible(root, "fsl,P1020UTM-PC"); 233 } 234 235 static int __init p1024_rdb_probe(void) 236 { 237 unsigned long root = of_get_flat_dt_root(); 238 239 return of_flat_dt_is_compatible(root, "fsl,P1024RDB"); 240 } 241 242 define_machine(p2020_rdb) { 243 .name = "P2020 RDB", 244 .probe = p2020_rdb_probe, 245 .setup_arch = mpc85xx_rdb_setup_arch, 246 .init_IRQ = mpc85xx_rdb_pic_init, 247 #ifdef CONFIG_PCI 248 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 249 #endif 250 .get_irq = mpic_get_irq, 251 .restart = fsl_rstcr_restart, 252 .calibrate_decr = generic_calibrate_decr, 253 .progress = udbg_progress, 254 }; 255 256 define_machine(p1020_rdb) { 257 .name = "P1020 RDB", 258 .probe = p1020_rdb_probe, 259 .setup_arch = mpc85xx_rdb_setup_arch, 260 .init_IRQ = mpc85xx_rdb_pic_init, 261 #ifdef CONFIG_PCI 262 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 263 #endif 264 .get_irq = mpic_get_irq, 265 .restart = fsl_rstcr_restart, 266 .calibrate_decr = generic_calibrate_decr, 267 .progress = udbg_progress, 268 }; 269 270 define_machine(p1021_rdb_pc) { 271 .name = "P1021 RDB-PC", 272 .probe = p1021_rdb_pc_probe, 273 .setup_arch = mpc85xx_rdb_setup_arch, 274 .init_IRQ = mpc85xx_rdb_pic_init, 275 #ifdef CONFIG_PCI 276 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 277 #endif 278 .get_irq = mpic_get_irq, 279 .restart = fsl_rstcr_restart, 280 .calibrate_decr = generic_calibrate_decr, 281 .progress = udbg_progress, 282 }; 283 284 define_machine(p2020_rdb_pc) { 285 .name = "P2020RDB-PC", 286 .probe = p2020_rdb_pc_probe, 287 .setup_arch = mpc85xx_rdb_setup_arch, 288 .init_IRQ = mpc85xx_rdb_pic_init, 289 #ifdef CONFIG_PCI 290 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 291 #endif 292 .get_irq = mpic_get_irq, 293 .restart = fsl_rstcr_restart, 294 .calibrate_decr = generic_calibrate_decr, 295 .progress = udbg_progress, 296 }; 297 298 define_machine(p1025_rdb) { 299 .name = "P1025 RDB", 300 .probe = p1025_rdb_probe, 301 .setup_arch = mpc85xx_rdb_setup_arch, 302 .init_IRQ = mpc85xx_rdb_pic_init, 303 #ifdef CONFIG_PCI 304 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 305 #endif 306 .get_irq = mpic_get_irq, 307 .restart = fsl_rstcr_restart, 308 .calibrate_decr = generic_calibrate_decr, 309 .progress = udbg_progress, 310 }; 311 312 define_machine(p1020_mbg_pc) { 313 .name = "P1020 MBG-PC", 314 .probe = p1020_mbg_pc_probe, 315 .setup_arch = mpc85xx_rdb_setup_arch, 316 .init_IRQ = mpc85xx_rdb_pic_init, 317 #ifdef CONFIG_PCI 318 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 319 #endif 320 .get_irq = mpic_get_irq, 321 .restart = fsl_rstcr_restart, 322 .calibrate_decr = generic_calibrate_decr, 323 .progress = udbg_progress, 324 }; 325 326 define_machine(p1020_utm_pc) { 327 .name = "P1020 UTM-PC", 328 .probe = p1020_utm_pc_probe, 329 .setup_arch = mpc85xx_rdb_setup_arch, 330 .init_IRQ = mpc85xx_rdb_pic_init, 331 #ifdef CONFIG_PCI 332 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 333 #endif 334 .get_irq = mpic_get_irq, 335 .restart = fsl_rstcr_restart, 336 .calibrate_decr = generic_calibrate_decr, 337 .progress = udbg_progress, 338 }; 339 340 define_machine(p1020_rdb_pc) { 341 .name = "P1020RDB-PC", 342 .probe = p1020_rdb_pc_probe, 343 .setup_arch = mpc85xx_rdb_setup_arch, 344 .init_IRQ = mpc85xx_rdb_pic_init, 345 #ifdef CONFIG_PCI 346 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 347 #endif 348 .get_irq = mpic_get_irq, 349 .restart = fsl_rstcr_restart, 350 .calibrate_decr = generic_calibrate_decr, 351 .progress = udbg_progress, 352 }; 353 354 define_machine(p1024_rdb) { 355 .name = "P1024 RDB", 356 .probe = p1024_rdb_probe, 357 .setup_arch = mpc85xx_rdb_setup_arch, 358 .init_IRQ = mpc85xx_rdb_pic_init, 359 #ifdef CONFIG_PCI 360 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 361 #endif 362 .get_irq = mpic_get_irq, 363 .restart = fsl_rstcr_restart, 364 .calibrate_decr = generic_calibrate_decr, 365 .progress = udbg_progress, 366 }; 367