1 /*
2  * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved.
3  *
4  * Author: Andy Fleming <afleming@freescale.com>
5  *
6  * Based on 83xx/mpc8360e_pb.c by:
7  *	   Li Yang <LeoLi@freescale.com>
8  *	   Yin Olivia <Hong-hua.Yin@freescale.com>
9  *
10  * Description:
11  * MPC85xx MDS board specific routines.
12  *
13  * This program is free software; you can redistribute  it and/or modify it
14  * under  the terms of  the GNU General  Public License as published by the
15  * Free Software Foundation;  either version 2 of the  License, or (at your
16  * option) any later version.
17  */
18 
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/reboot.h>
24 #include <linux/pci.h>
25 #include <linux/kdev_t.h>
26 #include <linux/major.h>
27 #include <linux/console.h>
28 #include <linux/delay.h>
29 #include <linux/seq_file.h>
30 #include <linux/initrd.h>
31 #include <linux/module.h>
32 #include <linux/fsl_devices.h>
33 #include <linux/of_platform.h>
34 #include <linux/of_device.h>
35 #include <linux/phy.h>
36 #include <linux/memblock.h>
37 
38 #include <asm/system.h>
39 #include <asm/atomic.h>
40 #include <asm/time.h>
41 #include <asm/io.h>
42 #include <asm/machdep.h>
43 #include <asm/pci-bridge.h>
44 #include <asm/irq.h>
45 #include <mm/mmu_decl.h>
46 #include <asm/prom.h>
47 #include <asm/udbg.h>
48 #include <sysdev/fsl_soc.h>
49 #include <sysdev/fsl_pci.h>
50 #include <sysdev/simple_gpio.h>
51 #include <asm/qe.h>
52 #include <asm/qe_ic.h>
53 #include <asm/mpic.h>
54 #include <asm/swiotlb.h>
55 
56 #undef DEBUG
57 #ifdef DEBUG
58 #define DBG(fmt...) udbg_printf(fmt)
59 #else
60 #define DBG(fmt...)
61 #endif
62 
63 #define MV88E1111_SCR	0x10
64 #define MV88E1111_SCR_125CLK	0x0010
65 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
66 {
67 	int scr;
68 	int err;
69 
70 	/* Workaround for the 125 CLK Toggle */
71 	scr = phy_read(phydev, MV88E1111_SCR);
72 
73 	if (scr < 0)
74 		return scr;
75 
76 	err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
77 
78 	if (err)
79 		return err;
80 
81 	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
82 
83 	if (err)
84 		return err;
85 
86 	scr = phy_read(phydev, MV88E1111_SCR);
87 
88 	if (scr < 0)
89 		return scr;
90 
91 	err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
92 
93 	return err;
94 }
95 
96 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
97 {
98 	int temp;
99 	int err;
100 
101 	/* Errata */
102 	err = phy_write(phydev,29, 0x0006);
103 
104 	if (err)
105 		return err;
106 
107 	temp = phy_read(phydev, 30);
108 
109 	if (temp < 0)
110 		return temp;
111 
112 	temp = (temp & (~0x8000)) | 0x4000;
113 	err = phy_write(phydev,30, temp);
114 
115 	if (err)
116 		return err;
117 
118 	err = phy_write(phydev,29, 0x000a);
119 
120 	if (err)
121 		return err;
122 
123 	temp = phy_read(phydev, 30);
124 
125 	if (temp < 0)
126 		return temp;
127 
128 	temp = phy_read(phydev, 30);
129 
130 	if (temp < 0)
131 		return temp;
132 
133 	temp &= ~0x0020;
134 
135 	err = phy_write(phydev,30,temp);
136 
137 	if (err)
138 		return err;
139 
140 	/* Disable automatic MDI/MDIX selection */
141 	temp = phy_read(phydev, 16);
142 
143 	if (temp < 0)
144 		return temp;
145 
146 	temp &= ~0x0060;
147 	err = phy_write(phydev,16,temp);
148 
149 	return err;
150 }
151 
152 /* ************************************************************************
153  *
154  * Setup the architecture
155  *
156  */
157 #ifdef CONFIG_SMP
158 extern void __init mpc85xx_smp_init(void);
159 #endif
160 
161 #ifdef CONFIG_QUICC_ENGINE
162 static struct of_device_id mpc85xx_qe_ids[] __initdata = {
163 	{ .type = "qe", },
164 	{ .compatible = "fsl,qe", },
165 	{ },
166 };
167 
168 static void __init mpc85xx_publish_qe_devices(void)
169 {
170 	struct device_node *np;
171 
172 	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
173 	if (!of_device_is_available(np)) {
174 		of_node_put(np);
175 		return;
176 	}
177 
178 	of_platform_bus_probe(NULL, mpc85xx_qe_ids, NULL);
179 }
180 
181 static void __init mpc85xx_mds_reset_ucc_phys(void)
182 {
183 	struct device_node *np;
184 	static u8 __iomem *bcsr_regs;
185 
186 	/* Map BCSR area */
187 	np = of_find_node_by_name(NULL, "bcsr");
188 	if (!np)
189 		return;
190 
191 	bcsr_regs = of_iomap(np, 0);
192 	of_node_put(np);
193 	if (!bcsr_regs)
194 		return;
195 
196 	if (machine_is(mpc8568_mds)) {
197 #define BCSR_UCC1_GETH_EN	(0x1 << 7)
198 #define BCSR_UCC2_GETH_EN	(0x1 << 7)
199 #define BCSR_UCC1_MODE_MSK	(0x3 << 4)
200 #define BCSR_UCC2_MODE_MSK	(0x3 << 0)
201 
202 		/* Turn off UCC1 & UCC2 */
203 		clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
204 		clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
205 
206 		/* Mode is RGMII, all bits clear */
207 		clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
208 					 BCSR_UCC2_MODE_MSK);
209 
210 		/* Turn UCC1 & UCC2 on */
211 		setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
212 		setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
213 	} else if (machine_is(mpc8569_mds)) {
214 #define BCSR7_UCC12_GETHnRST	(0x1 << 2)
215 #define BCSR8_UEM_MARVELL_RST	(0x1 << 1)
216 #define BCSR_UCC_RGMII		(0x1 << 6)
217 #define BCSR_UCC_RTBI		(0x1 << 5)
218 		/*
219 		 * U-Boot mangles interrupt polarity for Marvell PHYs,
220 		 * so reset built-in and UEM Marvell PHYs, this puts
221 		 * the PHYs into their normal state.
222 		 */
223 		clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
224 		setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
225 
226 		setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
227 		clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
228 
229 		for (np = NULL; (np = of_find_compatible_node(np,
230 						"network",
231 						"ucc_geth")) != NULL;) {
232 			const unsigned int *prop;
233 			int ucc_num;
234 
235 			prop = of_get_property(np, "cell-index", NULL);
236 			if (prop == NULL)
237 				continue;
238 
239 			ucc_num = *prop - 1;
240 
241 			prop = of_get_property(np, "phy-connection-type", NULL);
242 			if (prop == NULL)
243 				continue;
244 
245 			if (strcmp("rtbi", (const char *)prop) == 0)
246 				clrsetbits_8(&bcsr_regs[7 + ucc_num],
247 					BCSR_UCC_RGMII, BCSR_UCC_RTBI);
248 		}
249 	} else if (machine_is(p1021_mds)) {
250 #define BCSR11_ENET_MICRST     (0x1 << 5)
251 		/* Reset Micrel PHY */
252 		clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
253 		setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
254 	}
255 
256 	iounmap(bcsr_regs);
257 }
258 
259 static void __init mpc85xx_mds_qe_init(void)
260 {
261 	struct device_node *np;
262 
263 	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
264 	if (!np) {
265 		np = of_find_node_by_name(NULL, "qe");
266 		if (!np)
267 			return;
268 	}
269 
270 	if (!of_device_is_available(np)) {
271 		of_node_put(np);
272 		return;
273 	}
274 
275 	qe_reset();
276 	of_node_put(np);
277 
278 	np = of_find_node_by_name(NULL, "par_io");
279 	if (np) {
280 		struct device_node *ucc;
281 
282 		par_io_init(np);
283 		of_node_put(np);
284 
285 		for_each_node_by_name(ucc, "ucc")
286 			par_io_of_config(ucc);
287 	}
288 
289 	mpc85xx_mds_reset_ucc_phys();
290 
291 	if (machine_is(p1021_mds)) {
292 #define MPC85xx_PMUXCR_OFFSET           0x60
293 #define MPC85xx_PMUXCR_QE0              0x00008000
294 #define MPC85xx_PMUXCR_QE3              0x00001000
295 #define MPC85xx_PMUXCR_QE9              0x00000040
296 #define MPC85xx_PMUXCR_QE12             0x00000008
297 		static __be32 __iomem *pmuxcr;
298 
299 		np = of_find_node_by_name(NULL, "global-utilities");
300 
301 		if (np) {
302 			pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
303 
304 			if (!pmuxcr)
305 				printk(KERN_EMERG "Error: Alternate function"
306 					" signal multiplex control register not"
307 					" mapped!\n");
308 			else
309 			/* P1021 has pins muxed for QE and other functions. To
310 			 * enable QE UEC mode, we need to set bit QE0 for UCC1
311 			 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
312 			 * and QE12 for QE MII management signals in PMUXCR
313 			 * register.
314 			 */
315 				setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
316 						  MPC85xx_PMUXCR_QE3 |
317 						  MPC85xx_PMUXCR_QE9 |
318 						  MPC85xx_PMUXCR_QE12);
319 
320 			of_node_put(np);
321 		}
322 
323 	}
324 }
325 
326 static void __init mpc85xx_mds_qeic_init(void)
327 {
328 	struct device_node *np;
329 
330 	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
331 	if (!of_device_is_available(np)) {
332 		of_node_put(np);
333 		return;
334 	}
335 
336 	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
337 	if (!np) {
338 		np = of_find_node_by_type(NULL, "qeic");
339 		if (!np)
340 			return;
341 	}
342 
343 	if (machine_is(p1021_mds))
344 		qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
345 				qe_ic_cascade_high_mpic);
346 	else
347 		qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
348 	of_node_put(np);
349 }
350 #else
351 static void __init mpc85xx_publish_qe_devices(void) { }
352 static void __init mpc85xx_mds_qe_init(void) { }
353 static void __init mpc85xx_mds_qeic_init(void) { }
354 #endif	/* CONFIG_QUICC_ENGINE */
355 
356 static void __init mpc85xx_mds_setup_arch(void)
357 {
358 #ifdef CONFIG_PCI
359 	struct pci_controller *hose;
360 	struct device_node *np;
361 #endif
362 	dma_addr_t max = 0xffffffff;
363 
364 	if (ppc_md.progress)
365 		ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
366 
367 #ifdef CONFIG_PCI
368 	for_each_node_by_type(np, "pci") {
369 		if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
370 		    of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
371 			struct resource rsrc;
372 			of_address_to_resource(np, 0, &rsrc);
373 			if ((rsrc.start & 0xfffff) == 0x8000)
374 				fsl_add_bridge(np, 1);
375 			else
376 				fsl_add_bridge(np, 0);
377 
378 			hose = pci_find_hose_for_OF_device(np);
379 			max = min(max, hose->dma_window_base_cur +
380 					hose->dma_window_size);
381 		}
382 	}
383 #endif
384 
385 #ifdef CONFIG_SMP
386 	mpc85xx_smp_init();
387 #endif
388 
389 	mpc85xx_mds_qe_init();
390 
391 #ifdef CONFIG_SWIOTLB
392 	if (memblock_end_of_DRAM() > max) {
393 		ppc_swiotlb_enable = 1;
394 		set_pci_dma_ops(&swiotlb_dma_ops);
395 		ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
396 	}
397 #endif
398 }
399 
400 
401 static int __init board_fixups(void)
402 {
403 	char phy_id[20];
404 	char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
405 	struct device_node *mdio;
406 	struct resource res;
407 	int i;
408 
409 	for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
410 		mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
411 
412 		of_address_to_resource(mdio, 0, &res);
413 		snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
414 			(unsigned long long)res.start, 1);
415 
416 		phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
417 		phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
418 
419 		/* Register a workaround for errata */
420 		snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
421 			(unsigned long long)res.start, 7);
422 		phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
423 
424 		of_node_put(mdio);
425 	}
426 
427 	return 0;
428 }
429 machine_arch_initcall(mpc8568_mds, board_fixups);
430 machine_arch_initcall(mpc8569_mds, board_fixups);
431 
432 static struct of_device_id mpc85xx_ids[] = {
433 	{ .type = "soc", },
434 	{ .compatible = "soc", },
435 	{ .compatible = "simple-bus", },
436 	{ .compatible = "gianfar", },
437 	{ .compatible = "fsl,rapidio-delta", },
438 	{ .compatible = "fsl,mpc8548-guts", },
439 	{ .compatible = "gpio-leds", },
440 	{},
441 };
442 
443 static struct of_device_id p1021_ids[] = {
444 	{ .type = "soc", },
445 	{ .compatible = "soc", },
446 	{ .compatible = "simple-bus", },
447 	{ .compatible = "gianfar", },
448 	{},
449 };
450 
451 static int __init mpc85xx_publish_devices(void)
452 {
453 	if (machine_is(mpc8568_mds))
454 		simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
455 	if (machine_is(mpc8569_mds))
456 		simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
457 
458 	of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
459 	mpc85xx_publish_qe_devices();
460 
461 	return 0;
462 }
463 
464 static int __init p1021_publish_devices(void)
465 {
466 	of_platform_bus_probe(NULL, p1021_ids, NULL);
467 	mpc85xx_publish_qe_devices();
468 
469 	return 0;
470 }
471 
472 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
473 machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
474 machine_device_initcall(p1021_mds, p1021_publish_devices);
475 
476 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
477 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
478 machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
479 
480 static void __init mpc85xx_mds_pic_init(void)
481 {
482 	struct mpic *mpic;
483 	struct resource r;
484 	struct device_node *np = NULL;
485 
486 	np = of_find_node_by_type(NULL, "open-pic");
487 	if (!np)
488 		return;
489 
490 	if (of_address_to_resource(np, 0, &r)) {
491 		printk(KERN_ERR "Failed to map mpic register space\n");
492 		of_node_put(np);
493 		return;
494 	}
495 
496 	mpic = mpic_alloc(np, r.start,
497 			MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
498 			MPIC_BROKEN_FRR_NIRQS | MPIC_SINGLE_DEST_CPU,
499 			0, 256, " OpenPIC  ");
500 	BUG_ON(mpic == NULL);
501 	of_node_put(np);
502 
503 	mpic_init(mpic);
504 	mpc85xx_mds_qeic_init();
505 }
506 
507 static int __init mpc85xx_mds_probe(void)
508 {
509         unsigned long root = of_get_flat_dt_root();
510 
511         return of_flat_dt_is_compatible(root, "MPC85xxMDS");
512 }
513 
514 define_machine(mpc8568_mds) {
515 	.name		= "MPC8568 MDS",
516 	.probe		= mpc85xx_mds_probe,
517 	.setup_arch	= mpc85xx_mds_setup_arch,
518 	.init_IRQ	= mpc85xx_mds_pic_init,
519 	.get_irq	= mpic_get_irq,
520 	.restart	= fsl_rstcr_restart,
521 	.calibrate_decr	= generic_calibrate_decr,
522 	.progress	= udbg_progress,
523 #ifdef CONFIG_PCI
524 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
525 #endif
526 };
527 
528 static int __init mpc8569_mds_probe(void)
529 {
530 	unsigned long root = of_get_flat_dt_root();
531 
532 	return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
533 }
534 
535 define_machine(mpc8569_mds) {
536 	.name		= "MPC8569 MDS",
537 	.probe		= mpc8569_mds_probe,
538 	.setup_arch	= mpc85xx_mds_setup_arch,
539 	.init_IRQ	= mpc85xx_mds_pic_init,
540 	.get_irq	= mpic_get_irq,
541 	.restart	= fsl_rstcr_restart,
542 	.calibrate_decr	= generic_calibrate_decr,
543 	.progress	= udbg_progress,
544 #ifdef CONFIG_PCI
545 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
546 #endif
547 };
548 
549 static int __init p1021_mds_probe(void)
550 {
551 	unsigned long root = of_get_flat_dt_root();
552 
553 	return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
554 
555 }
556 
557 define_machine(p1021_mds) {
558 	.name		= "P1021 MDS",
559 	.probe		= p1021_mds_probe,
560 	.setup_arch	= mpc85xx_mds_setup_arch,
561 	.init_IRQ	= mpc85xx_mds_pic_init,
562 	.get_irq	= mpic_get_irq,
563 	.restart	= fsl_rstcr_restart,
564 	.calibrate_decr	= generic_calibrate_decr,
565 	.progress	= udbg_progress,
566 #ifdef CONFIG_PCI
567 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
568 #endif
569 };
570 
571