1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
4  * All rights reserved.
5  *
6  * Author: Andy Fleming <afleming@freescale.com>
7  *
8  * Based on 83xx/mpc8360e_pb.c by:
9  *	   Li Yang <LeoLi@freescale.com>
10  *	   Yin Olivia <Hong-hua.Yin@freescale.com>
11  *
12  * Description:
13  * MPC85xx MDS board specific routines.
14  */
15 
16 #include <linux/stddef.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/reboot.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/major.h>
24 #include <linux/console.h>
25 #include <linux/delay.h>
26 #include <linux/seq_file.h>
27 #include <linux/initrd.h>
28 #include <linux/fsl_devices.h>
29 #include <linux/of_platform.h>
30 #include <linux/of_device.h>
31 #include <linux/phy.h>
32 #include <linux/memblock.h>
33 #include <linux/fsl/guts.h>
34 
35 #include <linux/atomic.h>
36 #include <asm/time.h>
37 #include <asm/io.h>
38 #include <asm/machdep.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/irq.h>
41 #include <mm/mmu_decl.h>
42 #include <asm/prom.h>
43 #include <asm/udbg.h>
44 #include <sysdev/fsl_soc.h>
45 #include <sysdev/fsl_pci.h>
46 #include <soc/fsl/qe/qe.h>
47 #include <soc/fsl/qe/qe_ic.h>
48 #include <asm/mpic.h>
49 #include <asm/swiotlb.h>
50 #include "smp.h"
51 
52 #include "mpc85xx.h"
53 
54 #undef DEBUG
55 #ifdef DEBUG
56 #define DBG(fmt...) udbg_printf(fmt)
57 #else
58 #define DBG(fmt...)
59 #endif
60 
61 #if IS_BUILTIN(CONFIG_PHYLIB)
62 
63 #define MV88E1111_SCR	0x10
64 #define MV88E1111_SCR_125CLK	0x0010
65 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
66 {
67 	int scr;
68 	int err;
69 
70 	/* Workaround for the 125 CLK Toggle */
71 	scr = phy_read(phydev, MV88E1111_SCR);
72 
73 	if (scr < 0)
74 		return scr;
75 
76 	err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
77 
78 	if (err)
79 		return err;
80 
81 	err = phy_write(phydev, MII_BMCR, BMCR_RESET);
82 
83 	if (err)
84 		return err;
85 
86 	scr = phy_read(phydev, MV88E1111_SCR);
87 
88 	if (scr < 0)
89 		return scr;
90 
91 	err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
92 
93 	return err;
94 }
95 
96 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
97 {
98 	int temp;
99 	int err;
100 
101 	/* Errata */
102 	err = phy_write(phydev,29, 0x0006);
103 
104 	if (err)
105 		return err;
106 
107 	temp = phy_read(phydev, 30);
108 
109 	if (temp < 0)
110 		return temp;
111 
112 	temp = (temp & (~0x8000)) | 0x4000;
113 	err = phy_write(phydev,30, temp);
114 
115 	if (err)
116 		return err;
117 
118 	err = phy_write(phydev,29, 0x000a);
119 
120 	if (err)
121 		return err;
122 
123 	temp = phy_read(phydev, 30);
124 
125 	if (temp < 0)
126 		return temp;
127 
128 	temp = phy_read(phydev, 30);
129 
130 	if (temp < 0)
131 		return temp;
132 
133 	temp &= ~0x0020;
134 
135 	err = phy_write(phydev,30,temp);
136 
137 	if (err)
138 		return err;
139 
140 	/* Disable automatic MDI/MDIX selection */
141 	temp = phy_read(phydev, 16);
142 
143 	if (temp < 0)
144 		return temp;
145 
146 	temp &= ~0x0060;
147 	err = phy_write(phydev,16,temp);
148 
149 	return err;
150 }
151 
152 #endif
153 
154 /* ************************************************************************
155  *
156  * Setup the architecture
157  *
158  */
159 #ifdef CONFIG_QUICC_ENGINE
160 static void __init mpc85xx_mds_reset_ucc_phys(void)
161 {
162 	struct device_node *np;
163 	static u8 __iomem *bcsr_regs;
164 
165 	/* Map BCSR area */
166 	np = of_find_node_by_name(NULL, "bcsr");
167 	if (!np)
168 		return;
169 
170 	bcsr_regs = of_iomap(np, 0);
171 	of_node_put(np);
172 	if (!bcsr_regs)
173 		return;
174 
175 	if (machine_is(mpc8568_mds)) {
176 #define BCSR_UCC1_GETH_EN	(0x1 << 7)
177 #define BCSR_UCC2_GETH_EN	(0x1 << 7)
178 #define BCSR_UCC1_MODE_MSK	(0x3 << 4)
179 #define BCSR_UCC2_MODE_MSK	(0x3 << 0)
180 
181 		/* Turn off UCC1 & UCC2 */
182 		clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
183 		clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
184 
185 		/* Mode is RGMII, all bits clear */
186 		clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
187 					 BCSR_UCC2_MODE_MSK);
188 
189 		/* Turn UCC1 & UCC2 on */
190 		setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
191 		setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
192 	} else if (machine_is(mpc8569_mds)) {
193 #define BCSR7_UCC12_GETHnRST	(0x1 << 2)
194 #define BCSR8_UEM_MARVELL_RST	(0x1 << 1)
195 #define BCSR_UCC_RGMII		(0x1 << 6)
196 #define BCSR_UCC_RTBI		(0x1 << 5)
197 		/*
198 		 * U-Boot mangles interrupt polarity for Marvell PHYs,
199 		 * so reset built-in and UEM Marvell PHYs, this puts
200 		 * the PHYs into their normal state.
201 		 */
202 		clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
203 		setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
204 
205 		setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
206 		clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
207 
208 		for_each_compatible_node(np, "network", "ucc_geth") {
209 			const unsigned int *prop;
210 			int ucc_num;
211 
212 			prop = of_get_property(np, "cell-index", NULL);
213 			if (prop == NULL)
214 				continue;
215 
216 			ucc_num = *prop - 1;
217 
218 			prop = of_get_property(np, "phy-connection-type", NULL);
219 			if (prop == NULL)
220 				continue;
221 
222 			if (strcmp("rtbi", (const char *)prop) == 0)
223 				clrsetbits_8(&bcsr_regs[7 + ucc_num],
224 					BCSR_UCC_RGMII, BCSR_UCC_RTBI);
225 		}
226 	} else if (machine_is(p1021_mds)) {
227 #define BCSR11_ENET_MICRST     (0x1 << 5)
228 		/* Reset Micrel PHY */
229 		clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
230 		setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
231 	}
232 
233 	iounmap(bcsr_regs);
234 }
235 
236 static void __init mpc85xx_mds_qe_init(void)
237 {
238 	struct device_node *np;
239 
240 	mpc85xx_qe_par_io_init();
241 	mpc85xx_mds_reset_ucc_phys();
242 
243 	if (machine_is(p1021_mds)) {
244 
245 		struct ccsr_guts __iomem *guts;
246 
247 		np = of_find_node_by_name(NULL, "global-utilities");
248 		if (np) {
249 			guts = of_iomap(np, 0);
250 			if (!guts)
251 				pr_err("mpc85xx-rdb: could not map global utilities register\n");
252 			else{
253 			/* P1021 has pins muxed for QE and other functions. To
254 			 * enable QE UEC mode, we need to set bit QE0 for UCC1
255 			 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
256 			 * and QE12 for QE MII management signals in PMUXCR
257 			 * register.
258 			 */
259 				setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
260 						  MPC85xx_PMUXCR_QE(3) |
261 						  MPC85xx_PMUXCR_QE(9) |
262 						  MPC85xx_PMUXCR_QE(12));
263 				iounmap(guts);
264 			}
265 			of_node_put(np);
266 		}
267 
268 	}
269 }
270 
271 static void __init mpc85xx_mds_qeic_init(void)
272 {
273 	struct device_node *np;
274 
275 	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
276 	if (!of_device_is_available(np)) {
277 		of_node_put(np);
278 		return;
279 	}
280 
281 	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
282 	if (!np) {
283 		np = of_find_node_by_type(NULL, "qeic");
284 		if (!np)
285 			return;
286 	}
287 
288 	if (machine_is(p1021_mds))
289 		qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
290 				qe_ic_cascade_high_mpic);
291 	else
292 		qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
293 	of_node_put(np);
294 }
295 #else
296 static void __init mpc85xx_mds_qe_init(void) { }
297 static void __init mpc85xx_mds_qeic_init(void) { }
298 #endif	/* CONFIG_QUICC_ENGINE */
299 
300 static void __init mpc85xx_mds_setup_arch(void)
301 {
302 	if (ppc_md.progress)
303 		ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
304 
305 	mpc85xx_smp_init();
306 
307 	mpc85xx_mds_qe_init();
308 
309 	fsl_pci_assign_primary();
310 
311 	swiotlb_detect_4g();
312 }
313 
314 #if IS_BUILTIN(CONFIG_PHYLIB)
315 
316 static int __init board_fixups(void)
317 {
318 	char phy_id[20];
319 	char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
320 	struct device_node *mdio;
321 	struct resource res;
322 	int i;
323 
324 	for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
325 		mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
326 
327 		of_address_to_resource(mdio, 0, &res);
328 		snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
329 			(unsigned long long)res.start, 1);
330 
331 		phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
332 		phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
333 
334 		/* Register a workaround for errata */
335 		snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
336 			(unsigned long long)res.start, 7);
337 		phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
338 
339 		of_node_put(mdio);
340 	}
341 
342 	return 0;
343 }
344 
345 machine_arch_initcall(mpc8568_mds, board_fixups);
346 machine_arch_initcall(mpc8569_mds, board_fixups);
347 
348 #endif
349 
350 static int __init mpc85xx_publish_devices(void)
351 {
352 	return mpc85xx_common_publish_devices();
353 }
354 
355 machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
356 machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
357 machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);
358 
359 static void __init mpc85xx_mds_pic_init(void)
360 {
361 	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
362 			MPIC_SINGLE_DEST_CPU,
363 			0, 256, " OpenPIC  ");
364 	BUG_ON(mpic == NULL);
365 
366 	mpic_init(mpic);
367 	mpc85xx_mds_qeic_init();
368 }
369 
370 static int __init mpc85xx_mds_probe(void)
371 {
372 	return of_machine_is_compatible("MPC85xxMDS");
373 }
374 
375 define_machine(mpc8568_mds) {
376 	.name		= "MPC8568 MDS",
377 	.probe		= mpc85xx_mds_probe,
378 	.setup_arch	= mpc85xx_mds_setup_arch,
379 	.init_IRQ	= mpc85xx_mds_pic_init,
380 	.get_irq	= mpic_get_irq,
381 	.calibrate_decr	= generic_calibrate_decr,
382 	.progress	= udbg_progress,
383 #ifdef CONFIG_PCI
384 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
385 	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
386 #endif
387 };
388 
389 static int __init mpc8569_mds_probe(void)
390 {
391 	return of_machine_is_compatible("fsl,MPC8569EMDS");
392 }
393 
394 define_machine(mpc8569_mds) {
395 	.name		= "MPC8569 MDS",
396 	.probe		= mpc8569_mds_probe,
397 	.setup_arch	= mpc85xx_mds_setup_arch,
398 	.init_IRQ	= mpc85xx_mds_pic_init,
399 	.get_irq	= mpic_get_irq,
400 	.calibrate_decr	= generic_calibrate_decr,
401 	.progress	= udbg_progress,
402 #ifdef CONFIG_PCI
403 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
404 	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
405 #endif
406 };
407 
408 static int __init p1021_mds_probe(void)
409 {
410 	return of_machine_is_compatible("fsl,P1021MDS");
411 
412 }
413 
414 define_machine(p1021_mds) {
415 	.name		= "P1021 MDS",
416 	.probe		= p1021_mds_probe,
417 	.setup_arch	= mpc85xx_mds_setup_arch,
418 	.init_IRQ	= mpc85xx_mds_pic_init,
419 	.get_irq	= mpic_get_irq,
420 	.calibrate_decr	= generic_calibrate_decr,
421 	.progress	= udbg_progress,
422 #ifdef CONFIG_PCI
423 	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,
424 	.pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
425 #endif
426 };
427