1 /* 2 * MPC85xx DS Board Setup 3 * 4 * Author Xianghua Xiao (x.xiao@freescale.com) 5 * Roy Zang <tie-fei.zang@freescale.com> 6 * - Add PCI/PCI Exprees support 7 * Copyright 2007 Freescale Semiconductor Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #include <linux/stddef.h> 16 #include <linux/kernel.h> 17 #include <linux/pci.h> 18 #include <linux/kdev_t.h> 19 #include <linux/delay.h> 20 #include <linux/seq_file.h> 21 #include <linux/interrupt.h> 22 #include <linux/of_platform.h> 23 #include <linux/memblock.h> 24 25 #include <asm/time.h> 26 #include <asm/machdep.h> 27 #include <asm/pci-bridge.h> 28 #include <mm/mmu_decl.h> 29 #include <asm/prom.h> 30 #include <asm/udbg.h> 31 #include <asm/mpic.h> 32 #include <asm/i8259.h> 33 #include <asm/swiotlb.h> 34 35 #include <sysdev/fsl_soc.h> 36 #include <sysdev/fsl_pci.h> 37 #include "smp.h" 38 39 #include "mpc85xx.h" 40 41 #undef DEBUG 42 43 #ifdef DEBUG 44 #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) 45 #else 46 #define DBG(fmt, args...) 47 #endif 48 49 #ifdef CONFIG_PPC_I8259 50 static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) 51 { 52 struct irq_chip *chip = irq_desc_get_chip(desc); 53 unsigned int cascade_irq = i8259_irq(); 54 55 if (cascade_irq != NO_IRQ) { 56 generic_handle_irq(cascade_irq); 57 } 58 chip->irq_eoi(&desc->irq_data); 59 } 60 #endif /* CONFIG_PPC_I8259 */ 61 62 void __init mpc85xx_ds_pic_init(void) 63 { 64 struct mpic *mpic; 65 #ifdef CONFIG_PPC_I8259 66 struct device_node *np; 67 struct device_node *cascade_node = NULL; 68 int cascade_irq; 69 #endif 70 unsigned long root = of_get_flat_dt_root(); 71 72 if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) { 73 mpic = mpic_alloc(NULL, 0, 74 MPIC_NO_RESET | 75 MPIC_BIG_ENDIAN | 76 MPIC_SINGLE_DEST_CPU, 77 0, 256, " OpenPIC "); 78 } else { 79 mpic = mpic_alloc(NULL, 0, 80 MPIC_BIG_ENDIAN | 81 MPIC_SINGLE_DEST_CPU, 82 0, 256, " OpenPIC "); 83 } 84 85 BUG_ON(mpic == NULL); 86 mpic_init(mpic); 87 88 #ifdef CONFIG_PPC_I8259 89 /* Initialize the i8259 controller */ 90 for_each_node_by_type(np, "interrupt-controller") 91 if (of_device_is_compatible(np, "chrp,iic")) { 92 cascade_node = np; 93 break; 94 } 95 96 if (cascade_node == NULL) { 97 printk(KERN_DEBUG "Could not find i8259 PIC\n"); 98 return; 99 } 100 101 cascade_irq = irq_of_parse_and_map(cascade_node, 0); 102 if (cascade_irq == NO_IRQ) { 103 printk(KERN_ERR "Failed to map cascade interrupt\n"); 104 return; 105 } 106 107 DBG("mpc85xxds: cascade mapped to irq %d\n", cascade_irq); 108 109 i8259_init(cascade_node, 0); 110 of_node_put(cascade_node); 111 112 irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade); 113 #endif /* CONFIG_PPC_I8259 */ 114 } 115 116 #ifdef CONFIG_PCI 117 static int primary_phb_addr; 118 extern int uli_exclude_device(struct pci_controller *hose, 119 u_char bus, u_char devfn); 120 121 static int mpc85xx_exclude_device(struct pci_controller *hose, 122 u_char bus, u_char devfn) 123 { 124 struct device_node* node; 125 struct resource rsrc; 126 127 node = hose->dn; 128 of_address_to_resource(node, 0, &rsrc); 129 130 if ((rsrc.start & 0xfffff) == primary_phb_addr) { 131 return uli_exclude_device(hose, bus, devfn); 132 } 133 134 return PCIBIOS_SUCCESSFUL; 135 } 136 #endif /* CONFIG_PCI */ 137 138 /* 139 * Setup the architecture 140 */ 141 static void __init mpc85xx_ds_setup_arch(void) 142 { 143 #ifdef CONFIG_PCI 144 struct device_node *np; 145 struct pci_controller *hose; 146 #endif 147 dma_addr_t max = 0xffffffff; 148 149 if (ppc_md.progress) 150 ppc_md.progress("mpc85xx_ds_setup_arch()", 0); 151 152 #ifdef CONFIG_PCI 153 for_each_node_by_type(np, "pci") { 154 if (of_device_is_compatible(np, "fsl,mpc8540-pci") || 155 of_device_is_compatible(np, "fsl,mpc8548-pcie") || 156 of_device_is_compatible(np, "fsl,p2020-pcie")) { 157 struct resource rsrc; 158 of_address_to_resource(np, 0, &rsrc); 159 if ((rsrc.start & 0xfffff) == primary_phb_addr) 160 fsl_add_bridge(np, 1); 161 else 162 fsl_add_bridge(np, 0); 163 164 hose = pci_find_hose_for_OF_device(np); 165 max = min(max, hose->dma_window_base_cur + 166 hose->dma_window_size); 167 } 168 } 169 170 ppc_md.pci_exclude_device = mpc85xx_exclude_device; 171 #endif 172 173 mpc85xx_smp_init(); 174 175 #ifdef CONFIG_SWIOTLB 176 if (memblock_end_of_DRAM() > max) { 177 ppc_swiotlb_enable = 1; 178 set_pci_dma_ops(&swiotlb_dma_ops); 179 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb; 180 } 181 #endif 182 183 printk("MPC85xx DS board from Freescale Semiconductor\n"); 184 } 185 186 /* 187 * Called very early, device-tree isn't unflattened 188 */ 189 static int __init mpc8544_ds_probe(void) 190 { 191 unsigned long root = of_get_flat_dt_root(); 192 193 if (of_flat_dt_is_compatible(root, "MPC8544DS")) { 194 #ifdef CONFIG_PCI 195 primary_phb_addr = 0xb000; 196 #endif 197 return 1; 198 } 199 200 return 0; 201 } 202 203 machine_device_initcall(mpc8544_ds, mpc85xx_common_publish_devices); 204 machine_device_initcall(mpc8572_ds, mpc85xx_common_publish_devices); 205 machine_device_initcall(p2020_ds, mpc85xx_common_publish_devices); 206 207 machine_arch_initcall(mpc8544_ds, swiotlb_setup_bus_notifier); 208 machine_arch_initcall(mpc8572_ds, swiotlb_setup_bus_notifier); 209 machine_arch_initcall(p2020_ds, swiotlb_setup_bus_notifier); 210 211 /* 212 * Called very early, device-tree isn't unflattened 213 */ 214 static int __init mpc8572_ds_probe(void) 215 { 216 unsigned long root = of_get_flat_dt_root(); 217 218 if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS")) { 219 #ifdef CONFIG_PCI 220 primary_phb_addr = 0x8000; 221 #endif 222 return 1; 223 } 224 225 return 0; 226 } 227 228 /* 229 * Called very early, device-tree isn't unflattened 230 */ 231 static int __init p2020_ds_probe(void) 232 { 233 unsigned long root = of_get_flat_dt_root(); 234 235 if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) { 236 #ifdef CONFIG_PCI 237 primary_phb_addr = 0x9000; 238 #endif 239 return 1; 240 } 241 242 return 0; 243 } 244 245 define_machine(mpc8544_ds) { 246 .name = "MPC8544 DS", 247 .probe = mpc8544_ds_probe, 248 .setup_arch = mpc85xx_ds_setup_arch, 249 .init_IRQ = mpc85xx_ds_pic_init, 250 #ifdef CONFIG_PCI 251 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 252 #endif 253 .get_irq = mpic_get_irq, 254 .restart = fsl_rstcr_restart, 255 .calibrate_decr = generic_calibrate_decr, 256 .progress = udbg_progress, 257 }; 258 259 define_machine(mpc8572_ds) { 260 .name = "MPC8572 DS", 261 .probe = mpc8572_ds_probe, 262 .setup_arch = mpc85xx_ds_setup_arch, 263 .init_IRQ = mpc85xx_ds_pic_init, 264 #ifdef CONFIG_PCI 265 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 266 #endif 267 .get_irq = mpic_get_irq, 268 .restart = fsl_rstcr_restart, 269 .calibrate_decr = generic_calibrate_decr, 270 .progress = udbg_progress, 271 }; 272 273 define_machine(p2020_ds) { 274 .name = "P2020 DS", 275 .probe = p2020_ds_probe, 276 .setup_arch = mpc85xx_ds_setup_arch, 277 .init_IRQ = mpc85xx_ds_pic_init, 278 #ifdef CONFIG_PCI 279 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 280 #endif 281 .get_irq = mpic_get_irq, 282 .restart = fsl_rstcr_restart, 283 .calibrate_decr = generic_calibrate_decr, 284 .progress = udbg_progress, 285 }; 286