1/* 2 * Enter and leave deep sleep state on MPC83xx 3 * 4 * Copyright (c) 2006-2008 Freescale Semiconductor, Inc. 5 * Author: Scott Wood <scottwood@freescale.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation. 10 */ 11 12#include <asm/page.h> 13#include <asm/ppc_asm.h> 14#include <asm/reg.h> 15#include <asm/asm-offsets.h> 16 17#define SS_MEMSAVE 0x00 /* First 8 bytes of RAM */ 18#define SS_HID 0x08 /* 3 HIDs */ 19#define SS_IABR 0x14 /* 2 IABRs */ 20#define SS_IBCR 0x1c 21#define SS_DABR 0x20 /* 2 DABRs */ 22#define SS_DBCR 0x28 23#define SS_SP 0x2c 24#define SS_SR 0x30 /* 16 segment registers */ 25#define SS_R2 0x70 26#define SS_MSR 0x74 27#define SS_SDR1 0x78 28#define SS_LR 0x7c 29#define SS_SPRG 0x80 /* 8 SPRGs */ 30#define SS_DBAT 0xa0 /* 8 DBATs */ 31#define SS_IBAT 0xe0 /* 8 IBATs */ 32#define SS_TB 0x120 33#define SS_CR 0x128 34#define SS_GPREG 0x12c /* r12-r31 */ 35#define STATE_SAVE_SIZE 0x17c 36 37 .section .data 38 .align 5 39 40mpc83xx_sleep_save_area: 41 .space STATE_SAVE_SIZE 42immrbase: 43 .long 0 44 45 .section .text 46 .align 5 47 48 /* r3 = physical address of IMMR */ 49_GLOBAL(mpc83xx_enter_deep_sleep) 50 lis r4, immrbase@ha 51 stw r3, immrbase@l(r4) 52 53 /* The first 2 words of memory are used to communicate with the 54 * bootloader, to tell it how to resume. 55 * 56 * The first word is the magic number 0xf5153ae5, and the second 57 * is the pointer to mpc83xx_deep_resume. 58 * 59 * The original content of these two words is saved in SS_MEMSAVE. 60 */ 61 62 lis r3, mpc83xx_sleep_save_area@h 63 ori r3, r3, mpc83xx_sleep_save_area@l 64 65 lis r4, KERNELBASE@h 66 lwz r5, 0(r4) 67 lwz r6, 4(r4) 68 69 stw r5, SS_MEMSAVE+0(r3) 70 stw r6, SS_MEMSAVE+4(r3) 71 72 mfspr r5, SPRN_HID0 73 mfspr r6, SPRN_HID1 74 mfspr r7, SPRN_HID2 75 76 stw r5, SS_HID+0(r3) 77 stw r6, SS_HID+4(r3) 78 stw r7, SS_HID+8(r3) 79 80 mfspr r4, SPRN_IABR 81 mfspr r5, SPRN_IABR2 82 mfspr r6, SPRN_IBCR 83 mfspr r7, SPRN_DABR 84 mfspr r8, SPRN_DABR2 85 mfspr r9, SPRN_DBCR 86 87 stw r4, SS_IABR+0(r3) 88 stw r5, SS_IABR+4(r3) 89 stw r6, SS_IBCR(r3) 90 stw r7, SS_DABR+0(r3) 91 stw r8, SS_DABR+4(r3) 92 stw r9, SS_DBCR(r3) 93 94 mfspr r4, SPRN_SPRG0 95 mfspr r5, SPRN_SPRG1 96 mfspr r6, SPRN_SPRG2 97 mfspr r7, SPRN_SPRG3 98 mfsdr1 r8 99 100 stw r4, SS_SPRG+0(r3) 101 stw r5, SS_SPRG+4(r3) 102 stw r6, SS_SPRG+8(r3) 103 stw r7, SS_SPRG+12(r3) 104 stw r8, SS_SDR1(r3) 105 106 mfspr r4, SPRN_SPRG4 107 mfspr r5, SPRN_SPRG5 108 mfspr r6, SPRN_SPRG6 109 mfspr r7, SPRN_SPRG7 110 111 stw r4, SS_SPRG+16(r3) 112 stw r5, SS_SPRG+20(r3) 113 stw r6, SS_SPRG+24(r3) 114 stw r7, SS_SPRG+28(r3) 115 116 mfspr r4, SPRN_DBAT0U 117 mfspr r5, SPRN_DBAT0L 118 mfspr r6, SPRN_DBAT1U 119 mfspr r7, SPRN_DBAT1L 120 121 stw r4, SS_DBAT+0x00(r3) 122 stw r5, SS_DBAT+0x04(r3) 123 stw r6, SS_DBAT+0x08(r3) 124 stw r7, SS_DBAT+0x0c(r3) 125 126 mfspr r4, SPRN_DBAT2U 127 mfspr r5, SPRN_DBAT2L 128 mfspr r6, SPRN_DBAT3U 129 mfspr r7, SPRN_DBAT3L 130 131 stw r4, SS_DBAT+0x10(r3) 132 stw r5, SS_DBAT+0x14(r3) 133 stw r6, SS_DBAT+0x18(r3) 134 stw r7, SS_DBAT+0x1c(r3) 135 136 mfspr r4, SPRN_DBAT4U 137 mfspr r5, SPRN_DBAT4L 138 mfspr r6, SPRN_DBAT5U 139 mfspr r7, SPRN_DBAT5L 140 141 stw r4, SS_DBAT+0x20(r3) 142 stw r5, SS_DBAT+0x24(r3) 143 stw r6, SS_DBAT+0x28(r3) 144 stw r7, SS_DBAT+0x2c(r3) 145 146 mfspr r4, SPRN_DBAT6U 147 mfspr r5, SPRN_DBAT6L 148 mfspr r6, SPRN_DBAT7U 149 mfspr r7, SPRN_DBAT7L 150 151 stw r4, SS_DBAT+0x30(r3) 152 stw r5, SS_DBAT+0x34(r3) 153 stw r6, SS_DBAT+0x38(r3) 154 stw r7, SS_DBAT+0x3c(r3) 155 156 mfspr r4, SPRN_IBAT0U 157 mfspr r5, SPRN_IBAT0L 158 mfspr r6, SPRN_IBAT1U 159 mfspr r7, SPRN_IBAT1L 160 161 stw r4, SS_IBAT+0x00(r3) 162 stw r5, SS_IBAT+0x04(r3) 163 stw r6, SS_IBAT+0x08(r3) 164 stw r7, SS_IBAT+0x0c(r3) 165 166 mfspr r4, SPRN_IBAT2U 167 mfspr r5, SPRN_IBAT2L 168 mfspr r6, SPRN_IBAT3U 169 mfspr r7, SPRN_IBAT3L 170 171 stw r4, SS_IBAT+0x10(r3) 172 stw r5, SS_IBAT+0x14(r3) 173 stw r6, SS_IBAT+0x18(r3) 174 stw r7, SS_IBAT+0x1c(r3) 175 176 mfspr r4, SPRN_IBAT4U 177 mfspr r5, SPRN_IBAT4L 178 mfspr r6, SPRN_IBAT5U 179 mfspr r7, SPRN_IBAT5L 180 181 stw r4, SS_IBAT+0x20(r3) 182 stw r5, SS_IBAT+0x24(r3) 183 stw r6, SS_IBAT+0x28(r3) 184 stw r7, SS_IBAT+0x2c(r3) 185 186 mfspr r4, SPRN_IBAT6U 187 mfspr r5, SPRN_IBAT6L 188 mfspr r6, SPRN_IBAT7U 189 mfspr r7, SPRN_IBAT7L 190 191 stw r4, SS_IBAT+0x30(r3) 192 stw r5, SS_IBAT+0x34(r3) 193 stw r6, SS_IBAT+0x38(r3) 194 stw r7, SS_IBAT+0x3c(r3) 195 196 mfmsr r4 197 mflr r5 198 mfcr r6 199 200 stw r4, SS_MSR(r3) 201 stw r5, SS_LR(r3) 202 stw r6, SS_CR(r3) 203 stw r1, SS_SP(r3) 204 stw r2, SS_R2(r3) 205 2061: mftbu r4 207 mftb r5 208 mftbu r6 209 cmpw r4, r6 210 bne 1b 211 212 stw r4, SS_TB+0(r3) 213 stw r5, SS_TB+4(r3) 214 215 stmw r12, SS_GPREG(r3) 216 217 li r4, 0 218 addi r6, r3, SS_SR-4 2191: mfsrin r5, r4 220 stwu r5, 4(r6) 221 addis r4, r4, 0x1000 222 cmpwi r4, 0 223 bne 1b 224 225 /* Disable machine checks and critical exceptions */ 226 mfmsr r4 227 rlwinm r4, r4, 0, ~MSR_CE 228 rlwinm r4, r4, 0, ~MSR_ME 229 mtmsr r4 230 isync 231 232#define TMP_VIRT_IMMR 0xf0000000 233#define DEFAULT_IMMR_VALUE 0xff400000 234#define IMMRBAR_BASE 0x0000 235 236 lis r4, immrbase@ha 237 lwz r4, immrbase@l(r4) 238 239 /* Use DBAT0 to address the current IMMR space */ 240 241 ori r4, r4, 0x002a 242 mtspr SPRN_DBAT0L, r4 243 lis r8, TMP_VIRT_IMMR@h 244 ori r4, r8, 0x001e /* 1 MByte accessible from Kernel Space only */ 245 mtspr SPRN_DBAT0U, r4 246 isync 247 248 /* Use DBAT1 to address the original IMMR space */ 249 250 lis r4, DEFAULT_IMMR_VALUE@h 251 ori r4, r4, 0x002a 252 mtspr SPRN_DBAT1L, r4 253 lis r9, (TMP_VIRT_IMMR + 0x01000000)@h 254 ori r4, r9, 0x001e /* 1 MByte accessible from Kernel Space only */ 255 mtspr SPRN_DBAT1U, r4 256 isync 257 258 /* Use DBAT2 to address the beginning of RAM. This isn't done 259 * using the normal virtual mapping, because with page debugging 260 * enabled it will be read-only. 261 */ 262 263 li r4, 0x0002 264 mtspr SPRN_DBAT2L, r4 265 lis r4, KERNELBASE@h 266 ori r4, r4, 0x001e /* 1 MByte accessible from Kernel Space only */ 267 mtspr SPRN_DBAT2U, r4 268 isync 269 270 /* Flush the cache with our BAT, as there will be TLB misses 271 * otherwise if page debugging is enabled, and these misses 272 * will disturb the PLRU algorithm. 273 */ 274 275 bl __flush_disable_L1 276 277 /* Keep the i-cache enabled, so the hack below for low-boot 278 * flash will work. 279 */ 280 mfspr r3, SPRN_HID0 281 ori r3, r3, HID0_ICE 282 mtspr SPRN_HID0, r3 283 isync 284 285 lis r6, 0xf515 286 ori r6, r6, 0x3ae5 287 288 lis r7, mpc83xx_deep_resume@h 289 ori r7, r7, mpc83xx_deep_resume@l 290 tophys(r7, r7) 291 292 lis r5, KERNELBASE@h 293 stw r6, 0(r5) 294 stw r7, 4(r5) 295 296 /* Reset BARs */ 297 298 li r4, 0 299 stw r4, 0x0024(r8) 300 stw r4, 0x002c(r8) 301 stw r4, 0x0034(r8) 302 stw r4, 0x003c(r8) 303 stw r4, 0x0064(r8) 304 stw r4, 0x006c(r8) 305 306 /* Rev 1 of the 8313 has problems with wakeup events that are 307 * pending during the transition to deep sleep state (such as if 308 * the PCI host sets the state to D3 and then D0 in rapid 309 * succession). This check shrinks the race window somewhat. 310 * 311 * See erratum PCI23, though the problem is not limited 312 * to PCI. 313 */ 314 315 lwz r3, 0x0b04(r8) 316 andi. r3, r3, 1 317 bne- mpc83xx_deep_resume 318 319 /* Move IMMR back to the default location, following the 320 * procedure specified in the MPC8313 manual. 321 */ 322 lwz r4, IMMRBAR_BASE(r8) 323 isync 324 lis r4, DEFAULT_IMMR_VALUE@h 325 stw r4, IMMRBAR_BASE(r8) 326 lis r4, KERNELBASE@h 327 lwz r4, 0(r4) 328 isync 329 lwz r4, IMMRBAR_BASE(r9) 330 mr r8, r9 331 isync 332 333 /* Check the Reset Configuration Word to see whether flash needs 334 * to be mapped at a low address or a high address. 335 */ 336 337 lwz r4, 0x0904(r8) 338 andis. r4, r4, 0x0400 339 li r4, 0 340 beq boot_low 341 lis r4, 0xff80 342boot_low: 343 stw r4, 0x0020(r8) 344 lis r7, 0x8000 345 ori r7, r7, 0x0016 346 347 mfspr r5, SPRN_HID0 348 rlwinm r5, r5, 0, ~(HID0_DOZE | HID0_NAP) 349 oris r5, r5, HID0_SLEEP@h 350 mtspr SPRN_HID0, r5 351 isync 352 353 mfmsr r5 354 oris r5, r5, MSR_POW@h 355 356 /* Enable the flash mapping at the appropriate address. This 357 * mapping will override the RAM mapping if booting low, so there's 358 * no need to disable the latter. This must be done inside the same 359 * cache line as setting MSR_POW, so that no instruction fetches 360 * from RAM happen after the flash mapping is turned on. 361 */ 362 363 .align 5 364 stw r7, 0x0024(r8) 365 sync 366 isync 367 mtmsr r5 368 isync 3691: b 1b 370 371mpc83xx_deep_resume: 372 lis r4, 1f@h 373 ori r4, r4, 1f@l 374 tophys(r4, r4) 375 mtsrr0 r4 376 377 mfmsr r4 378 rlwinm r4, r4, 0, ~(MSR_IR | MSR_DR) 379 mtsrr1 r4 380 381 rfi 382 3831: tlbia 384 bl __inval_enable_L1 385 386 lis r3, mpc83xx_sleep_save_area@h 387 ori r3, r3, mpc83xx_sleep_save_area@l 388 tophys(r3, r3) 389 390 lwz r5, SS_MEMSAVE+0(r3) 391 lwz r6, SS_MEMSAVE+4(r3) 392 393 stw r5, 0(0) 394 stw r6, 4(0) 395 396 lwz r5, SS_HID+0(r3) 397 lwz r6, SS_HID+4(r3) 398 lwz r7, SS_HID+8(r3) 399 400 mtspr SPRN_HID0, r5 401 mtspr SPRN_HID1, r6 402 mtspr SPRN_HID2, r7 403 404 lwz r4, SS_IABR+0(r3) 405 lwz r5, SS_IABR+4(r3) 406 lwz r6, SS_IBCR(r3) 407 lwz r7, SS_DABR+0(r3) 408 lwz r8, SS_DABR+4(r3) 409 lwz r9, SS_DBCR(r3) 410 411 mtspr SPRN_IABR, r4 412 mtspr SPRN_IABR2, r5 413 mtspr SPRN_IBCR, r6 414 mtspr SPRN_DABR, r7 415 mtspr SPRN_DABR2, r8 416 mtspr SPRN_DBCR, r9 417 418 li r4, 0 419 addi r6, r3, SS_SR-4 4201: lwzu r5, 4(r6) 421 mtsrin r5, r4 422 addis r4, r4, 0x1000 423 cmpwi r4, 0 424 bne 1b 425 426 lwz r4, SS_DBAT+0x00(r3) 427 lwz r5, SS_DBAT+0x04(r3) 428 lwz r6, SS_DBAT+0x08(r3) 429 lwz r7, SS_DBAT+0x0c(r3) 430 431 mtspr SPRN_DBAT0U, r4 432 mtspr SPRN_DBAT0L, r5 433 mtspr SPRN_DBAT1U, r6 434 mtspr SPRN_DBAT1L, r7 435 436 lwz r4, SS_DBAT+0x10(r3) 437 lwz r5, SS_DBAT+0x14(r3) 438 lwz r6, SS_DBAT+0x18(r3) 439 lwz r7, SS_DBAT+0x1c(r3) 440 441 mtspr SPRN_DBAT2U, r4 442 mtspr SPRN_DBAT2L, r5 443 mtspr SPRN_DBAT3U, r6 444 mtspr SPRN_DBAT3L, r7 445 446 lwz r4, SS_DBAT+0x20(r3) 447 lwz r5, SS_DBAT+0x24(r3) 448 lwz r6, SS_DBAT+0x28(r3) 449 lwz r7, SS_DBAT+0x2c(r3) 450 451 mtspr SPRN_DBAT4U, r4 452 mtspr SPRN_DBAT4L, r5 453 mtspr SPRN_DBAT5U, r6 454 mtspr SPRN_DBAT5L, r7 455 456 lwz r4, SS_DBAT+0x30(r3) 457 lwz r5, SS_DBAT+0x34(r3) 458 lwz r6, SS_DBAT+0x38(r3) 459 lwz r7, SS_DBAT+0x3c(r3) 460 461 mtspr SPRN_DBAT6U, r4 462 mtspr SPRN_DBAT6L, r5 463 mtspr SPRN_DBAT7U, r6 464 mtspr SPRN_DBAT7L, r7 465 466 lwz r4, SS_IBAT+0x00(r3) 467 lwz r5, SS_IBAT+0x04(r3) 468 lwz r6, SS_IBAT+0x08(r3) 469 lwz r7, SS_IBAT+0x0c(r3) 470 471 mtspr SPRN_IBAT0U, r4 472 mtspr SPRN_IBAT0L, r5 473 mtspr SPRN_IBAT1U, r6 474 mtspr SPRN_IBAT1L, r7 475 476 lwz r4, SS_IBAT+0x10(r3) 477 lwz r5, SS_IBAT+0x14(r3) 478 lwz r6, SS_IBAT+0x18(r3) 479 lwz r7, SS_IBAT+0x1c(r3) 480 481 mtspr SPRN_IBAT2U, r4 482 mtspr SPRN_IBAT2L, r5 483 mtspr SPRN_IBAT3U, r6 484 mtspr SPRN_IBAT3L, r7 485 486 lwz r4, SS_IBAT+0x20(r3) 487 lwz r5, SS_IBAT+0x24(r3) 488 lwz r6, SS_IBAT+0x28(r3) 489 lwz r7, SS_IBAT+0x2c(r3) 490 491 mtspr SPRN_IBAT4U, r4 492 mtspr SPRN_IBAT4L, r5 493 mtspr SPRN_IBAT5U, r6 494 mtspr SPRN_IBAT5L, r7 495 496 lwz r4, SS_IBAT+0x30(r3) 497 lwz r5, SS_IBAT+0x34(r3) 498 lwz r6, SS_IBAT+0x38(r3) 499 lwz r7, SS_IBAT+0x3c(r3) 500 501 mtspr SPRN_IBAT6U, r4 502 mtspr SPRN_IBAT6L, r5 503 mtspr SPRN_IBAT7U, r6 504 mtspr SPRN_IBAT7L, r7 505 506 lwz r4, SS_SPRG+16(r3) 507 lwz r5, SS_SPRG+20(r3) 508 lwz r6, SS_SPRG+24(r3) 509 lwz r7, SS_SPRG+28(r3) 510 511 mtspr SPRN_SPRG4, r4 512 mtspr SPRN_SPRG5, r5 513 mtspr SPRN_SPRG6, r6 514 mtspr SPRN_SPRG7, r7 515 516 lwz r4, SS_SPRG+0(r3) 517 lwz r5, SS_SPRG+4(r3) 518 lwz r6, SS_SPRG+8(r3) 519 lwz r7, SS_SPRG+12(r3) 520 lwz r8, SS_SDR1(r3) 521 522 mtspr SPRN_SPRG0, r4 523 mtspr SPRN_SPRG1, r5 524 mtspr SPRN_SPRG2, r6 525 mtspr SPRN_SPRG3, r7 526 mtsdr1 r8 527 528 lwz r4, SS_MSR(r3) 529 lwz r5, SS_LR(r3) 530 lwz r6, SS_CR(r3) 531 lwz r1, SS_SP(r3) 532 lwz r2, SS_R2(r3) 533 534 mtsrr1 r4 535 mtsrr0 r5 536 mtcr r6 537 538 li r4, 0 539 mtspr SPRN_TBWL, r4 540 541 lwz r4, SS_TB+0(r3) 542 lwz r5, SS_TB+4(r3) 543 544 mtspr SPRN_TBWU, r4 545 mtspr SPRN_TBWL, r5 546 547 lmw r12, SS_GPREG(r3) 548 549 /* Kick decrementer */ 550 li r0, 1 551 mtdec r0 552 553 rfi 554