xref: /openbmc/linux/arch/powerpc/platforms/83xx/misc.c (revision aa5b395b)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * misc setup functions for MPC83xx
4  *
5  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
6  */
7 
8 #include <linux/stddef.h>
9 #include <linux/kernel.h>
10 #include <linux/of_platform.h>
11 #include <linux/pci.h>
12 
13 #include <asm/debug.h>
14 #include <asm/io.h>
15 #include <asm/hw_irq.h>
16 #include <asm/ipic.h>
17 #include <soc/fsl/qe/qe_ic.h>
18 #include <sysdev/fsl_soc.h>
19 #include <sysdev/fsl_pci.h>
20 
21 #include <mm/mmu_decl.h>
22 
23 #include "mpc83xx.h"
24 
25 static __be32 __iomem *restart_reg_base;
26 
27 static int __init mpc83xx_restart_init(void)
28 {
29 	/* map reset restart_reg_baseister space */
30 	restart_reg_base = ioremap(get_immrbase() + 0x900, 0xff);
31 
32 	return 0;
33 }
34 
35 arch_initcall(mpc83xx_restart_init);
36 
37 void __noreturn mpc83xx_restart(char *cmd)
38 {
39 #define RST_OFFSET	0x00000900
40 #define RST_PROT_REG	0x00000018
41 #define RST_CTRL_REG	0x0000001c
42 
43 	local_irq_disable();
44 
45 	if (restart_reg_base) {
46 		/* enable software reset "RSTE" */
47 		out_be32(restart_reg_base + (RST_PROT_REG >> 2), 0x52535445);
48 
49 		/* set software hard reset */
50 		out_be32(restart_reg_base + (RST_CTRL_REG >> 2), 0x2);
51 	} else {
52 		printk (KERN_EMERG "Error: Restart registers not mapped, spinning!\n");
53 	}
54 
55 	for (;;) ;
56 }
57 
58 long __init mpc83xx_time_init(void)
59 {
60 #define SPCR_OFFSET	0x00000110
61 #define SPCR_TBEN	0x00400000
62 	__be32 __iomem *spcr = ioremap(get_immrbase() + SPCR_OFFSET, 4);
63 	__be32 tmp;
64 
65 	tmp = in_be32(spcr);
66 	out_be32(spcr, tmp | SPCR_TBEN);
67 
68 	iounmap(spcr);
69 
70 	return 0;
71 }
72 
73 void __init mpc83xx_ipic_init_IRQ(void)
74 {
75 	struct device_node *np;
76 
77 	/* looking for fsl,pq2pro-pic which is asl compatible with fsl,ipic */
78 	np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
79 	if (!np)
80 		np = of_find_node_by_type(NULL, "ipic");
81 	if (!np)
82 		return;
83 
84 	ipic_init(np, 0);
85 
86 	of_node_put(np);
87 
88 	/* Initialize the default interrupt mapping priorities,
89 	 * in case the boot rom changed something on us.
90 	 */
91 	ipic_set_default_priority();
92 }
93 
94 #ifdef CONFIG_QUICC_ENGINE
95 void __init mpc83xx_qe_init_IRQ(void)
96 {
97 	struct device_node *np;
98 
99 	np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
100 	if (!np) {
101 		np = of_find_node_by_type(NULL, "qeic");
102 		if (!np)
103 			return;
104 	}
105 	qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
106 	of_node_put(np);
107 }
108 
109 void __init mpc83xx_ipic_and_qe_init_IRQ(void)
110 {
111 	mpc83xx_ipic_init_IRQ();
112 	mpc83xx_qe_init_IRQ();
113 }
114 #endif /* CONFIG_QUICC_ENGINE */
115 
116 static const struct of_device_id of_bus_ids[] __initconst = {
117 	{ .type = "soc", },
118 	{ .compatible = "soc", },
119 	{ .compatible = "simple-bus" },
120 	{ .compatible = "gianfar" },
121 	{ .compatible = "gpio-leds", },
122 	{ .type = "qe", },
123 	{ .compatible = "fsl,qe", },
124 	{},
125 };
126 
127 int __init mpc83xx_declare_of_platform_devices(void)
128 {
129 	of_platform_bus_probe(NULL, of_bus_ids, NULL);
130 	return 0;
131 }
132 
133 #ifdef CONFIG_PCI
134 void __init mpc83xx_setup_pci(void)
135 {
136 	struct device_node *np;
137 
138 	for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
139 		mpc83xx_add_bridge(np);
140 	for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
141 		mpc83xx_add_bridge(np);
142 }
143 #endif
144 
145 void __init mpc83xx_setup_arch(void)
146 {
147 	if (ppc_md.progress)
148 		ppc_md.progress("mpc83xx_setup_arch()", 0);
149 
150 	if (!__map_without_bats) {
151 		phys_addr_t immrbase = get_immrbase();
152 		int immrsize = IS_ALIGNED(immrbase, SZ_2M) ? SZ_2M : SZ_1M;
153 		unsigned long va = fix_to_virt(FIX_IMMR_BASE);
154 
155 		setbat(-1, va, immrbase, immrsize, PAGE_KERNEL_NCG);
156 		update_bats();
157 	}
158 
159 	mpc83xx_setup_pci();
160 }
161 
162 int machine_check_83xx(struct pt_regs *regs)
163 {
164 	u32 mask = 1 << (31 - IPIC_MCP_WDT);
165 
166 	if (!(regs->msr & SRR1_MCE_MCP) || !(ipic_get_mcp_status() & mask))
167 		return machine_check_generic(regs);
168 	ipic_clear_mcp_status(mask);
169 
170 	if (debugger_fault_handler(regs))
171 		return 1;
172 
173 	die("Watchdog NMI Reset", regs, 0);
174 
175 	return 1;
176 }
177