1e00c5498SScott Wood /* 2e00c5498SScott Wood * Common PowerQUICC II code. 3e00c5498SScott Wood * 4e00c5498SScott Wood * Author: Scott Wood <scottwood@freescale.com> 5e00c5498SScott Wood * Copyright (c) 2007 Freescale Semiconductor 6e00c5498SScott Wood * 7e00c5498SScott Wood * Based on code by Vitaly Bordug <vbordug@ru.mvista.com> 8e00c5498SScott Wood * pq2_restart fix by Wade Farnsworth <wfarnsworth@mvista.com> 9e00c5498SScott Wood * Copyright (c) 2006 MontaVista Software, Inc. 10e00c5498SScott Wood * 11e00c5498SScott Wood * This program is free software; you can redistribute it and/or modify it 12e00c5498SScott Wood * under the terms of the GNU General Public License as published by the 13e00c5498SScott Wood * Free Software Foundation; either version 2 of the License, or (at your 14e00c5498SScott Wood * option) any later version. 15e00c5498SScott Wood */ 16e00c5498SScott Wood 17e00c5498SScott Wood #include <asm/cpm2.h> 18e00c5498SScott Wood #include <asm/io.h> 19e00c5498SScott Wood #include <asm/pci-bridge.h> 20e00c5498SScott Wood #include <asm/system.h> 21e00c5498SScott Wood 22e00c5498SScott Wood #include <platforms/82xx/pq2.h> 23e00c5498SScott Wood 24e00c5498SScott Wood #define RMR_CSRE 0x00000001 25e00c5498SScott Wood 26e00c5498SScott Wood void pq2_restart(char *cmd) 27e00c5498SScott Wood { 28e00c5498SScott Wood local_irq_disable(); 29e00c5498SScott Wood setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE); 30e00c5498SScott Wood 31e00c5498SScott Wood /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */ 32e00c5498SScott Wood mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR)); 33e00c5498SScott Wood in_8(&cpm2_immr->im_clkrst.res[0]); 34e00c5498SScott Wood 35e00c5498SScott Wood panic("Restart failed\n"); 36e00c5498SScott Wood } 37e00c5498SScott Wood 38e00c5498SScott Wood #ifdef CONFIG_PCI 39e00c5498SScott Wood static int pq2_pci_exclude_device(struct pci_controller *hose, 40e00c5498SScott Wood u_char bus, u8 devfn) 41e00c5498SScott Wood { 42e00c5498SScott Wood if (bus == 0 && PCI_SLOT(devfn) == 0) 43e00c5498SScott Wood return PCIBIOS_DEVICE_NOT_FOUND; 44e00c5498SScott Wood else 45e00c5498SScott Wood return PCIBIOS_SUCCESSFUL; 46e00c5498SScott Wood } 47e00c5498SScott Wood 48e00c5498SScott Wood static void __init pq2_pci_add_bridge(struct device_node *np) 49e00c5498SScott Wood { 50e00c5498SScott Wood struct pci_controller *hose; 51e00c5498SScott Wood struct resource r; 52e00c5498SScott Wood 53e00c5498SScott Wood if (of_address_to_resource(np, 0, &r) || r.end - r.start < 0x10b) 54e00c5498SScott Wood goto err; 55e00c5498SScott Wood 56e00c5498SScott Wood pci_assign_all_buses = 1; 57e00c5498SScott Wood 58e00c5498SScott Wood hose = pcibios_alloc_controller(np); 59e00c5498SScott Wood if (!hose) 60e00c5498SScott Wood return; 61e00c5498SScott Wood 62e00c5498SScott Wood hose->arch_data = np; 63e00c5498SScott Wood 64e00c5498SScott Wood setup_indirect_pci(hose, r.start + 0x100, r.start + 0x104, 0); 65e00c5498SScott Wood pci_process_bridge_OF_ranges(hose, np, 1); 66e00c5498SScott Wood 67e00c5498SScott Wood return; 68e00c5498SScott Wood 69e00c5498SScott Wood err: 70e00c5498SScott Wood printk(KERN_ERR "No valid PCI reg property in device tree\n"); 71e00c5498SScott Wood } 72e00c5498SScott Wood 73e00c5498SScott Wood void __init pq2_init_pci(void) 74e00c5498SScott Wood { 75e00c5498SScott Wood struct device_node *np = NULL; 76e00c5498SScott Wood 77e00c5498SScott Wood ppc_md.pci_exclude_device = pq2_pci_exclude_device; 78e00c5498SScott Wood 79e00c5498SScott Wood while ((np = of_find_compatible_node(np, NULL, "fsl,pq2-pci"))) 80e00c5498SScott Wood pq2_pci_add_bridge(np); 81e00c5498SScott Wood } 82e00c5498SScott Wood #endif 83