1 /* 2 * Embedded Planet EP8248E support 3 * 4 * Copyright 2007 Freescale Semiconductor, Inc. 5 * Author: Scott Wood <scottwood@freescale.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/fsl_devices.h> 16 #include <linux/mdio-bitbang.h> 17 #include <linux/of_mdio.h> 18 #include <linux/of_platform.h> 19 20 #include <asm/io.h> 21 #include <asm/cpm2.h> 22 #include <asm/udbg.h> 23 #include <asm/machdep.h> 24 #include <asm/time.h> 25 #include <asm/mpc8260.h> 26 #include <asm/prom.h> 27 28 #include <sysdev/fsl_soc.h> 29 #include <sysdev/cpm2_pic.h> 30 31 #include "pq2.h" 32 33 static u8 __iomem *ep8248e_bcsr; 34 static struct device_node *ep8248e_bcsr_node; 35 36 #define BCSR7_SCC2_ENABLE 0x10 37 38 #define BCSR8_PHY1_ENABLE 0x80 39 #define BCSR8_PHY1_POWER 0x40 40 #define BCSR8_PHY2_ENABLE 0x20 41 #define BCSR8_PHY2_POWER 0x10 42 #define BCSR8_MDIO_READ 0x04 43 #define BCSR8_MDIO_CLOCK 0x02 44 #define BCSR8_MDIO_DATA 0x01 45 46 #define BCSR9_USB_ENABLE 0x80 47 #define BCSR9_USB_POWER 0x40 48 #define BCSR9_USB_HOST 0x20 49 #define BCSR9_USB_FULL_SPEED_TARGET 0x10 50 51 static void __init ep8248e_pic_init(void) 52 { 53 struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic"); 54 if (!np) { 55 printk(KERN_ERR "PIC init: can not find cpm-pic node\n"); 56 return; 57 } 58 59 cpm2_pic_init(np); 60 of_node_put(np); 61 } 62 63 static void ep8248e_set_mdc(struct mdiobb_ctrl *ctrl, int level) 64 { 65 if (level) 66 setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK); 67 else 68 clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK); 69 70 /* Read back to flush the write. */ 71 in_8(&ep8248e_bcsr[8]); 72 } 73 74 static void ep8248e_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 75 { 76 if (output) 77 clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ); 78 else 79 setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ); 80 81 /* Read back to flush the write. */ 82 in_8(&ep8248e_bcsr[8]); 83 } 84 85 static void ep8248e_set_mdio_data(struct mdiobb_ctrl *ctrl, int data) 86 { 87 if (data) 88 setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA); 89 else 90 clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA); 91 92 /* Read back to flush the write. */ 93 in_8(&ep8248e_bcsr[8]); 94 } 95 96 static int ep8248e_get_mdio_data(struct mdiobb_ctrl *ctrl) 97 { 98 return in_8(&ep8248e_bcsr[8]) & BCSR8_MDIO_DATA; 99 } 100 101 static const struct mdiobb_ops ep8248e_mdio_ops = { 102 .set_mdc = ep8248e_set_mdc, 103 .set_mdio_dir = ep8248e_set_mdio_dir, 104 .set_mdio_data = ep8248e_set_mdio_data, 105 .get_mdio_data = ep8248e_get_mdio_data, 106 .owner = THIS_MODULE, 107 }; 108 109 static struct mdiobb_ctrl ep8248e_mdio_ctrl = { 110 .ops = &ep8248e_mdio_ops, 111 }; 112 113 static int __devinit ep8248e_mdio_probe(struct of_device *ofdev, 114 const struct of_device_id *match) 115 { 116 struct mii_bus *bus; 117 struct resource res; 118 struct device_node *node; 119 int ret; 120 121 node = of_get_parent(ofdev->node); 122 of_node_put(node); 123 if (node != ep8248e_bcsr_node) 124 return -ENODEV; 125 126 ret = of_address_to_resource(ofdev->node, 0, &res); 127 if (ret) 128 return ret; 129 130 bus = alloc_mdio_bitbang(&ep8248e_mdio_ctrl); 131 if (!bus) 132 return -ENOMEM; 133 134 bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 135 136 bus->name = "ep8248e-mdio-bitbang"; 137 bus->parent = &ofdev->dev; 138 snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start); 139 140 return of_mdiobus_register(bus, ofdev->node); 141 } 142 143 static int ep8248e_mdio_remove(struct of_device *ofdev) 144 { 145 BUG(); 146 return 0; 147 } 148 149 static const struct of_device_id ep8248e_mdio_match[] = { 150 { 151 .compatible = "fsl,ep8248e-mdio-bitbang", 152 }, 153 {}, 154 }; 155 156 static struct of_platform_driver ep8248e_mdio_driver = { 157 .driver = { 158 .name = "ep8248e-mdio-bitbang", 159 }, 160 .match_table = ep8248e_mdio_match, 161 .probe = ep8248e_mdio_probe, 162 .remove = ep8248e_mdio_remove, 163 }; 164 165 struct cpm_pin { 166 int port, pin, flags; 167 }; 168 169 static __initdata struct cpm_pin ep8248e_pins[] = { 170 /* SMC1 */ 171 {2, 4, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 172 {2, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 173 174 /* SCC1 */ 175 {2, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 176 {2, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 177 {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 178 {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 179 {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 180 181 /* FCC1 */ 182 {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 183 {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 184 {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 185 {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 186 {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 187 {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 188 {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 189 {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 190 {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 191 {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 192 {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 193 {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 194 {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 195 {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 196 {2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 197 {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 198 199 /* FCC2 */ 200 {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 201 {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 202 {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 203 {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 204 {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 205 {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 206 {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 207 {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 208 {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 209 {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 210 {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 211 {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 212 {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 213 {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 214 {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 215 {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 216 217 /* I2C */ 218 {4, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 219 {4, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 220 221 /* USB */ 222 {2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 223 {2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 224 {2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 225 {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 226 {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 227 {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 228 {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 229 }; 230 231 static void __init init_ioports(void) 232 { 233 int i; 234 235 for (i = 0; i < ARRAY_SIZE(ep8248e_pins); i++) { 236 const struct cpm_pin *pin = &ep8248e_pins[i]; 237 cpm2_set_pin(pin->port, pin->pin, pin->flags); 238 } 239 240 cpm2_smc_clk_setup(CPM_CLK_SMC1, CPM_BRG7); 241 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX); 242 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX); 243 cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX); /* USB */ 244 cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX); 245 cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX); 246 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX); 247 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX); 248 } 249 250 static void __init ep8248e_setup_arch(void) 251 { 252 if (ppc_md.progress) 253 ppc_md.progress("ep8248e_setup_arch()", 0); 254 255 cpm2_reset(); 256 257 /* When this is set, snooping CPM DMA from RAM causes 258 * machine checks. See erratum SIU18. 259 */ 260 clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP); 261 262 ep8248e_bcsr_node = 263 of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr"); 264 if (!ep8248e_bcsr_node) { 265 printk(KERN_ERR "No bcsr in device tree\n"); 266 return; 267 } 268 269 ep8248e_bcsr = of_iomap(ep8248e_bcsr_node, 0); 270 if (!ep8248e_bcsr) { 271 printk(KERN_ERR "Cannot map BCSR registers\n"); 272 of_node_put(ep8248e_bcsr_node); 273 ep8248e_bcsr_node = NULL; 274 return; 275 } 276 277 setbits8(&ep8248e_bcsr[7], BCSR7_SCC2_ENABLE); 278 setbits8(&ep8248e_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER | 279 BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER); 280 281 init_ioports(); 282 283 if (ppc_md.progress) 284 ppc_md.progress("ep8248e_setup_arch(), finish", 0); 285 } 286 287 static __initdata struct of_device_id of_bus_ids[] = { 288 { .compatible = "simple-bus", }, 289 { .compatible = "fsl,ep8248e-bcsr", }, 290 {}, 291 }; 292 293 static int __init declare_of_platform_devices(void) 294 { 295 of_platform_bus_probe(NULL, of_bus_ids, NULL); 296 of_register_platform_driver(&ep8248e_mdio_driver); 297 298 return 0; 299 } 300 machine_device_initcall(ep8248e, declare_of_platform_devices); 301 302 /* 303 * Called very early, device-tree isn't unflattened 304 */ 305 static int __init ep8248e_probe(void) 306 { 307 unsigned long root = of_get_flat_dt_root(); 308 return of_flat_dt_is_compatible(root, "fsl,ep8248e"); 309 } 310 311 define_machine(ep8248e) 312 { 313 .name = "Embedded Planet EP8248E", 314 .probe = ep8248e_probe, 315 .setup_arch = ep8248e_setup_arch, 316 .init_IRQ = ep8248e_pic_init, 317 .get_irq = cpm2_get_irq, 318 .calibrate_decr = generic_calibrate_decr, 319 .restart = pq2_restart, 320 .progress = udbg_progress, 321 }; 322