1 /* 2 * Embedded Planet EP8248E support 3 * 4 * Copyright 2007 Freescale Semiconductor, Inc. 5 * Author: Scott Wood <scottwood@freescale.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/fsl_devices.h> 16 #include <linux/mdio-bitbang.h> 17 #include <linux/of_platform.h> 18 19 #include <asm/io.h> 20 #include <asm/cpm2.h> 21 #include <asm/udbg.h> 22 #include <asm/machdep.h> 23 #include <asm/time.h> 24 #include <asm/mpc8260.h> 25 #include <asm/prom.h> 26 27 #include <sysdev/fsl_soc.h> 28 #include <sysdev/cpm2_pic.h> 29 30 #include "pq2.h" 31 32 static u8 __iomem *ep8248e_bcsr; 33 static struct device_node *ep8248e_bcsr_node; 34 35 #define BCSR7_SCC2_ENABLE 0x10 36 37 #define BCSR8_PHY1_ENABLE 0x80 38 #define BCSR8_PHY1_POWER 0x40 39 #define BCSR8_PHY2_ENABLE 0x20 40 #define BCSR8_PHY2_POWER 0x10 41 #define BCSR8_MDIO_READ 0x04 42 #define BCSR8_MDIO_CLOCK 0x02 43 #define BCSR8_MDIO_DATA 0x01 44 45 #define BCSR9_USB_ENABLE 0x80 46 #define BCSR9_USB_POWER 0x40 47 #define BCSR9_USB_HOST 0x20 48 #define BCSR9_USB_FULL_SPEED_TARGET 0x10 49 50 static void __init ep8248e_pic_init(void) 51 { 52 struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic"); 53 if (!np) { 54 printk(KERN_ERR "PIC init: can not find cpm-pic node\n"); 55 return; 56 } 57 58 cpm2_pic_init(np); 59 of_node_put(np); 60 } 61 62 static void ep8248e_set_mdc(struct mdiobb_ctrl *ctrl, int level) 63 { 64 if (level) 65 setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK); 66 else 67 clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK); 68 69 /* Read back to flush the write. */ 70 in_8(&ep8248e_bcsr[8]); 71 } 72 73 static void ep8248e_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 74 { 75 if (output) 76 clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ); 77 else 78 setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ); 79 80 /* Read back to flush the write. */ 81 in_8(&ep8248e_bcsr[8]); 82 } 83 84 static void ep8248e_set_mdio_data(struct mdiobb_ctrl *ctrl, int data) 85 { 86 if (data) 87 setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA); 88 else 89 clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA); 90 91 /* Read back to flush the write. */ 92 in_8(&ep8248e_bcsr[8]); 93 } 94 95 static int ep8248e_get_mdio_data(struct mdiobb_ctrl *ctrl) 96 { 97 return in_8(&ep8248e_bcsr[8]) & BCSR8_MDIO_DATA; 98 } 99 100 static const struct mdiobb_ops ep8248e_mdio_ops = { 101 .set_mdc = ep8248e_set_mdc, 102 .set_mdio_dir = ep8248e_set_mdio_dir, 103 .set_mdio_data = ep8248e_set_mdio_data, 104 .get_mdio_data = ep8248e_get_mdio_data, 105 .owner = THIS_MODULE, 106 }; 107 108 static struct mdiobb_ctrl ep8248e_mdio_ctrl = { 109 .ops = &ep8248e_mdio_ops, 110 }; 111 112 static int __devinit ep8248e_mdio_probe(struct of_device *ofdev, 113 const struct of_device_id *match) 114 { 115 struct mii_bus *bus; 116 struct resource res; 117 struct device_node *node; 118 int ret, i; 119 120 node = of_get_parent(ofdev->node); 121 of_node_put(node); 122 if (node != ep8248e_bcsr_node) 123 return -ENODEV; 124 125 ret = of_address_to_resource(ofdev->node, 0, &res); 126 if (ret) 127 return ret; 128 129 bus = alloc_mdio_bitbang(&ep8248e_mdio_ctrl); 130 if (!bus) 131 return -ENOMEM; 132 133 bus->phy_mask = 0; 134 bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 135 136 for (i = 0; i < PHY_MAX_ADDR; i++) 137 bus->irq[i] = -1; 138 139 bus->name = "ep8248e-mdio-bitbang"; 140 bus->parent = &ofdev->dev; 141 snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start); 142 143 return mdiobus_register(bus); 144 } 145 146 static int ep8248e_mdio_remove(struct of_device *ofdev) 147 { 148 BUG(); 149 return 0; 150 } 151 152 static const struct of_device_id ep8248e_mdio_match[] = { 153 { 154 .compatible = "fsl,ep8248e-mdio-bitbang", 155 }, 156 {}, 157 }; 158 159 static struct of_platform_driver ep8248e_mdio_driver = { 160 .driver = { 161 .name = "ep8248e-mdio-bitbang", 162 }, 163 .match_table = ep8248e_mdio_match, 164 .probe = ep8248e_mdio_probe, 165 .remove = ep8248e_mdio_remove, 166 }; 167 168 struct cpm_pin { 169 int port, pin, flags; 170 }; 171 172 static __initdata struct cpm_pin ep8248e_pins[] = { 173 /* SMC1 */ 174 {2, 4, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 175 {2, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 176 177 /* SCC1 */ 178 {2, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 179 {2, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 180 {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 181 {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 182 {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 183 184 /* FCC1 */ 185 {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 186 {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 187 {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 188 {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 189 {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 190 {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 191 {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 192 {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 193 {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 194 {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 195 {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 196 {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 197 {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 198 {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 199 {2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 200 {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 201 202 /* FCC2 */ 203 {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 204 {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 205 {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 206 {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 207 {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 208 {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 209 {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 210 {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 211 {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 212 {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 213 {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 214 {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 215 {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 216 {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 217 {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 218 {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 219 220 /* I2C */ 221 {4, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 222 {4, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 223 224 /* USB */ 225 {2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 226 {2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 227 {2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 228 {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 229 {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 230 {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 231 {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 232 }; 233 234 static void __init init_ioports(void) 235 { 236 int i; 237 238 for (i = 0; i < ARRAY_SIZE(ep8248e_pins); i++) { 239 const struct cpm_pin *pin = &ep8248e_pins[i]; 240 cpm2_set_pin(pin->port, pin->pin, pin->flags); 241 } 242 243 cpm2_smc_clk_setup(CPM_CLK_SMC1, CPM_BRG7); 244 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX); 245 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX); 246 cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX); /* USB */ 247 cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX); 248 cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX); 249 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX); 250 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX); 251 } 252 253 static void __init ep8248e_setup_arch(void) 254 { 255 if (ppc_md.progress) 256 ppc_md.progress("ep8248e_setup_arch()", 0); 257 258 cpm2_reset(); 259 260 /* When this is set, snooping CPM DMA from RAM causes 261 * machine checks. See erratum SIU18. 262 */ 263 clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP); 264 265 ep8248e_bcsr_node = 266 of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr"); 267 if (!ep8248e_bcsr_node) { 268 printk(KERN_ERR "No bcsr in device tree\n"); 269 return; 270 } 271 272 ep8248e_bcsr = of_iomap(ep8248e_bcsr_node, 0); 273 if (!ep8248e_bcsr) { 274 printk(KERN_ERR "Cannot map BCSR registers\n"); 275 of_node_put(ep8248e_bcsr_node); 276 ep8248e_bcsr_node = NULL; 277 return; 278 } 279 280 setbits8(&ep8248e_bcsr[7], BCSR7_SCC2_ENABLE); 281 setbits8(&ep8248e_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER | 282 BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER); 283 284 init_ioports(); 285 286 if (ppc_md.progress) 287 ppc_md.progress("ep8248e_setup_arch(), finish", 0); 288 } 289 290 static __initdata struct of_device_id of_bus_ids[] = { 291 { .compatible = "simple-bus", }, 292 { .compatible = "fsl,ep8248e-bcsr", }, 293 {}, 294 }; 295 296 static int __init declare_of_platform_devices(void) 297 { 298 of_platform_bus_probe(NULL, of_bus_ids, NULL); 299 of_register_platform_driver(&ep8248e_mdio_driver); 300 301 return 0; 302 } 303 machine_device_initcall(ep8248e, declare_of_platform_devices); 304 305 /* 306 * Called very early, device-tree isn't unflattened 307 */ 308 static int __init ep8248e_probe(void) 309 { 310 unsigned long root = of_get_flat_dt_root(); 311 return of_flat_dt_is_compatible(root, "fsl,ep8248e"); 312 } 313 314 define_machine(ep8248e) 315 { 316 .name = "Embedded Planet EP8248E", 317 .probe = ep8248e_probe, 318 .setup_arch = ep8248e_setup_arch, 319 .init_IRQ = ep8248e_pic_init, 320 .get_irq = cpm2_get_irq, 321 .calibrate_decr = generic_calibrate_decr, 322 .restart = pq2_restart, 323 .progress = udbg_progress, 324 }; 325