1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Embedded Planet EP8248E support
4  *
5  * Copyright 2007 Freescale Semiconductor, Inc.
6  * Author: Scott Wood <scottwood@freescale.com>
7  */
8 
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
11 #include <linux/fsl_devices.h>
12 #include <linux/mdio-bitbang.h>
13 #include <linux/of_mdio.h>
14 #include <linux/slab.h>
15 #include <linux/of_platform.h>
16 
17 #include <asm/io.h>
18 #include <asm/cpm2.h>
19 #include <asm/udbg.h>
20 #include <asm/machdep.h>
21 #include <asm/time.h>
22 #include <asm/mpc8260.h>
23 #include <asm/prom.h>
24 
25 #include <sysdev/fsl_soc.h>
26 #include <sysdev/cpm2_pic.h>
27 
28 #include "pq2.h"
29 
30 static u8 __iomem *ep8248e_bcsr;
31 static struct device_node *ep8248e_bcsr_node;
32 
33 #define BCSR7_SCC2_ENABLE 0x10
34 
35 #define BCSR8_PHY1_ENABLE 0x80
36 #define BCSR8_PHY1_POWER  0x40
37 #define BCSR8_PHY2_ENABLE 0x20
38 #define BCSR8_PHY2_POWER  0x10
39 #define BCSR8_MDIO_READ   0x04
40 #define BCSR8_MDIO_CLOCK  0x02
41 #define BCSR8_MDIO_DATA   0x01
42 
43 #define BCSR9_USB_ENABLE  0x80
44 #define BCSR9_USB_POWER   0x40
45 #define BCSR9_USB_HOST    0x20
46 #define BCSR9_USB_FULL_SPEED_TARGET 0x10
47 
48 static void __init ep8248e_pic_init(void)
49 {
50 	struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic");
51 	if (!np) {
52 		printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
53 		return;
54 	}
55 
56 	cpm2_pic_init(np);
57 	of_node_put(np);
58 }
59 
60 static void ep8248e_set_mdc(struct mdiobb_ctrl *ctrl, int level)
61 {
62 	if (level)
63 		setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK);
64 	else
65 		clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK);
66 
67 	/* Read back to flush the write. */
68 	in_8(&ep8248e_bcsr[8]);
69 }
70 
71 static void ep8248e_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
72 {
73 	if (output)
74 		clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ);
75 	else
76 		setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ);
77 
78 	/* Read back to flush the write. */
79 	in_8(&ep8248e_bcsr[8]);
80 }
81 
82 static void ep8248e_set_mdio_data(struct mdiobb_ctrl *ctrl, int data)
83 {
84 	if (data)
85 		setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA);
86 	else
87 		clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA);
88 
89 	/* Read back to flush the write. */
90 	in_8(&ep8248e_bcsr[8]);
91 }
92 
93 static int ep8248e_get_mdio_data(struct mdiobb_ctrl *ctrl)
94 {
95 	return in_8(&ep8248e_bcsr[8]) & BCSR8_MDIO_DATA;
96 }
97 
98 static const struct mdiobb_ops ep8248e_mdio_ops = {
99 	.set_mdc = ep8248e_set_mdc,
100 	.set_mdio_dir = ep8248e_set_mdio_dir,
101 	.set_mdio_data = ep8248e_set_mdio_data,
102 	.get_mdio_data = ep8248e_get_mdio_data,
103 	.owner = THIS_MODULE,
104 };
105 
106 static struct mdiobb_ctrl ep8248e_mdio_ctrl = {
107 	.ops = &ep8248e_mdio_ops,
108 };
109 
110 static int ep8248e_mdio_probe(struct platform_device *ofdev)
111 {
112 	struct mii_bus *bus;
113 	struct resource res;
114 	struct device_node *node;
115 	int ret;
116 
117 	node = of_get_parent(ofdev->dev.of_node);
118 	of_node_put(node);
119 	if (node != ep8248e_bcsr_node)
120 		return -ENODEV;
121 
122 	ret = of_address_to_resource(ofdev->dev.of_node, 0, &res);
123 	if (ret)
124 		return ret;
125 
126 	bus = alloc_mdio_bitbang(&ep8248e_mdio_ctrl);
127 	if (!bus)
128 		return -ENOMEM;
129 
130 	bus->name = "ep8248e-mdio-bitbang";
131 	bus->parent = &ofdev->dev;
132 	snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
133 
134 	ret = of_mdiobus_register(bus, ofdev->dev.of_node);
135 	if (ret)
136 		goto err_free_bus;
137 
138 	return 0;
139 err_free_bus:
140 	free_mdio_bitbang(bus);
141 	return ret;
142 }
143 
144 static int ep8248e_mdio_remove(struct platform_device *ofdev)
145 {
146 	BUG();
147 	return 0;
148 }
149 
150 static const struct of_device_id ep8248e_mdio_match[] = {
151 	{
152 		.compatible = "fsl,ep8248e-mdio-bitbang",
153 	},
154 	{},
155 };
156 
157 static struct platform_driver ep8248e_mdio_driver = {
158 	.driver = {
159 		.name = "ep8248e-mdio-bitbang",
160 		.of_match_table = ep8248e_mdio_match,
161 	},
162 	.probe = ep8248e_mdio_probe,
163 	.remove = ep8248e_mdio_remove,
164 };
165 
166 struct cpm_pin {
167 	int port, pin, flags;
168 };
169 
170 static __initdata struct cpm_pin ep8248e_pins[] = {
171 	/* SMC1 */
172 	{2, 4, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
173 	{2, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
174 
175 	/* SCC1 */
176 	{2, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
177 	{2, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
178 	{3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
179 	{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
180 	{3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
181 
182 	/* FCC1 */
183 	{0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
184 	{0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
185 	{0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
186 	{0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
187 	{0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
188 	{0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
189 	{0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
190 	{0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
191 	{0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
192 	{0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
193 	{0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
194 	{0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
195 	{0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
196 	{0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
197 	{2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
198 	{2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
199 
200 	/* FCC2 */
201 	{1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
202 	{1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
203 	{1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
204 	{1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
205 	{1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
206 	{1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
207 	{1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
208 	{1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
209 	{1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
210 	{1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
211 	{1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
212 	{1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
213 	{1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
214 	{1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
215 	{2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
216 	{2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
217 
218 	/* I2C */
219 	{4, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
220 	{4, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
221 
222 	/* USB */
223 	{2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
224 	{2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
225 	{2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
226 	{2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
227 	{3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
228 	{3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
229 	{3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
230 };
231 
232 static void __init init_ioports(void)
233 {
234 	int i;
235 
236 	for (i = 0; i < ARRAY_SIZE(ep8248e_pins); i++) {
237 		const struct cpm_pin *pin = &ep8248e_pins[i];
238 		cpm2_set_pin(pin->port, pin->pin, pin->flags);
239 	}
240 
241 	cpm2_smc_clk_setup(CPM_CLK_SMC1, CPM_BRG7);
242 	cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
243 	cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
244 	cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX); /* USB */
245 	cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX);
246 	cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
247 	cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
248 	cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
249 }
250 
251 static void __init ep8248e_setup_arch(void)
252 {
253 	if (ppc_md.progress)
254 		ppc_md.progress("ep8248e_setup_arch()", 0);
255 
256 	cpm2_reset();
257 
258 	/* When this is set, snooping CPM DMA from RAM causes
259 	 * machine checks.  See erratum SIU18.
260 	 */
261 	clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
262 
263 	ep8248e_bcsr_node =
264 		of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr");
265 	if (!ep8248e_bcsr_node) {
266 		printk(KERN_ERR "No bcsr in device tree\n");
267 		return;
268 	}
269 
270 	ep8248e_bcsr = of_iomap(ep8248e_bcsr_node, 0);
271 	if (!ep8248e_bcsr) {
272 		printk(KERN_ERR "Cannot map BCSR registers\n");
273 		of_node_put(ep8248e_bcsr_node);
274 		ep8248e_bcsr_node = NULL;
275 		return;
276 	}
277 
278 	setbits8(&ep8248e_bcsr[7], BCSR7_SCC2_ENABLE);
279 	setbits8(&ep8248e_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER |
280 	                           BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER);
281 
282 	init_ioports();
283 
284 	if (ppc_md.progress)
285 		ppc_md.progress("ep8248e_setup_arch(), finish", 0);
286 }
287 
288 static const struct of_device_id of_bus_ids[] __initconst = {
289 	{ .compatible = "simple-bus", },
290 	{ .compatible = "fsl,ep8248e-bcsr", },
291 	{},
292 };
293 
294 static int __init declare_of_platform_devices(void)
295 {
296 	of_platform_bus_probe(NULL, of_bus_ids, NULL);
297 
298 	if (IS_ENABLED(CONFIG_MDIO_BITBANG))
299 		platform_driver_register(&ep8248e_mdio_driver);
300 
301 	return 0;
302 }
303 machine_device_initcall(ep8248e, declare_of_platform_devices);
304 
305 /*
306  * Called very early, device-tree isn't unflattened
307  */
308 static int __init ep8248e_probe(void)
309 {
310 	return of_machine_is_compatible("fsl,ep8248e");
311 }
312 
313 define_machine(ep8248e)
314 {
315 	.name = "Embedded Planet EP8248E",
316 	.probe = ep8248e_probe,
317 	.setup_arch = ep8248e_setup_arch,
318 	.init_IRQ = ep8248e_pic_init,
319 	.get_irq = cpm2_get_irq,
320 	.calibrate_decr = generic_calibrate_decr,
321 	.restart = pq2_restart,
322 	.progress = udbg_progress,
323 };
324