1 /* 2 * Embedded Planet EP8248E support 3 * 4 * Copyright 2007 Freescale Semiconductor, Inc. 5 * Author: Scott Wood <scottwood@freescale.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/fsl_devices.h> 16 #include <linux/mdio-bitbang.h> 17 #include <linux/of_mdio.h> 18 #include <linux/slab.h> 19 #include <linux/of_platform.h> 20 21 #include <asm/io.h> 22 #include <asm/cpm2.h> 23 #include <asm/udbg.h> 24 #include <asm/machdep.h> 25 #include <asm/time.h> 26 #include <asm/mpc8260.h> 27 #include <asm/prom.h> 28 29 #include <sysdev/fsl_soc.h> 30 #include <sysdev/cpm2_pic.h> 31 32 #include "pq2.h" 33 34 static u8 __iomem *ep8248e_bcsr; 35 static struct device_node *ep8248e_bcsr_node; 36 37 #define BCSR7_SCC2_ENABLE 0x10 38 39 #define BCSR8_PHY1_ENABLE 0x80 40 #define BCSR8_PHY1_POWER 0x40 41 #define BCSR8_PHY2_ENABLE 0x20 42 #define BCSR8_PHY2_POWER 0x10 43 #define BCSR8_MDIO_READ 0x04 44 #define BCSR8_MDIO_CLOCK 0x02 45 #define BCSR8_MDIO_DATA 0x01 46 47 #define BCSR9_USB_ENABLE 0x80 48 #define BCSR9_USB_POWER 0x40 49 #define BCSR9_USB_HOST 0x20 50 #define BCSR9_USB_FULL_SPEED_TARGET 0x10 51 52 static void __init ep8248e_pic_init(void) 53 { 54 struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic"); 55 if (!np) { 56 printk(KERN_ERR "PIC init: can not find cpm-pic node\n"); 57 return; 58 } 59 60 cpm2_pic_init(np); 61 of_node_put(np); 62 } 63 64 static void ep8248e_set_mdc(struct mdiobb_ctrl *ctrl, int level) 65 { 66 if (level) 67 setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK); 68 else 69 clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK); 70 71 /* Read back to flush the write. */ 72 in_8(&ep8248e_bcsr[8]); 73 } 74 75 static void ep8248e_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 76 { 77 if (output) 78 clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ); 79 else 80 setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ); 81 82 /* Read back to flush the write. */ 83 in_8(&ep8248e_bcsr[8]); 84 } 85 86 static void ep8248e_set_mdio_data(struct mdiobb_ctrl *ctrl, int data) 87 { 88 if (data) 89 setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA); 90 else 91 clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA); 92 93 /* Read back to flush the write. */ 94 in_8(&ep8248e_bcsr[8]); 95 } 96 97 static int ep8248e_get_mdio_data(struct mdiobb_ctrl *ctrl) 98 { 99 return in_8(&ep8248e_bcsr[8]) & BCSR8_MDIO_DATA; 100 } 101 102 static const struct mdiobb_ops ep8248e_mdio_ops = { 103 .set_mdc = ep8248e_set_mdc, 104 .set_mdio_dir = ep8248e_set_mdio_dir, 105 .set_mdio_data = ep8248e_set_mdio_data, 106 .get_mdio_data = ep8248e_get_mdio_data, 107 .owner = THIS_MODULE, 108 }; 109 110 static struct mdiobb_ctrl ep8248e_mdio_ctrl = { 111 .ops = &ep8248e_mdio_ops, 112 }; 113 114 static int ep8248e_mdio_probe(struct platform_device *ofdev) 115 { 116 struct mii_bus *bus; 117 struct resource res; 118 struct device_node *node; 119 int ret; 120 121 node = of_get_parent(ofdev->dev.of_node); 122 of_node_put(node); 123 if (node != ep8248e_bcsr_node) 124 return -ENODEV; 125 126 ret = of_address_to_resource(ofdev->dev.of_node, 0, &res); 127 if (ret) 128 return ret; 129 130 bus = alloc_mdio_bitbang(&ep8248e_mdio_ctrl); 131 if (!bus) 132 return -ENOMEM; 133 134 bus->name = "ep8248e-mdio-bitbang"; 135 bus->parent = &ofdev->dev; 136 snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start); 137 138 ret = of_mdiobus_register(bus, ofdev->dev.of_node); 139 if (ret) 140 goto err_free_bus; 141 142 return 0; 143 err_free_bus: 144 free_mdio_bitbang(bus); 145 return ret; 146 } 147 148 static int ep8248e_mdio_remove(struct platform_device *ofdev) 149 { 150 BUG(); 151 return 0; 152 } 153 154 static const struct of_device_id ep8248e_mdio_match[] = { 155 { 156 .compatible = "fsl,ep8248e-mdio-bitbang", 157 }, 158 {}, 159 }; 160 161 static struct platform_driver ep8248e_mdio_driver = { 162 .driver = { 163 .name = "ep8248e-mdio-bitbang", 164 .of_match_table = ep8248e_mdio_match, 165 }, 166 .probe = ep8248e_mdio_probe, 167 .remove = ep8248e_mdio_remove, 168 }; 169 170 struct cpm_pin { 171 int port, pin, flags; 172 }; 173 174 static __initdata struct cpm_pin ep8248e_pins[] = { 175 /* SMC1 */ 176 {2, 4, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 177 {2, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 178 179 /* SCC1 */ 180 {2, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 181 {2, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 182 {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 183 {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 184 {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 185 186 /* FCC1 */ 187 {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 188 {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 189 {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 190 {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 191 {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 192 {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 193 {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 194 {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 195 {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 196 {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 197 {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 198 {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 199 {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 200 {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 201 {2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 202 {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 203 204 /* FCC2 */ 205 {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 206 {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 207 {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 208 {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 209 {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 210 {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 211 {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 212 {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 213 {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 214 {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 215 {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 216 {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, 217 {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 218 {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 219 {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 220 {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 221 222 /* I2C */ 223 {4, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 224 {4, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, 225 226 /* USB */ 227 {2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 228 {2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 229 {2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 230 {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 231 {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 232 {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, 233 {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, 234 }; 235 236 static void __init init_ioports(void) 237 { 238 int i; 239 240 for (i = 0; i < ARRAY_SIZE(ep8248e_pins); i++) { 241 const struct cpm_pin *pin = &ep8248e_pins[i]; 242 cpm2_set_pin(pin->port, pin->pin, pin->flags); 243 } 244 245 cpm2_smc_clk_setup(CPM_CLK_SMC1, CPM_BRG7); 246 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX); 247 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX); 248 cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX); /* USB */ 249 cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX); 250 cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX); 251 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX); 252 cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX); 253 } 254 255 static void __init ep8248e_setup_arch(void) 256 { 257 if (ppc_md.progress) 258 ppc_md.progress("ep8248e_setup_arch()", 0); 259 260 cpm2_reset(); 261 262 /* When this is set, snooping CPM DMA from RAM causes 263 * machine checks. See erratum SIU18. 264 */ 265 clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP); 266 267 ep8248e_bcsr_node = 268 of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr"); 269 if (!ep8248e_bcsr_node) { 270 printk(KERN_ERR "No bcsr in device tree\n"); 271 return; 272 } 273 274 ep8248e_bcsr = of_iomap(ep8248e_bcsr_node, 0); 275 if (!ep8248e_bcsr) { 276 printk(KERN_ERR "Cannot map BCSR registers\n"); 277 of_node_put(ep8248e_bcsr_node); 278 ep8248e_bcsr_node = NULL; 279 return; 280 } 281 282 setbits8(&ep8248e_bcsr[7], BCSR7_SCC2_ENABLE); 283 setbits8(&ep8248e_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER | 284 BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER); 285 286 init_ioports(); 287 288 if (ppc_md.progress) 289 ppc_md.progress("ep8248e_setup_arch(), finish", 0); 290 } 291 292 static const struct of_device_id of_bus_ids[] __initconst = { 293 { .compatible = "simple-bus", }, 294 { .compatible = "fsl,ep8248e-bcsr", }, 295 {}, 296 }; 297 298 static int __init declare_of_platform_devices(void) 299 { 300 of_platform_bus_probe(NULL, of_bus_ids, NULL); 301 302 if (IS_ENABLED(CONFIG_MDIO_BITBANG)) 303 platform_driver_register(&ep8248e_mdio_driver); 304 305 return 0; 306 } 307 machine_device_initcall(ep8248e, declare_of_platform_devices); 308 309 /* 310 * Called very early, device-tree isn't unflattened 311 */ 312 static int __init ep8248e_probe(void) 313 { 314 return of_machine_is_compatible("fsl,ep8248e"); 315 } 316 317 define_machine(ep8248e) 318 { 319 .name = "Embedded Planet EP8248E", 320 .probe = ep8248e_probe, 321 .setup_arch = ep8248e_setup_arch, 322 .init_IRQ = ep8248e_pic_init, 323 .get_irq = cpm2_get_irq, 324 .calibrate_decr = generic_calibrate_decr, 325 .restart = pq2_restart, 326 .progress = udbg_progress, 327 }; 328