1 #include <linux/init.h> 2 #include <linux/suspend.h> 3 #include <linux/io.h> 4 #include <asm/time.h> 5 #include <asm/cacheflush.h> 6 #include <asm/mpc52xx.h> 7 8 #include "mpc52xx_pic.h" 9 10 11 /* these are defined in mpc52xx_sleep.S, and only used here */ 12 extern void mpc52xx_deep_sleep(void __iomem *sram, void __iomem *sdram_regs, 13 struct mpc52xx_cdm __iomem *, struct mpc52xx_intr __iomem*); 14 extern void mpc52xx_ds_sram(void); 15 extern const long mpc52xx_ds_sram_size; 16 extern void mpc52xx_ds_cached(void); 17 extern const long mpc52xx_ds_cached_size; 18 19 static void __iomem *mbar; 20 static void __iomem *sdram; 21 static struct mpc52xx_cdm __iomem *cdm; 22 static struct mpc52xx_intr __iomem *intr; 23 static struct mpc52xx_gpio_wkup __iomem *gpiow; 24 static void __iomem *sram; 25 static int sram_size; 26 27 struct mpc52xx_suspend mpc52xx_suspend; 28 29 static int mpc52xx_pm_valid(suspend_state_t state) 30 { 31 switch (state) { 32 case PM_SUSPEND_STANDBY: 33 return 1; 34 default: 35 return 0; 36 } 37 } 38 39 int mpc52xx_set_wakeup_gpio(u8 pin, u8 level) 40 { 41 u16 tmp; 42 43 /* enable gpio */ 44 out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin)); 45 /* set as input */ 46 out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin)); 47 /* enable deep sleep interrupt */ 48 out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin)); 49 /* low/high level creates wakeup interrupt */ 50 tmp = in_be16(&gpiow->wkup_itype); 51 tmp &= ~(0x3 << (pin * 2)); 52 tmp |= (!level + 1) << (pin * 2); 53 out_be16(&gpiow->wkup_itype, tmp); 54 /* master enable */ 55 out_8(&gpiow->wkup_maste, 1); 56 57 return 0; 58 } 59 60 int mpc52xx_pm_prepare(void) 61 { 62 struct device_node *np; 63 const struct of_device_id immr_ids[] = { 64 { .compatible = "fsl,mpc5200-immr", }, 65 { .compatible = "fsl,mpc5200b-immr", }, 66 { .type = "soc", .compatible = "mpc5200", }, /* lite5200 */ 67 { .type = "builtin", .compatible = "mpc5200", }, /* efika */ 68 {} 69 }; 70 71 /* map the whole register space */ 72 np = of_find_matching_node(NULL, immr_ids); 73 mbar = of_iomap(np, 0); 74 of_node_put(np); 75 if (!mbar) { 76 pr_err("mpc52xx_pm_prepare(): could not map registers\n"); 77 return -ENOSYS; 78 } 79 /* these offsets are from mpc5200 users manual */ 80 sdram = mbar + 0x100; 81 cdm = mbar + 0x200; 82 intr = mbar + 0x500; 83 gpiow = mbar + 0xc00; 84 sram = mbar + 0x8000; /* Those will be handled by the */ 85 sram_size = 0x4000; /* bestcomm driver soon */ 86 87 /* call board suspend code, if applicable */ 88 if (mpc52xx_suspend.board_suspend_prepare) 89 mpc52xx_suspend.board_suspend_prepare(mbar); 90 else { 91 printk(KERN_ALERT "%s: %i don't know how to wake up the board\n", 92 __func__, __LINE__); 93 goto out_unmap; 94 } 95 96 return 0; 97 98 out_unmap: 99 iounmap(mbar); 100 return -ENOSYS; 101 } 102 103 104 char saved_sram[0x4000]; 105 106 int mpc52xx_pm_enter(suspend_state_t state) 107 { 108 u32 clk_enables; 109 u32 msr, hid0; 110 u32 intr_main_mask; 111 void __iomem * irq_0x500 = (void __iomem *)CONFIG_KERNEL_START + 0x500; 112 unsigned long irq_0x500_stop = (unsigned long)irq_0x500 + mpc52xx_ds_cached_size; 113 char saved_0x500[mpc52xx_ds_cached_size]; 114 115 /* disable all interrupts in PIC */ 116 intr_main_mask = in_be32(&intr->main_mask); 117 out_be32(&intr->main_mask, intr_main_mask | 0x1ffff); 118 119 /* don't let DEC expire any time soon */ 120 mtspr(SPRN_DEC, 0x7fffffff); 121 122 /* save SRAM */ 123 memcpy(saved_sram, sram, sram_size); 124 125 /* copy low level suspend code to sram */ 126 memcpy(sram, mpc52xx_ds_sram, mpc52xx_ds_sram_size); 127 128 out_8(&cdm->ccs_sleep_enable, 1); 129 out_8(&cdm->osc_sleep_enable, 1); 130 out_8(&cdm->ccs_qreq_test, 1); 131 132 /* disable all but SDRAM and bestcomm (SRAM) clocks */ 133 clk_enables = in_be32(&cdm->clk_enables); 134 out_be32(&cdm->clk_enables, clk_enables & 0x00088000); 135 136 /* disable power management */ 137 msr = mfmsr(); 138 mtmsr(msr & ~MSR_POW); 139 140 /* enable sleep mode, disable others */ 141 hid0 = mfspr(SPRN_HID0); 142 mtspr(SPRN_HID0, (hid0 & ~(HID0_DOZE | HID0_NAP | HID0_DPM)) | HID0_SLEEP); 143 144 /* save original, copy our irq handler, flush from dcache and invalidate icache */ 145 memcpy(saved_0x500, irq_0x500, mpc52xx_ds_cached_size); 146 memcpy(irq_0x500, mpc52xx_ds_cached, mpc52xx_ds_cached_size); 147 flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop); 148 149 /* call low-level sleep code */ 150 mpc52xx_deep_sleep(sram, sdram, cdm, intr); 151 152 /* restore original irq handler */ 153 memcpy(irq_0x500, saved_0x500, mpc52xx_ds_cached_size); 154 flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop); 155 156 /* restore old power mode */ 157 mtmsr(msr & ~MSR_POW); 158 mtspr(SPRN_HID0, hid0); 159 mtmsr(msr); 160 161 out_be32(&cdm->clk_enables, clk_enables); 162 out_8(&cdm->ccs_sleep_enable, 0); 163 out_8(&cdm->osc_sleep_enable, 0); 164 165 /* restore SRAM */ 166 memcpy(sram, saved_sram, sram_size); 167 168 /* restart jiffies */ 169 wakeup_decrementer(); 170 171 /* reenable interrupts in PIC */ 172 out_be32(&intr->main_mask, intr_main_mask); 173 174 return 0; 175 } 176 177 void mpc52xx_pm_finish(void) 178 { 179 /* call board resume code */ 180 if (mpc52xx_suspend.board_resume_finish) 181 mpc52xx_suspend.board_resume_finish(mbar); 182 183 iounmap(mbar); 184 } 185 186 static struct platform_suspend_ops mpc52xx_pm_ops = { 187 .valid = mpc52xx_pm_valid, 188 .prepare = mpc52xx_pm_prepare, 189 .enter = mpc52xx_pm_enter, 190 .finish = mpc52xx_pm_finish, 191 }; 192 193 int __init mpc52xx_pm_init(void) 194 { 195 suspend_set_ops(&mpc52xx_pm_ops); 196 return 0; 197 } 198