1 #include <linux/init.h>
2 #include <linux/suspend.h>
3 #include <linux/io.h>
4 #include <asm/time.h>
5 #include <asm/cacheflush.h>
6 #include <asm/mpc52xx.h>
7 
8 #include "mpc52xx_pic.h"
9 
10 
11 /* these are defined in mpc52xx_sleep.S, and only used here */
12 extern void mpc52xx_deep_sleep(void __iomem *sram, void __iomem *sdram_regs,
13 		struct mpc52xx_cdm __iomem *, struct mpc52xx_intr __iomem*);
14 extern void mpc52xx_ds_sram(void);
15 extern const long mpc52xx_ds_sram_size;
16 extern void mpc52xx_ds_cached(void);
17 extern const long mpc52xx_ds_cached_size;
18 
19 static void __iomem *mbar;
20 static void __iomem *sdram;
21 static struct mpc52xx_cdm __iomem *cdm;
22 static struct mpc52xx_intr __iomem *intr;
23 static struct mpc52xx_gpio_wkup __iomem *gpiow;
24 static void __iomem *sram;
25 static int sram_size;
26 
27 struct mpc52xx_suspend mpc52xx_suspend;
28 
29 static int mpc52xx_pm_valid(suspend_state_t state)
30 {
31 	switch (state) {
32 	case PM_SUSPEND_STANDBY:
33 		return 1;
34 	default:
35 		return 0;
36 	}
37 }
38 
39 int mpc52xx_set_wakeup_gpio(u8 pin, u8 level)
40 {
41 	u16 tmp;
42 
43 	/* enable gpio */
44 	out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin));
45 	/* set as input */
46 	out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin));
47 	/* enable deep sleep interrupt */
48 	out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin));
49 	/* low/high level creates wakeup interrupt */
50 	tmp = in_be16(&gpiow->wkup_itype);
51 	tmp &= ~(0x3 << (pin * 2));
52 	tmp |= (!level + 1) << (pin * 2);
53 	out_be16(&gpiow->wkup_itype, tmp);
54 	/* master enable */
55 	out_8(&gpiow->wkup_maste, 1);
56 
57 	return 0;
58 }
59 
60 int mpc52xx_pm_prepare(void)
61 {
62 	struct device_node *np;
63 
64 	/* map the whole register space */
65 	np = of_find_compatible_node(NULL, NULL, "mpc5200");
66 	mbar = of_iomap(np, 0);
67 	of_node_put(np);
68 	if (!mbar) {
69 		pr_err("mpc52xx_pm_prepare(): could not map registers\n");
70 		return -ENOSYS;
71 	}
72 	/* these offsets are from mpc5200 users manual */
73 	sdram	= mbar + 0x100;
74 	cdm	= mbar + 0x200;
75 	intr	= mbar + 0x500;
76 	gpiow	= mbar + 0xc00;
77 	sram	= mbar + 0x8000;	/* Those will be handled by the */
78 	sram_size = 0x4000;		/* bestcomm driver soon */
79 
80 	/* call board suspend code, if applicable */
81 	if (mpc52xx_suspend.board_suspend_prepare)
82 		mpc52xx_suspend.board_suspend_prepare(mbar);
83 	else {
84 		printk(KERN_ALERT "%s: %i don't know how to wake up the board\n",
85 				__func__, __LINE__);
86 		goto out_unmap;
87 	}
88 
89 	return 0;
90 
91  out_unmap:
92 	iounmap(mbar);
93 	return -ENOSYS;
94 }
95 
96 
97 char saved_sram[0x4000];
98 
99 int mpc52xx_pm_enter(suspend_state_t state)
100 {
101 	u32 clk_enables;
102 	u32 msr, hid0;
103 	u32 intr_main_mask;
104 	void __iomem * irq_0x500 = (void __iomem *)CONFIG_KERNEL_START + 0x500;
105 	unsigned long irq_0x500_stop = (unsigned long)irq_0x500 + mpc52xx_ds_cached_size;
106 	char saved_0x500[mpc52xx_ds_cached_size];
107 
108 	/* disable all interrupts in PIC */
109 	intr_main_mask = in_be32(&intr->main_mask);
110 	out_be32(&intr->main_mask, intr_main_mask | 0x1ffff);
111 
112 	/* don't let DEC expire any time soon */
113 	mtspr(SPRN_DEC, 0x7fffffff);
114 
115 	/* save SRAM */
116 	memcpy(saved_sram, sram, sram_size);
117 
118 	/* copy low level suspend code to sram */
119 	memcpy(sram, mpc52xx_ds_sram, mpc52xx_ds_sram_size);
120 
121 	out_8(&cdm->ccs_sleep_enable, 1);
122 	out_8(&cdm->osc_sleep_enable, 1);
123 	out_8(&cdm->ccs_qreq_test, 1);
124 
125 	/* disable all but SDRAM and bestcomm (SRAM) clocks */
126 	clk_enables = in_be32(&cdm->clk_enables);
127 	out_be32(&cdm->clk_enables, clk_enables & 0x00088000);
128 
129 	/* disable power management */
130 	msr = mfmsr();
131 	mtmsr(msr & ~MSR_POW);
132 
133 	/* enable sleep mode, disable others */
134 	hid0 = mfspr(SPRN_HID0);
135 	mtspr(SPRN_HID0, (hid0 & ~(HID0_DOZE | HID0_NAP | HID0_DPM)) | HID0_SLEEP);
136 
137 	/* save original, copy our irq handler, flush from dcache and invalidate icache */
138 	memcpy(saved_0x500, irq_0x500, mpc52xx_ds_cached_size);
139 	memcpy(irq_0x500, mpc52xx_ds_cached, mpc52xx_ds_cached_size);
140 	flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop);
141 
142 	/* call low-level sleep code */
143 	mpc52xx_deep_sleep(sram, sdram, cdm, intr);
144 
145 	/* restore original irq handler */
146 	memcpy(irq_0x500, saved_0x500, mpc52xx_ds_cached_size);
147 	flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop);
148 
149 	/* restore old power mode */
150 	mtmsr(msr & ~MSR_POW);
151 	mtspr(SPRN_HID0, hid0);
152 	mtmsr(msr);
153 
154 	out_be32(&cdm->clk_enables, clk_enables);
155 	out_8(&cdm->ccs_sleep_enable, 0);
156 	out_8(&cdm->osc_sleep_enable, 0);
157 
158 	/* restore SRAM */
159 	memcpy(sram, saved_sram, sram_size);
160 
161 	/* restart jiffies */
162 	wakeup_decrementer();
163 
164 	/* reenable interrupts in PIC */
165 	out_be32(&intr->main_mask, intr_main_mask);
166 
167 	return 0;
168 }
169 
170 void mpc52xx_pm_finish(void)
171 {
172 	/* call board resume code */
173 	if (mpc52xx_suspend.board_resume_finish)
174 		mpc52xx_suspend.board_resume_finish(mbar);
175 
176 	iounmap(mbar);
177 }
178 
179 static struct platform_suspend_ops mpc52xx_pm_ops = {
180 	.valid		= mpc52xx_pm_valid,
181 	.prepare	= mpc52xx_pm_prepare,
182 	.enter		= mpc52xx_pm_enter,
183 	.finish		= mpc52xx_pm_finish,
184 };
185 
186 int __init mpc52xx_pm_init(void)
187 {
188 	suspend_set_ops(&mpc52xx_pm_ops);
189 	return 0;
190 }
191