1 /*
2  *
3  * Programmable Interrupt Controller functions for the Freescale MPC52xx.
4  *
5  * Copyright (C) 2008 Secret Lab Technologies Ltd.
6  * Copyright (C) 2006 bplan GmbH
7  * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
8  * Copyright (C) 2003 Montavista Software, Inc
9  *
10  * Based on the code from the 2.4 kernel by
11  * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
12  *
13  * This file is licensed under the terms of the GNU General Public License
14  * version 2. This program is licensed "as is" without any warranty of any
15  * kind, whether express or implied.
16  *
17  */
18 
19 /*
20  * This is the device driver for the MPC5200 interrupt controller.
21  *
22  * hardware overview
23  * -----------------
24  * The MPC5200 interrupt controller groups the all interrupt sources into
25  * three groups called 'critical', 'main', and 'peripheral'.  The critical
26  * group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
27  * sleep.  Main group include the other 3 external IRQs, slice timer 1, RTC,
28  * gpios, and the general purpose timers.  Peripheral group contains the
29  * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
30  * USB, DMA, etc).
31  *
32  * virqs
33  * -----
34  * The Linux IRQ subsystem requires that each irq source be assigned a
35  * system wide unique IRQ number starting at 1 (0 means no irq).  Since
36  * systems can have multiple interrupt controllers, the virtual IRQ (virq)
37  * infrastructure lets each interrupt controller to define a local set
38  * of IRQ numbers and the virq infrastructure maps those numbers into
39  * a unique range of the global IRQ# space.
40  *
41  * To define a range of virq numbers for this controller, this driver first
42  * assigns a number to each of the irq groups (called the level 1 or L1
43  * value).  Within each group individual irq sources are also assigned a
44  * number, as defined by the MPC5200 user guide, and refers to it as the
45  * level 2 or L2 value.  The virq number is determined by shifting up the
46  * L1 value by MPC52xx_IRQ_L1_OFFSET and ORing it with the L2 value.
47  *
48  * For example, the TMR0 interrupt is irq 9 in the main group.  The
49  * virq for TMR0 is calculated by ((1 << MPC52xx_IRQ_L1_OFFSET) | 9).
50  *
51  * The observant reader will also notice that this driver defines a 4th
52  * interrupt group called 'bestcomm'.  The bestcomm group isn't physically
53  * part of the MPC5200 interrupt controller, but it is used here to assign
54  * a separate virq number for each bestcomm task (since any of the 16
55  * bestcomm tasks can cause the bestcomm interrupt to be raised).  When a
56  * bestcomm interrupt occurs (peripheral group, irq 0) this driver determines
57  * which task needs servicing and returns the irq number for that task.  This
58  * allows drivers which use bestcomm to define their own interrupt handlers.
59  *
60  * irq_chip structures
61  * -------------------
62  * For actually manipulating IRQs (masking, enabling, clearing, etc) this
63  * driver defines four separate 'irq_chip' structures, one for the main
64  * group, one for the peripherals group, one for the bestcomm group and one
65  * for external interrupts.  The irq_chip structures provide the hooks needed
66  * to manipulate each IRQ source, and since each group is has a separate set
67  * of registers for controlling the irq, it makes sense to divide up the
68  * hooks along those lines.
69  *
70  * You'll notice that there is not an irq_chip for the critical group and
71  * you'll also notice that there is an irq_chip defined for external
72  * interrupts even though there is no external interrupt group.  The reason
73  * for this is that the four external interrupts are all managed with the same
74  * register even though one of the external IRQs is in the critical group and
75  * the other three are in the main group.  For this reason it makes sense for
76  * the 4 external irqs to be managed using a separate set of hooks.  The
77  * reason there is no crit irq_chip is that of the 3 irqs in the critical
78  * group, only external interrupt is actually support at this time by this
79  * driver and since external interrupt is the only one used, it can just
80  * be directed to make use of the external irq irq_chip.
81  *
82  * device tree bindings
83  * --------------------
84  * The device tree bindings for this controller reflect the two level
85  * organization of irqs in the device.  #interrupt-cells = <3> where the
86  * first cell is the group number [0..3], the second cell is the irq
87  * number in the group, and the third cell is the sense type (level/edge).
88  * For reference, the following is a list of the interrupt property values
89  * associated with external interrupt sources on the MPC5200 (just because
90  * it is non-obvious to determine what the interrupts property should be
91  * when reading the mpc5200 manual and it is a frequently asked question).
92  *
93  * External interrupts:
94  * <0 0 n>	external irq0, n is sense	(n=0: level high,
95  * <1 1 n>	external irq1, n is sense	 n=1: edge rising,
96  * <1 2 n>	external irq2, n is sense	 n=2: edge falling,
97  * <1 3 n>	external irq3, n is sense	 n=3: level low)
98  */
99 #undef DEBUG
100 
101 #include <linux/interrupt.h>
102 #include <linux/irq.h>
103 #include <linux/of.h>
104 #include <asm/io.h>
105 #include <asm/prom.h>
106 #include <asm/mpc52xx.h>
107 
108 /* HW IRQ mapping */
109 #define MPC52xx_IRQ_L1_CRIT	(0)
110 #define MPC52xx_IRQ_L1_MAIN	(1)
111 #define MPC52xx_IRQ_L1_PERP	(2)
112 #define MPC52xx_IRQ_L1_SDMA	(3)
113 
114 #define MPC52xx_IRQ_L1_OFFSET	(6)
115 #define MPC52xx_IRQ_L1_MASK	(0x00c0)
116 #define MPC52xx_IRQ_L2_MASK	(0x003f)
117 
118 #define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
119 
120 
121 /* MPC5200 device tree match tables */
122 static struct of_device_id mpc52xx_pic_ids[] __initdata = {
123 	{ .compatible = "fsl,mpc5200-pic", },
124 	{ .compatible = "mpc5200-pic", },
125 	{}
126 };
127 static struct of_device_id mpc52xx_sdma_ids[] __initdata = {
128 	{ .compatible = "fsl,mpc5200-bestcomm", },
129 	{ .compatible = "mpc5200-bestcomm", },
130 	{}
131 };
132 
133 static struct mpc52xx_intr __iomem *intr;
134 static struct mpc52xx_sdma __iomem *sdma;
135 static struct irq_host *mpc52xx_irqhost = NULL;
136 
137 static unsigned char mpc52xx_map_senses[4] = {
138 	IRQ_TYPE_LEVEL_HIGH,
139 	IRQ_TYPE_EDGE_RISING,
140 	IRQ_TYPE_EDGE_FALLING,
141 	IRQ_TYPE_LEVEL_LOW,
142 };
143 
144 /* Utility functions */
145 static inline void io_be_setbit(u32 __iomem *addr, int bitno)
146 {
147 	out_be32(addr, in_be32(addr) | (1 << bitno));
148 }
149 
150 static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
151 {
152 	out_be32(addr, in_be32(addr) & ~(1 << bitno));
153 }
154 
155 /*
156  * IRQ[0-3] interrupt irq_chip
157  */
158 static void mpc52xx_extirq_mask(unsigned int virq)
159 {
160 	int irq;
161 	int l2irq;
162 
163 	irq = irq_map[virq].hwirq;
164 	l2irq = irq & MPC52xx_IRQ_L2_MASK;
165 
166 	io_be_clrbit(&intr->ctrl, 11 - l2irq);
167 }
168 
169 static void mpc52xx_extirq_unmask(unsigned int virq)
170 {
171 	int irq;
172 	int l2irq;
173 
174 	irq = irq_map[virq].hwirq;
175 	l2irq = irq & MPC52xx_IRQ_L2_MASK;
176 
177 	io_be_setbit(&intr->ctrl, 11 - l2irq);
178 }
179 
180 static void mpc52xx_extirq_ack(unsigned int virq)
181 {
182 	int irq;
183 	int l2irq;
184 
185 	irq = irq_map[virq].hwirq;
186 	l2irq = irq & MPC52xx_IRQ_L2_MASK;
187 
188 	io_be_setbit(&intr->ctrl, 27-l2irq);
189 }
190 
191 static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
192 {
193 	u32 ctrl_reg, type;
194 	int irq;
195 	int l2irq;
196 	void *handler = handle_level_irq;
197 
198 	irq = irq_map[virq].hwirq;
199 	l2irq = irq & MPC52xx_IRQ_L2_MASK;
200 
201 	pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type);
202 
203 	switch (flow_type) {
204 	case IRQF_TRIGGER_HIGH: type = 0; break;
205 	case IRQF_TRIGGER_RISING: type = 1; handler = handle_edge_irq; break;
206 	case IRQF_TRIGGER_FALLING: type = 2; handler = handle_edge_irq; break;
207 	case IRQF_TRIGGER_LOW: type = 3; break;
208 	default:
209 		type = 0;
210 	}
211 
212 	ctrl_reg = in_be32(&intr->ctrl);
213 	ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
214 	ctrl_reg |= (type << (22 - (l2irq * 2)));
215 	out_be32(&intr->ctrl, ctrl_reg);
216 
217 	__set_irq_handler_unlocked(virq, handler);
218 
219 	return 0;
220 }
221 
222 static struct irq_chip mpc52xx_extirq_irqchip = {
223 	.name = "MPC52xx External",
224 	.mask = mpc52xx_extirq_mask,
225 	.unmask = mpc52xx_extirq_unmask,
226 	.ack = mpc52xx_extirq_ack,
227 	.set_type = mpc52xx_extirq_set_type,
228 };
229 
230 /*
231  * Main interrupt irq_chip
232  */
233 static int mpc52xx_null_set_type(unsigned int virq, unsigned int flow_type)
234 {
235 	return 0; /* Do nothing so that the sense mask will get updated */
236 }
237 
238 static void mpc52xx_main_mask(unsigned int virq)
239 {
240 	int irq;
241 	int l2irq;
242 
243 	irq = irq_map[virq].hwirq;
244 	l2irq = irq & MPC52xx_IRQ_L2_MASK;
245 
246 	io_be_setbit(&intr->main_mask, 16 - l2irq);
247 }
248 
249 static void mpc52xx_main_unmask(unsigned int virq)
250 {
251 	int irq;
252 	int l2irq;
253 
254 	irq = irq_map[virq].hwirq;
255 	l2irq = irq & MPC52xx_IRQ_L2_MASK;
256 
257 	io_be_clrbit(&intr->main_mask, 16 - l2irq);
258 }
259 
260 static struct irq_chip mpc52xx_main_irqchip = {
261 	.name = "MPC52xx Main",
262 	.mask = mpc52xx_main_mask,
263 	.mask_ack = mpc52xx_main_mask,
264 	.unmask = mpc52xx_main_unmask,
265 	.set_type = mpc52xx_null_set_type,
266 };
267 
268 /*
269  * Peripherals interrupt irq_chip
270  */
271 static void mpc52xx_periph_mask(unsigned int virq)
272 {
273 	int irq;
274 	int l2irq;
275 
276 	irq = irq_map[virq].hwirq;
277 	l2irq = irq & MPC52xx_IRQ_L2_MASK;
278 
279 	io_be_setbit(&intr->per_mask, 31 - l2irq);
280 }
281 
282 static void mpc52xx_periph_unmask(unsigned int virq)
283 {
284 	int irq;
285 	int l2irq;
286 
287 	irq = irq_map[virq].hwirq;
288 	l2irq = irq & MPC52xx_IRQ_L2_MASK;
289 
290 	io_be_clrbit(&intr->per_mask, 31 - l2irq);
291 }
292 
293 static struct irq_chip mpc52xx_periph_irqchip = {
294 	.name = "MPC52xx Peripherals",
295 	.mask = mpc52xx_periph_mask,
296 	.mask_ack = mpc52xx_periph_mask,
297 	.unmask = mpc52xx_periph_unmask,
298 	.set_type = mpc52xx_null_set_type,
299 };
300 
301 /*
302  * SDMA interrupt irq_chip
303  */
304 static void mpc52xx_sdma_mask(unsigned int virq)
305 {
306 	int irq;
307 	int l2irq;
308 
309 	irq = irq_map[virq].hwirq;
310 	l2irq = irq & MPC52xx_IRQ_L2_MASK;
311 
312 	io_be_setbit(&sdma->IntMask, l2irq);
313 }
314 
315 static void mpc52xx_sdma_unmask(unsigned int virq)
316 {
317 	int irq;
318 	int l2irq;
319 
320 	irq = irq_map[virq].hwirq;
321 	l2irq = irq & MPC52xx_IRQ_L2_MASK;
322 
323 	io_be_clrbit(&sdma->IntMask, l2irq);
324 }
325 
326 static void mpc52xx_sdma_ack(unsigned int virq)
327 {
328 	int irq;
329 	int l2irq;
330 
331 	irq = irq_map[virq].hwirq;
332 	l2irq = irq & MPC52xx_IRQ_L2_MASK;
333 
334 	out_be32(&sdma->IntPend, 1 << l2irq);
335 }
336 
337 static struct irq_chip mpc52xx_sdma_irqchip = {
338 	.name = "MPC52xx SDMA",
339 	.mask = mpc52xx_sdma_mask,
340 	.unmask = mpc52xx_sdma_unmask,
341 	.ack = mpc52xx_sdma_ack,
342 	.set_type = mpc52xx_null_set_type,
343 };
344 
345 /**
346  * mpc52xx_is_extirq - Returns true if hwirq number is for an external IRQ
347  */
348 static int mpc52xx_is_extirq(int l1, int l2)
349 {
350 	return ((l1 == 0) && (l2 == 0)) ||
351 	       ((l1 == 1) && (l2 >= 1) && (l2 <= 3));
352 }
353 
354 /**
355  * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property
356  */
357 static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
358 				 const u32 *intspec, unsigned int intsize,
359 				 irq_hw_number_t *out_hwirq,
360 				 unsigned int *out_flags)
361 {
362 	int intrvect_l1;
363 	int intrvect_l2;
364 	int intrvect_type;
365 	int intrvect_linux;
366 
367 	if (intsize != 3)
368 		return -1;
369 
370 	intrvect_l1 = (int)intspec[0];
371 	intrvect_l2 = (int)intspec[1];
372 	intrvect_type = (int)intspec[2] & 0x3;
373 
374 	intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) &
375 			 MPC52xx_IRQ_L1_MASK;
376 	intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK;
377 
378 	*out_hwirq = intrvect_linux;
379 	*out_flags = IRQ_TYPE_LEVEL_LOW;
380 	if (mpc52xx_is_extirq(intrvect_l1, intrvect_l2))
381 		*out_flags = mpc52xx_map_senses[intrvect_type];
382 
383 	pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
384 		 intrvect_l2);
385 	return 0;
386 }
387 
388 /**
389  * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure
390  */
391 static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
392 			       irq_hw_number_t irq)
393 {
394 	int l1irq;
395 	int l2irq;
396 	struct irq_chip *irqchip;
397 	void *hndlr;
398 	int type;
399 	u32 reg;
400 
401 	l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
402 	l2irq = irq & MPC52xx_IRQ_L2_MASK;
403 
404 	/*
405 	 * External IRQs are handled differently by the hardware so they are
406 	 * handled by a dedicated irq_chip structure.
407 	 */
408 	if (mpc52xx_is_extirq(l1irq, l2irq)) {
409 		reg = in_be32(&intr->ctrl);
410 		type = mpc52xx_map_senses[(reg >> (22 - l2irq * 2)) & 0x3];
411 		if ((type == IRQ_TYPE_EDGE_FALLING) ||
412 		    (type == IRQ_TYPE_EDGE_RISING))
413 			hndlr = handle_edge_irq;
414 		else
415 			hndlr = handle_level_irq;
416 
417 		set_irq_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
418 		pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n",
419 			 __func__, l2irq, virq, (int)irq, type);
420 		return 0;
421 	}
422 
423 	/* It is an internal SOC irq.  Choose the correct irq_chip */
424 	switch (l1irq) {
425 	case MPC52xx_IRQ_L1_MAIN: irqchip = &mpc52xx_main_irqchip; break;
426 	case MPC52xx_IRQ_L1_PERP: irqchip = &mpc52xx_periph_irqchip; break;
427 	case MPC52xx_IRQ_L1_SDMA: irqchip = &mpc52xx_sdma_irqchip; break;
428 	default:
429 		pr_err("%s: invalid irq: virq=%i, l1=%i, l2=%i\n",
430 		       __func__, virq, l1irq, l2irq);
431 		return -EINVAL;
432 	}
433 
434 	set_irq_chip_and_handler(virq, irqchip, handle_level_irq);
435 	pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq);
436 
437 	return 0;
438 }
439 
440 static struct irq_host_ops mpc52xx_irqhost_ops = {
441 	.xlate = mpc52xx_irqhost_xlate,
442 	.map = mpc52xx_irqhost_map,
443 };
444 
445 /**
446  * mpc52xx_init_irq - Initialize and register with the virq subsystem
447  *
448  * Hook for setting up IRQs on an mpc5200 system.  A pointer to this function
449  * is to be put into the machine definition structure.
450  *
451  * This function searches the device tree for an MPC5200 interrupt controller,
452  * initializes it, and registers it with the virq subsystem.
453  */
454 void __init mpc52xx_init_irq(void)
455 {
456 	u32 intr_ctrl;
457 	struct device_node *picnode;
458 	struct device_node *np;
459 
460 	/* Remap the necessary zones */
461 	picnode = of_find_matching_node(NULL, mpc52xx_pic_ids);
462 	intr = of_iomap(picnode, 0);
463 	if (!intr)
464 		panic(__FILE__	": find_and_map failed on 'mpc5200-pic'. "
465 				"Check node !");
466 
467 	np = of_find_matching_node(NULL, mpc52xx_sdma_ids);
468 	sdma = of_iomap(np, 0);
469 	of_node_put(np);
470 	if (!sdma)
471 		panic(__FILE__	": find_and_map failed on 'mpc5200-bestcomm'. "
472 				"Check node !");
473 
474 	pr_debug("MPC5200 IRQ controller mapped to 0x%p\n", intr);
475 
476 	/* Disable all interrupt sources. */
477 	out_be32(&sdma->IntPend, 0xffffffff);	/* 1 means clear pending */
478 	out_be32(&sdma->IntMask, 0xffffffff);	/* 1 means disabled */
479 	out_be32(&intr->per_mask, 0x7ffffc00);	/* 1 means disabled */
480 	out_be32(&intr->main_mask, 0x00010fff);	/* 1 means disabled */
481 	intr_ctrl = in_be32(&intr->ctrl);
482 	intr_ctrl &= 0x00ff0000;	/* Keeps IRQ[0-3] config */
483 	intr_ctrl |=	0x0f000000 |	/* clear IRQ 0-3 */
484 			0x00001000 |	/* MEE master external enable */
485 			0x00000000 |	/* 0 means disable IRQ 0-3 */
486 			0x00000001;	/* CEb route critical normally */
487 	out_be32(&intr->ctrl, intr_ctrl);
488 
489 	/* Zero a bunch of the priority settings. */
490 	out_be32(&intr->per_pri1, 0);
491 	out_be32(&intr->per_pri2, 0);
492 	out_be32(&intr->per_pri3, 0);
493 	out_be32(&intr->main_pri1, 0);
494 	out_be32(&intr->main_pri2, 0);
495 
496 	/*
497 	 * As last step, add an irq host to translate the real
498 	 * hw irq information provided by the ofw to linux virq
499 	 */
500 	mpc52xx_irqhost = irq_alloc_host(picnode, IRQ_HOST_MAP_LINEAR,
501 	                                 MPC52xx_IRQ_HIGHTESTHWIRQ,
502 	                                 &mpc52xx_irqhost_ops, -1);
503 
504 	if (!mpc52xx_irqhost)
505 		panic(__FILE__ ": Cannot allocate the IRQ host\n");
506 
507 	irq_set_default_host(mpc52xx_irqhost);
508 
509 	pr_info("MPC52xx PIC is up and running!\n");
510 }
511 
512 /**
513  * mpc52xx_get_irq - Get pending interrupt number hook function
514  *
515  * Called by the interupt handler to determine what IRQ handler needs to be
516  * executed.
517  *
518  * Status of pending interrupts is determined by reading the encoded status
519  * register.  The encoded status register has three fields; one for each of the
520  * types of interrupts defined by the controller - 'critical', 'main' and
521  * 'peripheral'.  This function reads the status register and returns the IRQ
522  * number associated with the highest priority pending interrupt.  'Critical'
523  * interrupts have the highest priority, followed by 'main' interrupts, and
524  * then 'peripheral'.
525  *
526  * The mpc5200 interrupt controller can be configured to boost the priority
527  * of individual 'peripheral' interrupts.  If this is the case then a special
528  * value will appear in either the crit or main fields indicating a high
529  * or medium priority peripheral irq has occurred.
530  *
531  * This function checks each of the 3 irq request fields and returns the
532  * first pending interrupt that it finds.
533  *
534  * This function also identifies a 4th type of interrupt; 'bestcomm'.  Each
535  * bestcomm DMA task can raise the bestcomm peripheral interrupt.  When this
536  * occurs at task-specific IRQ# is decoded so that each task can have its
537  * own IRQ handler.
538  */
539 unsigned int mpc52xx_get_irq(void)
540 {
541 	u32 status;
542 	int irq = NO_IRQ_IGNORE;
543 
544 	status = in_be32(&intr->enc_status);
545 	if (status & 0x00000400) {	/* critical */
546 		irq = (status >> 8) & 0x3;
547 		if (irq == 2)	/* high priority peripheral */
548 			goto peripheral;
549 		irq |= (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET);
550 	} else if (status & 0x00200000) {	/* main */
551 		irq = (status >> 16) & 0x1f;
552 		if (irq == 4)	/* low priority peripheral */
553 			goto peripheral;
554 		irq |= (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET);
555 	} else if (status & 0x20000000) {	/* peripheral */
556 	      peripheral:
557 		irq = (status >> 24) & 0x1f;
558 		if (irq == 0) {	/* bestcomm */
559 			status = in_be32(&sdma->IntPend);
560 			irq = ffs(status) - 1;
561 			irq |= (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET);
562 		} else {
563 			irq |= (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET);
564 		}
565 	}
566 
567 	return irq_linear_revmap(mpc52xx_irqhost, irq);
568 }
569