1 /* 2 * PCI code for the Freescale MPC52xx embedded CPU. 3 * 4 * Copyright (C) 2006 Secret Lab Technologies Ltd. 5 * Grant Likely <grant.likely@secretlab.ca> 6 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com> 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 */ 12 13 #undef DEBUG 14 15 #include <asm/pci.h> 16 #include <asm/mpc52xx.h> 17 #include <asm/delay.h> 18 #include <asm/machdep.h> 19 #include <linux/kernel.h> 20 21 22 /* ======================================================================== */ 23 /* PCI windows config */ 24 /* ======================================================================== */ 25 26 #define MPC52xx_PCI_TARGET_IO 0xf0000000 27 #define MPC52xx_PCI_TARGET_MEM 0x00000000 28 29 30 /* ======================================================================== */ 31 /* Structures mapping & Defines for PCI Unit */ 32 /* ======================================================================== */ 33 34 #define MPC52xx_PCI_GSCR_BM 0x40000000 35 #define MPC52xx_PCI_GSCR_PE 0x20000000 36 #define MPC52xx_PCI_GSCR_SE 0x10000000 37 #define MPC52xx_PCI_GSCR_XLB2PCI_MASK 0x07000000 38 #define MPC52xx_PCI_GSCR_XLB2PCI_SHIFT 24 39 #define MPC52xx_PCI_GSCR_IPG2PCI_MASK 0x00070000 40 #define MPC52xx_PCI_GSCR_IPG2PCI_SHIFT 16 41 #define MPC52xx_PCI_GSCR_BME 0x00004000 42 #define MPC52xx_PCI_GSCR_PEE 0x00002000 43 #define MPC52xx_PCI_GSCR_SEE 0x00001000 44 #define MPC52xx_PCI_GSCR_PR 0x00000001 45 46 47 #define MPC52xx_PCI_IWBTAR_TRANSLATION(proc_ad,pci_ad,size) \ 48 ( ( (proc_ad) & 0xff000000 ) | \ 49 ( (((size) - 1) >> 8) & 0x00ff0000 ) | \ 50 ( ((pci_ad) >> 16) & 0x0000ff00 ) ) 51 52 #define MPC52xx_PCI_IWCR_PACK(win0,win1,win2) (((win0) << 24) | \ 53 ((win1) << 16) | \ 54 ((win2) << 8)) 55 56 #define MPC52xx_PCI_IWCR_DISABLE 0x0 57 #define MPC52xx_PCI_IWCR_ENABLE 0x1 58 #define MPC52xx_PCI_IWCR_READ 0x0 59 #define MPC52xx_PCI_IWCR_READ_LINE 0x2 60 #define MPC52xx_PCI_IWCR_READ_MULTI 0x4 61 #define MPC52xx_PCI_IWCR_MEM 0x0 62 #define MPC52xx_PCI_IWCR_IO 0x8 63 64 #define MPC52xx_PCI_TCR_P 0x01000000 65 #define MPC52xx_PCI_TCR_LD 0x00010000 66 67 #define MPC52xx_PCI_TBATR_DISABLE 0x0 68 #define MPC52xx_PCI_TBATR_ENABLE 0x1 69 70 struct mpc52xx_pci { 71 u32 idr; /* PCI + 0x00 */ 72 u32 scr; /* PCI + 0x04 */ 73 u32 ccrir; /* PCI + 0x08 */ 74 u32 cr1; /* PCI + 0x0C */ 75 u32 bar0; /* PCI + 0x10 */ 76 u32 bar1; /* PCI + 0x14 */ 77 u8 reserved1[16]; /* PCI + 0x18 */ 78 u32 ccpr; /* PCI + 0x28 */ 79 u32 sid; /* PCI + 0x2C */ 80 u32 erbar; /* PCI + 0x30 */ 81 u32 cpr; /* PCI + 0x34 */ 82 u8 reserved2[4]; /* PCI + 0x38 */ 83 u32 cr2; /* PCI + 0x3C */ 84 u8 reserved3[32]; /* PCI + 0x40 */ 85 u32 gscr; /* PCI + 0x60 */ 86 u32 tbatr0; /* PCI + 0x64 */ 87 u32 tbatr1; /* PCI + 0x68 */ 88 u32 tcr; /* PCI + 0x6C */ 89 u32 iw0btar; /* PCI + 0x70 */ 90 u32 iw1btar; /* PCI + 0x74 */ 91 u32 iw2btar; /* PCI + 0x78 */ 92 u8 reserved4[4]; /* PCI + 0x7C */ 93 u32 iwcr; /* PCI + 0x80 */ 94 u32 icr; /* PCI + 0x84 */ 95 u32 isr; /* PCI + 0x88 */ 96 u32 arb; /* PCI + 0x8C */ 97 u8 reserved5[104]; /* PCI + 0x90 */ 98 u32 car; /* PCI + 0xF8 */ 99 u8 reserved6[4]; /* PCI + 0xFC */ 100 }; 101 102 /* MPC5200 device tree match tables */ 103 const struct of_device_id mpc52xx_pci_ids[] __initdata = { 104 { .type = "pci", .compatible = "fsl,mpc5200-pci", }, 105 { .type = "pci", .compatible = "mpc5200-pci", }, 106 {} 107 }; 108 109 /* ======================================================================== */ 110 /* PCI configuration acess */ 111 /* ======================================================================== */ 112 113 static int 114 mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, 115 int offset, int len, u32 *val) 116 { 117 struct pci_controller *hose = bus->sysdata; 118 u32 value; 119 120 if (ppc_md.pci_exclude_device) 121 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 122 return PCIBIOS_DEVICE_NOT_FOUND; 123 124 out_be32(hose->cfg_addr, 125 (1 << 31) | 126 (bus->number << 16) | 127 (devfn << 8) | 128 (offset & 0xfc)); 129 mb(); 130 131 #if defined(CONFIG_PPC_MPC5200_BUGFIX) 132 if (bus->number) { 133 /* workaround for the bug 435 of the MPC5200 (L25R); 134 * Don't do 32 bits config access during type-1 cycles */ 135 switch (len) { 136 case 1: 137 value = in_8(((u8 __iomem *)hose->cfg_data) + 138 (offset & 3)); 139 break; 140 case 2: 141 value = in_le16(((u16 __iomem *)hose->cfg_data) + 142 ((offset>>1) & 1)); 143 break; 144 145 default: 146 value = in_le16((u16 __iomem *)hose->cfg_data) | 147 (in_le16(((u16 __iomem *)hose->cfg_data) + 1) << 16); 148 break; 149 } 150 } 151 else 152 #endif 153 { 154 value = in_le32(hose->cfg_data); 155 156 if (len != 4) { 157 value >>= ((offset & 0x3) << 3); 158 value &= 0xffffffff >> (32 - (len << 3)); 159 } 160 } 161 162 *val = value; 163 164 out_be32(hose->cfg_addr, 0); 165 mb(); 166 167 return PCIBIOS_SUCCESSFUL; 168 } 169 170 static int 171 mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, 172 int offset, int len, u32 val) 173 { 174 struct pci_controller *hose = bus->sysdata; 175 u32 value, mask; 176 177 if (ppc_md.pci_exclude_device) 178 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 179 return PCIBIOS_DEVICE_NOT_FOUND; 180 181 out_be32(hose->cfg_addr, 182 (1 << 31) | 183 (bus->number << 16) | 184 (devfn << 8) | 185 (offset & 0xfc)); 186 mb(); 187 188 #if defined(CONFIG_PPC_MPC5200_BUGFIX) 189 if (bus->number) { 190 /* workaround for the bug 435 of the MPC5200 (L25R); 191 * Don't do 32 bits config access during type-1 cycles */ 192 switch (len) { 193 case 1: 194 out_8(((u8 __iomem *)hose->cfg_data) + 195 (offset & 3), val); 196 break; 197 case 2: 198 out_le16(((u16 __iomem *)hose->cfg_data) + 199 ((offset>>1) & 1), val); 200 break; 201 202 default: 203 out_le16((u16 __iomem *)hose->cfg_data, 204 (u16)val); 205 out_le16(((u16 __iomem *)hose->cfg_data) + 1, 206 (u16)(val>>16)); 207 break; 208 } 209 } 210 else 211 #endif 212 { 213 if (len != 4) { 214 value = in_le32(hose->cfg_data); 215 216 offset = (offset & 0x3) << 3; 217 mask = (0xffffffff >> (32 - (len << 3))); 218 mask <<= offset; 219 220 value &= ~mask; 221 val = value | ((val << offset) & mask); 222 } 223 224 out_le32(hose->cfg_data, val); 225 } 226 mb(); 227 228 out_be32(hose->cfg_addr, 0); 229 mb(); 230 231 return PCIBIOS_SUCCESSFUL; 232 } 233 234 static struct pci_ops mpc52xx_pci_ops = { 235 .read = mpc52xx_pci_read_config, 236 .write = mpc52xx_pci_write_config 237 }; 238 239 240 /* ======================================================================== */ 241 /* PCI setup */ 242 /* ======================================================================== */ 243 244 static void __init 245 mpc52xx_pci_setup(struct pci_controller *hose, 246 struct mpc52xx_pci __iomem *pci_regs) 247 { 248 struct resource *res; 249 u32 tmp; 250 int iwcr0 = 0, iwcr1 = 0, iwcr2 = 0; 251 252 pr_debug("mpc52xx_pci_setup(hose=%p, pci_regs=%p)\n", hose, pci_regs); 253 254 /* pci_process_bridge_OF_ranges() found all our addresses for us; 255 * now store them in the right places */ 256 hose->cfg_addr = &pci_regs->car; 257 hose->cfg_data = hose->io_base_virt; 258 259 /* Control regs */ 260 tmp = in_be32(&pci_regs->scr); 261 tmp |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 262 out_be32(&pci_regs->scr, tmp); 263 264 /* Memory windows */ 265 res = &hose->mem_resources[0]; 266 if (res->flags) { 267 pr_debug("mem_resource[0] = {.start=%x, .end=%x, .flags=%lx}\n", 268 res->start, res->end, res->flags); 269 out_be32(&pci_regs->iw0btar, 270 MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start, 271 res->end - res->start + 1)); 272 iwcr0 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM; 273 if (res->flags & IORESOURCE_PREFETCH) 274 iwcr0 |= MPC52xx_PCI_IWCR_READ_MULTI; 275 else 276 iwcr0 |= MPC52xx_PCI_IWCR_READ; 277 } 278 279 res = &hose->mem_resources[1]; 280 if (res->flags) { 281 pr_debug("mem_resource[1] = {.start=%x, .end=%x, .flags=%lx}\n", 282 res->start, res->end, res->flags); 283 out_be32(&pci_regs->iw1btar, 284 MPC52xx_PCI_IWBTAR_TRANSLATION(res->start, res->start, 285 res->end - res->start + 1)); 286 iwcr1 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_MEM; 287 if (res->flags & IORESOURCE_PREFETCH) 288 iwcr1 |= MPC52xx_PCI_IWCR_READ_MULTI; 289 else 290 iwcr1 |= MPC52xx_PCI_IWCR_READ; 291 } 292 293 /* IO resources */ 294 res = &hose->io_resource; 295 if (!res) { 296 printk(KERN_ERR "%s: Didn't find IO resources\n", __FILE__); 297 return; 298 } 299 pr_debug(".io_resource={.start=%x,.end=%x,.flags=%lx} " 300 ".io_base_phys=0x%p\n", 301 res->start, res->end, res->flags, (void*)hose->io_base_phys); 302 out_be32(&pci_regs->iw2btar, 303 MPC52xx_PCI_IWBTAR_TRANSLATION(hose->io_base_phys, 304 res->start, 305 res->end - res->start + 1)); 306 iwcr2 = MPC52xx_PCI_IWCR_ENABLE | MPC52xx_PCI_IWCR_IO; 307 308 /* Set all the IWCR fields at once; they're in the same reg */ 309 out_be32(&pci_regs->iwcr, MPC52xx_PCI_IWCR_PACK(iwcr0, iwcr1, iwcr2)); 310 311 out_be32(&pci_regs->tbatr0, 312 MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_IO ); 313 out_be32(&pci_regs->tbatr1, 314 MPC52xx_PCI_TBATR_ENABLE | MPC52xx_PCI_TARGET_MEM ); 315 316 out_be32(&pci_regs->tcr, MPC52xx_PCI_TCR_LD); 317 318 tmp = in_be32(&pci_regs->gscr); 319 #if 0 320 /* Reset the exteral bus ( internal PCI controller is NOT resetted ) */ 321 /* Not necessary and can be a bad thing if for example the bootloader 322 is displaying a splash screen or ... Just left here for 323 documentation purpose if anyone need it */ 324 out_be32(&pci_regs->gscr, tmp | MPC52xx_PCI_GSCR_PR); 325 udelay(50); 326 #endif 327 328 /* Make sure the PCI bridge is out of reset */ 329 out_be32(&pci_regs->gscr, tmp & ~MPC52xx_PCI_GSCR_PR); 330 } 331 332 static void 333 mpc52xx_pci_fixup_resources(struct pci_dev *dev) 334 { 335 int i; 336 337 pr_debug("mpc52xx_pci_fixup_resources() %.4x:%.4x\n", 338 dev->vendor, dev->device); 339 340 /* We don't rely on boot loader for PCI and resets all 341 devices */ 342 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 343 struct resource *res = &dev->resource[i]; 344 if (res->end > res->start) { /* Only valid resources */ 345 res->end -= res->start; 346 res->start = 0; 347 res->flags |= IORESOURCE_UNSET; 348 } 349 } 350 351 /* The PCI Host bridge of MPC52xx has a prefetch memory resource 352 fixed to 1Gb. Doesn't fit in the resource system so we remove it */ 353 if ( (dev->vendor == PCI_VENDOR_ID_MOTOROLA) && 354 ( dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200 355 || dev->device == PCI_DEVICE_ID_MOTOROLA_MPC5200B) ) { 356 struct resource *res = &dev->resource[1]; 357 res->start = res->end = res->flags = 0; 358 } 359 } 360 361 int __init 362 mpc52xx_add_bridge(struct device_node *node) 363 { 364 int len; 365 struct mpc52xx_pci __iomem *pci_regs; 366 struct pci_controller *hose; 367 const int *bus_range; 368 struct resource rsrc; 369 370 pr_debug("Adding MPC52xx PCI host bridge %s\n", node->full_name); 371 372 ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS; 373 374 if (of_address_to_resource(node, 0, &rsrc) != 0) { 375 printk(KERN_ERR "Can't get %s resources\n", node->full_name); 376 return -EINVAL; 377 } 378 379 bus_range = of_get_property(node, "bus-range", &len); 380 if (bus_range == NULL || len < 2 * sizeof(int)) { 381 printk(KERN_WARNING "Can't get %s bus-range, assume bus 0\n", 382 node->full_name); 383 bus_range = NULL; 384 } 385 386 /* There are some PCI quirks on the 52xx, register the hook to 387 * fix them. */ 388 ppc_md.pcibios_fixup_resources = mpc52xx_pci_fixup_resources; 389 390 /* Alloc and initialize the pci controller. Values in the device 391 * tree are needed to configure the 52xx PCI controller. Rather 392 * than parse the tree here, let pci_process_bridge_OF_ranges() 393 * do it for us and extract the values after the fact */ 394 hose = pcibios_alloc_controller(node); 395 if (!hose) 396 return -ENOMEM; 397 398 hose->first_busno = bus_range ? bus_range[0] : 0; 399 hose->last_busno = bus_range ? bus_range[1] : 0xff; 400 401 hose->ops = &mpc52xx_pci_ops; 402 403 pci_regs = ioremap(rsrc.start, rsrc.end - rsrc.start + 1); 404 if (!pci_regs) 405 return -ENOMEM; 406 407 pci_process_bridge_OF_ranges(hose, node, 1); 408 409 /* Finish setting up PCI using values obtained by 410 * pci_proces_bridge_OF_ranges */ 411 mpc52xx_pci_setup(hose, pci_regs); 412 413 return 0; 414 } 415 416 void __init mpc52xx_setup_pci(void) 417 { 418 struct device_node *pci; 419 420 pci = of_find_matching_node(NULL, mpc52xx_pci_ids); 421 if (!pci) 422 return; 423 424 mpc52xx_add_bridge(pci); 425 of_node_put(pci); 426 } 427