1 /* 2 * MPC5200 General Purpose Timer device driver 3 * 4 * Copyright (c) 2009 Secret Lab Technologies Ltd. 5 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * This file is a driver for the the General Purpose Timer (gpt) devices 13 * found on the MPC5200 SoC. Each timer has an IO pin which can be used 14 * for GPIO or can be used to raise interrupts. The timer function can 15 * be used independently from the IO pin, or it can be used to control 16 * output signals or measure input signals. 17 * 18 * This driver supports the GPIO and IRQ controller functions of the GPT 19 * device. Timer functions are not yet supported. 20 * 21 * The timer gpt0 can be used as watchdog (wdt). If the wdt mode is used, 22 * this prevents the use of any gpt0 gpt function (i.e. they will fail with 23 * -EBUSY). Thus, the safety wdt function always has precedence over the gpt 24 * function. If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT, 25 * this means that gpt0 is locked in wdt mode until the next reboot - this 26 * may be a requirement in safety applications. 27 * 28 * To use the GPIO function, the following two properties must be added 29 * to the device tree node for the gpt device (typically in the .dts file 30 * for the board): 31 * gpio-controller; 32 * #gpio-cells = < 2 >; 33 * This driver will register the GPIO pin if it finds the gpio-controller 34 * property in the device tree. 35 * 36 * To use the IRQ controller function, the following two properties must 37 * be added to the device tree node for the gpt device: 38 * interrupt-controller; 39 * #interrupt-cells = < 1 >; 40 * The IRQ controller binding only uses one cell to specify the interrupt, 41 * and the IRQ flags are encoded in the cell. A cell is not used to encode 42 * the IRQ number because the GPT only has a single IRQ source. For flags, 43 * a value of '1' means rising edge sensitive and '2' means falling edge. 44 * 45 * The GPIO and the IRQ controller functions can be used at the same time, 46 * but in this use case the IO line will only work as an input. Trying to 47 * use it as a GPIO output will not work. 48 * 49 * When using the GPIO line as an output, it can either be driven as normal 50 * IO, or it can be an Open Collector (OC) output. At the moment it is the 51 * responsibility of either the bootloader or the platform setup code to set 52 * the output mode. This driver does not change the output mode setting. 53 */ 54 55 #include <linux/device.h> 56 #include <linux/irq.h> 57 #include <linux/interrupt.h> 58 #include <linux/io.h> 59 #include <linux/list.h> 60 #include <linux/mutex.h> 61 #include <linux/of.h> 62 #include <linux/of_platform.h> 63 #include <linux/of_gpio.h> 64 #include <linux/kernel.h> 65 #include <linux/slab.h> 66 #include <linux/fs.h> 67 #include <linux/watchdog.h> 68 #include <linux/miscdevice.h> 69 #include <linux/uaccess.h> 70 #include <linux/module.h> 71 #include <asm/div64.h> 72 #include <asm/mpc52xx.h> 73 74 MODULE_DESCRIPTION("Freescale MPC52xx gpt driver"); 75 MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß"); 76 MODULE_LICENSE("GPL"); 77 78 /** 79 * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver 80 * @dev: pointer to device structure 81 * @regs: virtual address of GPT registers 82 * @lock: spinlock to coordinate between different functions. 83 * @gc: gpio_chip instance structure; used when GPIO is enabled 84 * @irqhost: Pointer to irq_host instance; used when IRQ mode is supported 85 * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates 86 * if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates 87 * if the timer is actively used as wdt which blocks gpt functions 88 */ 89 struct mpc52xx_gpt_priv { 90 struct list_head list; /* List of all GPT devices */ 91 struct device *dev; 92 struct mpc52xx_gpt __iomem *regs; 93 spinlock_t lock; 94 struct irq_host *irqhost; 95 u32 ipb_freq; 96 u8 wdt_mode; 97 98 #if defined(CONFIG_GPIOLIB) 99 struct gpio_chip gc; 100 #endif 101 }; 102 103 LIST_HEAD(mpc52xx_gpt_list); 104 DEFINE_MUTEX(mpc52xx_gpt_list_mutex); 105 106 #define MPC52xx_GPT_MODE_MS_MASK (0x07) 107 #define MPC52xx_GPT_MODE_MS_IC (0x01) 108 #define MPC52xx_GPT_MODE_MS_OC (0x02) 109 #define MPC52xx_GPT_MODE_MS_PWM (0x03) 110 #define MPC52xx_GPT_MODE_MS_GPIO (0x04) 111 112 #define MPC52xx_GPT_MODE_GPIO_MASK (0x30) 113 #define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20) 114 #define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30) 115 116 #define MPC52xx_GPT_MODE_COUNTER_ENABLE (0x1000) 117 #define MPC52xx_GPT_MODE_CONTINUOUS (0x0400) 118 #define MPC52xx_GPT_MODE_OPEN_DRAIN (0x0200) 119 #define MPC52xx_GPT_MODE_IRQ_EN (0x0100) 120 #define MPC52xx_GPT_MODE_WDT_EN (0x8000) 121 122 #define MPC52xx_GPT_MODE_ICT_MASK (0x030000) 123 #define MPC52xx_GPT_MODE_ICT_RISING (0x010000) 124 #define MPC52xx_GPT_MODE_ICT_FALLING (0x020000) 125 #define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000) 126 127 #define MPC52xx_GPT_MODE_WDT_PING (0xa5) 128 129 #define MPC52xx_GPT_STATUS_IRQMASK (0x000f) 130 131 #define MPC52xx_GPT_CAN_WDT (1 << 0) 132 #define MPC52xx_GPT_IS_WDT (1 << 1) 133 134 135 /* --------------------------------------------------------------------- 136 * Cascaded interrupt controller hooks 137 */ 138 139 static void mpc52xx_gpt_irq_unmask(struct irq_data *d) 140 { 141 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); 142 unsigned long flags; 143 144 spin_lock_irqsave(&gpt->lock, flags); 145 setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); 146 spin_unlock_irqrestore(&gpt->lock, flags); 147 } 148 149 static void mpc52xx_gpt_irq_mask(struct irq_data *d) 150 { 151 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); 152 unsigned long flags; 153 154 spin_lock_irqsave(&gpt->lock, flags); 155 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN); 156 spin_unlock_irqrestore(&gpt->lock, flags); 157 } 158 159 static void mpc52xx_gpt_irq_ack(struct irq_data *d) 160 { 161 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); 162 163 out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK); 164 } 165 166 static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type) 167 { 168 struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d); 169 unsigned long flags; 170 u32 reg; 171 172 dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type); 173 174 spin_lock_irqsave(&gpt->lock, flags); 175 reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK; 176 if (flow_type & IRQF_TRIGGER_RISING) 177 reg |= MPC52xx_GPT_MODE_ICT_RISING; 178 if (flow_type & IRQF_TRIGGER_FALLING) 179 reg |= MPC52xx_GPT_MODE_ICT_FALLING; 180 out_be32(&gpt->regs->mode, reg); 181 spin_unlock_irqrestore(&gpt->lock, flags); 182 183 return 0; 184 } 185 186 static struct irq_chip mpc52xx_gpt_irq_chip = { 187 .name = "MPC52xx GPT", 188 .irq_unmask = mpc52xx_gpt_irq_unmask, 189 .irq_mask = mpc52xx_gpt_irq_mask, 190 .irq_ack = mpc52xx_gpt_irq_ack, 191 .irq_set_type = mpc52xx_gpt_irq_set_type, 192 }; 193 194 void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc) 195 { 196 struct mpc52xx_gpt_priv *gpt = irq_get_handler_data(virq); 197 int sub_virq; 198 u32 status; 199 200 status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK; 201 if (status) { 202 sub_virq = irq_linear_revmap(gpt->irqhost, 0); 203 generic_handle_irq(sub_virq); 204 } 205 } 206 207 static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq, 208 irq_hw_number_t hw) 209 { 210 struct mpc52xx_gpt_priv *gpt = h->host_data; 211 212 dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq); 213 irq_set_chip_data(virq, gpt); 214 irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq); 215 216 return 0; 217 } 218 219 static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct, 220 const u32 *intspec, unsigned int intsize, 221 irq_hw_number_t *out_hwirq, 222 unsigned int *out_flags) 223 { 224 struct mpc52xx_gpt_priv *gpt = h->host_data; 225 226 dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]); 227 228 if ((intsize < 1) || (intspec[0] > 3)) { 229 dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name); 230 return -EINVAL; 231 } 232 233 *out_hwirq = 0; /* The GPT only has 1 IRQ line */ 234 *out_flags = intspec[0]; 235 236 return 0; 237 } 238 239 static struct irq_host_ops mpc52xx_gpt_irq_ops = { 240 .map = mpc52xx_gpt_irq_map, 241 .xlate = mpc52xx_gpt_irq_xlate, 242 }; 243 244 static void 245 mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node) 246 { 247 int cascade_virq; 248 unsigned long flags; 249 u32 mode; 250 251 cascade_virq = irq_of_parse_and_map(node, 0); 252 if (!cascade_virq) 253 return; 254 255 gpt->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1, 256 &mpc52xx_gpt_irq_ops, -1); 257 if (!gpt->irqhost) { 258 dev_err(gpt->dev, "irq_alloc_host() failed\n"); 259 return; 260 } 261 262 gpt->irqhost->host_data = gpt; 263 irq_set_handler_data(cascade_virq, gpt); 264 irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade); 265 266 /* If the GPT is currently disabled, then change it to be in Input 267 * Capture mode. If the mode is non-zero, then the pin could be 268 * already in use for something. */ 269 spin_lock_irqsave(&gpt->lock, flags); 270 mode = in_be32(&gpt->regs->mode); 271 if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0) 272 out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC); 273 spin_unlock_irqrestore(&gpt->lock, flags); 274 275 dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq); 276 } 277 278 279 /* --------------------------------------------------------------------- 280 * GPIOLIB hooks 281 */ 282 #if defined(CONFIG_GPIOLIB) 283 static inline struct mpc52xx_gpt_priv *gc_to_mpc52xx_gpt(struct gpio_chip *gc) 284 { 285 return container_of(gc, struct mpc52xx_gpt_priv, gc); 286 } 287 288 static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio) 289 { 290 struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc); 291 292 return (in_be32(&gpt->regs->status) >> 8) & 1; 293 } 294 295 static void 296 mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v) 297 { 298 struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc); 299 unsigned long flags; 300 u32 r; 301 302 dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v); 303 r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW; 304 305 spin_lock_irqsave(&gpt->lock, flags); 306 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r); 307 spin_unlock_irqrestore(&gpt->lock, flags); 308 } 309 310 static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 311 { 312 struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc); 313 unsigned long flags; 314 315 dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio); 316 317 spin_lock_irqsave(&gpt->lock, flags); 318 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK); 319 spin_unlock_irqrestore(&gpt->lock, flags); 320 321 return 0; 322 } 323 324 static int 325 mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 326 { 327 mpc52xx_gpt_gpio_set(gc, gpio, val); 328 return 0; 329 } 330 331 static void 332 mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node) 333 { 334 int rc; 335 336 /* Only setup GPIO if the device tree claims the GPT is 337 * a GPIO controller */ 338 if (!of_find_property(node, "gpio-controller", NULL)) 339 return; 340 341 gpt->gc.label = kstrdup(node->full_name, GFP_KERNEL); 342 if (!gpt->gc.label) { 343 dev_err(gpt->dev, "out of memory\n"); 344 return; 345 } 346 347 gpt->gc.ngpio = 1; 348 gpt->gc.direction_input = mpc52xx_gpt_gpio_dir_in; 349 gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out; 350 gpt->gc.get = mpc52xx_gpt_gpio_get; 351 gpt->gc.set = mpc52xx_gpt_gpio_set; 352 gpt->gc.base = -1; 353 gpt->gc.of_node = node; 354 355 /* Setup external pin in GPIO mode */ 356 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK, 357 MPC52xx_GPT_MODE_MS_GPIO); 358 359 rc = gpiochip_add(&gpt->gc); 360 if (rc) 361 dev_err(gpt->dev, "gpiochip_add() failed; rc=%i\n", rc); 362 363 dev_dbg(gpt->dev, "%s() complete.\n", __func__); 364 } 365 #else /* defined(CONFIG_GPIOLIB) */ 366 static void 367 mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { } 368 #endif /* defined(CONFIG_GPIOLIB) */ 369 370 /*********************************************************************** 371 * Timer API 372 */ 373 374 /** 375 * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number 376 * @irq: irq of timer. 377 */ 378 struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq) 379 { 380 struct mpc52xx_gpt_priv *gpt; 381 struct list_head *pos; 382 383 /* Iterate over the list of timers looking for a matching device */ 384 mutex_lock(&mpc52xx_gpt_list_mutex); 385 list_for_each(pos, &mpc52xx_gpt_list) { 386 gpt = container_of(pos, struct mpc52xx_gpt_priv, list); 387 if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) { 388 mutex_unlock(&mpc52xx_gpt_list_mutex); 389 return gpt; 390 } 391 } 392 mutex_unlock(&mpc52xx_gpt_list_mutex); 393 394 return NULL; 395 } 396 EXPORT_SYMBOL(mpc52xx_gpt_from_irq); 397 398 static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period, 399 int continuous, int as_wdt) 400 { 401 u32 clear, set; 402 u64 clocks; 403 u32 prescale; 404 unsigned long flags; 405 406 clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS; 407 set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE; 408 if (as_wdt) { 409 clear |= MPC52xx_GPT_MODE_IRQ_EN; 410 set |= MPC52xx_GPT_MODE_WDT_EN; 411 } else if (continuous) 412 set |= MPC52xx_GPT_MODE_CONTINUOUS; 413 414 /* Determine the number of clocks in the requested period. 64 bit 415 * arithmatic is done here to preserve the precision until the value 416 * is scaled back down into the u32 range. Period is in 'ns', bus 417 * frequency is in Hz. */ 418 clocks = period * (u64)gpt->ipb_freq; 419 do_div(clocks, 1000000000); /* Scale it down to ns range */ 420 421 /* This device cannot handle a clock count greater than 32 bits */ 422 if (clocks > 0xffffffff) 423 return -EINVAL; 424 425 /* Calculate the prescaler and count values from the clocks value. 426 * 'clocks' is the number of clock ticks in the period. The timer 427 * has 16 bit precision and a 16 bit prescaler. Prescaler is 428 * calculated by integer dividing the clocks by 0x10000 (shifting 429 * down 16 bits) to obtain the smallest possible divisor for clocks 430 * to get a 16 bit count value. 431 * 432 * Note: the prescale register is '1' based, not '0' based. ie. a 433 * value of '1' means divide the clock by one. 0xffff divides the 434 * clock by 0xffff. '0x0000' does not divide by zero, but wraps 435 * around and divides by 0x10000. That is why prescale must be 436 * a u32 variable, not a u16, for this calculation. */ 437 prescale = (clocks >> 16) + 1; 438 do_div(clocks, prescale); 439 if (clocks > 0xffff) { 440 pr_err("calculation error; prescale:%x clocks:%llx\n", 441 prescale, clocks); 442 return -EINVAL; 443 } 444 445 /* Set and enable the timer, reject an attempt to use a wdt as gpt */ 446 spin_lock_irqsave(&gpt->lock, flags); 447 if (as_wdt) 448 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT; 449 else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) { 450 spin_unlock_irqrestore(&gpt->lock, flags); 451 return -EBUSY; 452 } 453 out_be32(&gpt->regs->count, prescale << 16 | clocks); 454 clrsetbits_be32(&gpt->regs->mode, clear, set); 455 spin_unlock_irqrestore(&gpt->lock, flags); 456 457 return 0; 458 } 459 460 /** 461 * mpc52xx_gpt_start_timer - Set and enable the GPT timer 462 * @gpt: Pointer to gpt private data structure 463 * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock 464 * @continuous: set to 1 to make timer continuous free running 465 * 466 * An interrupt will be generated every time the timer fires 467 */ 468 int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period, 469 int continuous) 470 { 471 return mpc52xx_gpt_do_start(gpt, period, continuous, 0); 472 } 473 EXPORT_SYMBOL(mpc52xx_gpt_start_timer); 474 475 /** 476 * mpc52xx_gpt_stop_timer - Stop a gpt 477 * @gpt: Pointer to gpt private data structure 478 * 479 * Returns an error if attempting to stop a wdt 480 */ 481 int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt) 482 { 483 unsigned long flags; 484 485 /* reject the operation if the timer is used as watchdog (gpt 0 only) */ 486 spin_lock_irqsave(&gpt->lock, flags); 487 if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) { 488 spin_unlock_irqrestore(&gpt->lock, flags); 489 return -EBUSY; 490 } 491 492 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE); 493 spin_unlock_irqrestore(&gpt->lock, flags); 494 return 0; 495 } 496 EXPORT_SYMBOL(mpc52xx_gpt_stop_timer); 497 498 /** 499 * mpc52xx_gpt_timer_period - Read the timer period 500 * @gpt: Pointer to gpt private data structure 501 * 502 * Returns the timer period in ns 503 */ 504 u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt) 505 { 506 u64 period; 507 u64 prescale; 508 unsigned long flags; 509 510 spin_lock_irqsave(&gpt->lock, flags); 511 period = in_be32(&gpt->regs->count); 512 spin_unlock_irqrestore(&gpt->lock, flags); 513 514 prescale = period >> 16; 515 period &= 0xffff; 516 if (prescale == 0) 517 prescale = 0x10000; 518 period = period * prescale * 1000000000ULL; 519 do_div(period, (u64)gpt->ipb_freq); 520 return period; 521 } 522 EXPORT_SYMBOL(mpc52xx_gpt_timer_period); 523 524 #if defined(CONFIG_MPC5200_WDT) 525 /*********************************************************************** 526 * Watchdog API for gpt0 527 */ 528 529 #define WDT_IDENTITY "mpc52xx watchdog on GPT0" 530 531 /* wdt_is_active stores wether or not the /dev/watchdog device is opened */ 532 static unsigned long wdt_is_active; 533 534 /* wdt-capable gpt */ 535 static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt; 536 537 /* low-level wdt functions */ 538 static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt) 539 { 540 unsigned long flags; 541 542 spin_lock_irqsave(&gpt_wdt->lock, flags); 543 out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING); 544 spin_unlock_irqrestore(&gpt_wdt->lock, flags); 545 } 546 547 /* wdt misc device api */ 548 static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data, 549 size_t len, loff_t *ppos) 550 { 551 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; 552 mpc52xx_gpt_wdt_ping(gpt_wdt); 553 return 0; 554 } 555 556 static const struct watchdog_info mpc5200_wdt_info = { 557 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, 558 .identity = WDT_IDENTITY, 559 }; 560 561 static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd, 562 unsigned long arg) 563 { 564 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; 565 int __user *data = (int __user *)arg; 566 int timeout; 567 u64 real_timeout; 568 int ret = 0; 569 570 switch (cmd) { 571 case WDIOC_GETSUPPORT: 572 ret = copy_to_user(data, &mpc5200_wdt_info, 573 sizeof(mpc5200_wdt_info)); 574 if (ret) 575 ret = -EFAULT; 576 break; 577 578 case WDIOC_GETSTATUS: 579 case WDIOC_GETBOOTSTATUS: 580 ret = put_user(0, data); 581 break; 582 583 case WDIOC_KEEPALIVE: 584 mpc52xx_gpt_wdt_ping(gpt_wdt); 585 break; 586 587 case WDIOC_SETTIMEOUT: 588 ret = get_user(timeout, data); 589 if (ret) 590 break; 591 real_timeout = (u64) timeout * 1000000000ULL; 592 ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1); 593 if (ret) 594 break; 595 /* fall through and return the timeout */ 596 597 case WDIOC_GETTIMEOUT: 598 /* we need to round here as to avoid e.g. the following 599 * situation: 600 * - timeout requested is 1 second; 601 * - real timeout @33MHz is 999997090ns 602 * - the int divide by 10^9 will return 0. 603 */ 604 real_timeout = 605 mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL; 606 do_div(real_timeout, 1000000000ULL); 607 timeout = (int) real_timeout; 608 ret = put_user(timeout, data); 609 break; 610 611 default: 612 ret = -ENOTTY; 613 } 614 return ret; 615 } 616 617 static int mpc52xx_wdt_open(struct inode *inode, struct file *file) 618 { 619 int ret; 620 621 /* sanity check */ 622 if (!mpc52xx_gpt_wdt) 623 return -ENODEV; 624 625 /* /dev/watchdog can only be opened once */ 626 if (test_and_set_bit(0, &wdt_is_active)) 627 return -EBUSY; 628 629 /* Set and activate the watchdog with 30 seconds timeout */ 630 ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL, 631 0, 1); 632 if (ret) { 633 clear_bit(0, &wdt_is_active); 634 return ret; 635 } 636 637 file->private_data = mpc52xx_gpt_wdt; 638 return nonseekable_open(inode, file); 639 } 640 641 static int mpc52xx_wdt_release(struct inode *inode, struct file *file) 642 { 643 /* note: releasing the wdt in NOWAYOUT-mode does not stop it */ 644 #if !defined(CONFIG_WATCHDOG_NOWAYOUT) 645 struct mpc52xx_gpt_priv *gpt_wdt = file->private_data; 646 unsigned long flags; 647 648 spin_lock_irqsave(&gpt_wdt->lock, flags); 649 clrbits32(&gpt_wdt->regs->mode, 650 MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN); 651 gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT; 652 spin_unlock_irqrestore(&gpt_wdt->lock, flags); 653 #endif 654 clear_bit(0, &wdt_is_active); 655 return 0; 656 } 657 658 659 static const struct file_operations mpc52xx_wdt_fops = { 660 .owner = THIS_MODULE, 661 .llseek = no_llseek, 662 .write = mpc52xx_wdt_write, 663 .unlocked_ioctl = mpc52xx_wdt_ioctl, 664 .open = mpc52xx_wdt_open, 665 .release = mpc52xx_wdt_release, 666 }; 667 668 static struct miscdevice mpc52xx_wdt_miscdev = { 669 .minor = WATCHDOG_MINOR, 670 .name = "watchdog", 671 .fops = &mpc52xx_wdt_fops, 672 }; 673 674 static int __devinit mpc52xx_gpt_wdt_init(void) 675 { 676 int err; 677 678 /* try to register the watchdog misc device */ 679 err = misc_register(&mpc52xx_wdt_miscdev); 680 if (err) 681 pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY); 682 else 683 pr_info("%s: watchdog device registered\n", WDT_IDENTITY); 684 return err; 685 } 686 687 static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt, 688 const u32 *period) 689 { 690 u64 real_timeout; 691 692 /* remember the gpt for the wdt operation */ 693 mpc52xx_gpt_wdt = gpt; 694 695 /* configure the wdt if the device tree contained a timeout */ 696 if (!period || *period == 0) 697 return 0; 698 699 real_timeout = (u64) *period * 1000000000ULL; 700 if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1)) 701 dev_warn(gpt->dev, "starting as wdt failed\n"); 702 else 703 dev_info(gpt->dev, "watchdog set to %us timeout\n", *period); 704 return 0; 705 } 706 707 #else 708 709 static int __devinit mpc52xx_gpt_wdt_init(void) 710 { 711 return 0; 712 } 713 714 static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt, 715 const u32 *period) 716 { 717 return 0; 718 } 719 720 #endif /* CONFIG_MPC5200_WDT */ 721 722 /* --------------------------------------------------------------------- 723 * of_platform bus binding code 724 */ 725 static int __devinit mpc52xx_gpt_probe(struct platform_device *ofdev) 726 { 727 struct mpc52xx_gpt_priv *gpt; 728 729 gpt = kzalloc(sizeof *gpt, GFP_KERNEL); 730 if (!gpt) 731 return -ENOMEM; 732 733 spin_lock_init(&gpt->lock); 734 gpt->dev = &ofdev->dev; 735 gpt->ipb_freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); 736 gpt->regs = of_iomap(ofdev->dev.of_node, 0); 737 if (!gpt->regs) { 738 kfree(gpt); 739 return -ENOMEM; 740 } 741 742 dev_set_drvdata(&ofdev->dev, gpt); 743 744 mpc52xx_gpt_gpio_setup(gpt, ofdev->dev.of_node); 745 mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node); 746 747 mutex_lock(&mpc52xx_gpt_list_mutex); 748 list_add(&gpt->list, &mpc52xx_gpt_list); 749 mutex_unlock(&mpc52xx_gpt_list_mutex); 750 751 /* check if this device could be a watchdog */ 752 if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) || 753 of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) { 754 const u32 *on_boot_wdt; 755 756 gpt->wdt_mode = MPC52xx_GPT_CAN_WDT; 757 on_boot_wdt = of_get_property(ofdev->dev.of_node, 758 "fsl,wdt-on-boot", NULL); 759 if (on_boot_wdt) { 760 dev_info(gpt->dev, "used as watchdog\n"); 761 gpt->wdt_mode |= MPC52xx_GPT_IS_WDT; 762 } else 763 dev_info(gpt->dev, "can function as watchdog\n"); 764 mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt); 765 } 766 767 return 0; 768 } 769 770 static int mpc52xx_gpt_remove(struct platform_device *ofdev) 771 { 772 return -EBUSY; 773 } 774 775 static const struct of_device_id mpc52xx_gpt_match[] = { 776 { .compatible = "fsl,mpc5200-gpt", }, 777 778 /* Depreciated compatible values; don't use for new dts files */ 779 { .compatible = "fsl,mpc5200-gpt-gpio", }, 780 { .compatible = "mpc5200-gpt", }, 781 {} 782 }; 783 784 static struct platform_driver mpc52xx_gpt_driver = { 785 .driver = { 786 .name = "mpc52xx-gpt", 787 .owner = THIS_MODULE, 788 .of_match_table = mpc52xx_gpt_match, 789 }, 790 .probe = mpc52xx_gpt_probe, 791 .remove = mpc52xx_gpt_remove, 792 }; 793 794 static int __init mpc52xx_gpt_init(void) 795 { 796 return platform_driver_register(&mpc52xx_gpt_driver); 797 } 798 799 /* Make sure GPIOs and IRQs get set up before anyone tries to use them */ 800 subsys_initcall(mpc52xx_gpt_init); 801 device_initcall(mpc52xx_gpt_wdt_init); 802