1 /* 2 * Support for 'media5200-platform' compatible boards. 3 * 4 * Copyright (C) 2008 Secret Lab Technologies Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * Description: 12 * This code implements support for the Freescape Media5200 platform 13 * (built around the MPC5200 SoC). 14 * 15 * Notable characteristic of the Media5200 is the presence of an FPGA 16 * that has all external IRQ lines routed through it. This file implements 17 * a cascaded interrupt controller driver which attaches itself to the 18 * Virtual IRQ subsystem after the primary mpc5200 interrupt controller 19 * is initialized. 20 * 21 */ 22 23 #undef DEBUG 24 25 #include <linux/irq.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <asm/time.h> 29 #include <asm/prom.h> 30 #include <asm/machdep.h> 31 #include <asm/mpc52xx.h> 32 33 static struct of_device_id mpc5200_gpio_ids[] __initdata = { 34 { .compatible = "fsl,mpc5200-gpio", }, 35 { .compatible = "mpc5200-gpio", }, 36 {} 37 }; 38 39 /* FPGA register set */ 40 #define MEDIA5200_IRQ_ENABLE (0x40c) 41 #define MEDIA5200_IRQ_STATUS (0x410) 42 #define MEDIA5200_NUM_IRQS (6) 43 #define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS) 44 45 struct media5200_irq { 46 void __iomem *regs; 47 spinlock_t lock; 48 struct irq_host *irqhost; 49 }; 50 struct media5200_irq media5200_irq; 51 52 static void media5200_irq_unmask(struct irq_data *d) 53 { 54 unsigned long flags; 55 u32 val; 56 57 spin_lock_irqsave(&media5200_irq.lock, flags); 58 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); 59 val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[d->irq].hwirq); 60 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); 61 spin_unlock_irqrestore(&media5200_irq.lock, flags); 62 } 63 64 static void media5200_irq_mask(struct irq_data *d) 65 { 66 unsigned long flags; 67 u32 val; 68 69 spin_lock_irqsave(&media5200_irq.lock, flags); 70 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); 71 val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[d->irq].hwirq)); 72 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); 73 spin_unlock_irqrestore(&media5200_irq.lock, flags); 74 } 75 76 static struct irq_chip media5200_irq_chip = { 77 .name = "Media5200 FPGA", 78 .irq_unmask = media5200_irq_unmask, 79 .irq_mask = media5200_irq_mask, 80 .irq_mask_ack = media5200_irq_mask, 81 }; 82 83 void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) 84 { 85 struct irq_chip *chip = get_irq_desc_chip(desc); 86 int sub_virq, val; 87 u32 status, enable; 88 89 /* Mask off the cascaded IRQ */ 90 raw_spin_lock(&desc->lock); 91 chip->irq_mask(&desc->irq_data); 92 raw_spin_unlock(&desc->lock); 93 94 /* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs 95 * are pending. 'ffs()' is 1 based */ 96 status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); 97 enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS); 98 val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT); 99 if (val) { 100 sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1); 101 /* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n", 102 * __func__, virq, status, enable, val - 1, sub_virq); 103 */ 104 generic_handle_irq(sub_virq); 105 } 106 107 /* Processing done; can reenable the cascade now */ 108 raw_spin_lock(&desc->lock); 109 chip->irq_ack(&desc->irq_data); 110 if (!(desc->status & IRQ_DISABLED)) 111 chip->irq_unmask(&desc->irq_data); 112 raw_spin_unlock(&desc->lock); 113 } 114 115 static int media5200_irq_map(struct irq_host *h, unsigned int virq, 116 irq_hw_number_t hw) 117 { 118 struct irq_desc *desc = irq_to_desc(virq); 119 120 pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw); 121 set_irq_chip_data(virq, &media5200_irq); 122 set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq); 123 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 124 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 125 desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL; 126 127 return 0; 128 } 129 130 static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct, 131 const u32 *intspec, unsigned int intsize, 132 irq_hw_number_t *out_hwirq, 133 unsigned int *out_flags) 134 { 135 if (intsize != 2) 136 return -1; 137 138 pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]); 139 *out_hwirq = intspec[1]; 140 *out_flags = IRQ_TYPE_NONE; 141 return 0; 142 } 143 144 static struct irq_host_ops media5200_irq_ops = { 145 .map = media5200_irq_map, 146 .xlate = media5200_irq_xlate, 147 }; 148 149 /* 150 * Setup Media5200 IRQ mapping 151 */ 152 static void __init media5200_init_irq(void) 153 { 154 struct device_node *fpga_np; 155 int cascade_virq; 156 157 /* First setup the regular MPC5200 interrupt controller */ 158 mpc52xx_init_irq(); 159 160 /* Now find the FPGA IRQ */ 161 fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga"); 162 if (!fpga_np) 163 goto out; 164 pr_debug("%s: found fpga node: %s\n", __func__, fpga_np->full_name); 165 166 media5200_irq.regs = of_iomap(fpga_np, 0); 167 if (!media5200_irq.regs) 168 goto out; 169 pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs); 170 171 cascade_virq = irq_of_parse_and_map(fpga_np, 0); 172 if (!cascade_virq) 173 goto out; 174 pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq); 175 176 /* Disable all FPGA IRQs */ 177 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0); 178 179 spin_lock_init(&media5200_irq.lock); 180 181 media5200_irq.irqhost = irq_alloc_host(fpga_np, IRQ_HOST_MAP_LINEAR, 182 MEDIA5200_NUM_IRQS, 183 &media5200_irq_ops, -1); 184 if (!media5200_irq.irqhost) 185 goto out; 186 pr_debug("%s: allocated irqhost\n", __func__); 187 188 media5200_irq.irqhost->host_data = &media5200_irq; 189 190 set_irq_data(cascade_virq, &media5200_irq); 191 set_irq_chained_handler(cascade_virq, media5200_irq_cascade); 192 193 return; 194 195 out: 196 pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n"); 197 } 198 199 /* 200 * Setup the architecture 201 */ 202 static void __init media5200_setup_arch(void) 203 { 204 205 struct device_node *np; 206 struct mpc52xx_gpio __iomem *gpio; 207 u32 port_config; 208 209 if (ppc_md.progress) 210 ppc_md.progress("media5200_setup_arch()", 0); 211 212 /* Map important registers from the internal memory map */ 213 mpc52xx_map_common_devices(); 214 215 /* Some mpc5200 & mpc5200b related configuration */ 216 mpc5200_setup_xlb_arbiter(); 217 218 mpc52xx_setup_pci(); 219 220 np = of_find_matching_node(NULL, mpc5200_gpio_ids); 221 gpio = of_iomap(np, 0); 222 of_node_put(np); 223 if (!gpio) { 224 printk(KERN_ERR "%s() failed. expect abnormal behavior\n", 225 __func__); 226 return; 227 } 228 229 /* Set port config */ 230 port_config = in_be32(&gpio->port_config); 231 232 port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */ 233 port_config |= 0x01000000; 234 235 out_be32(&gpio->port_config, port_config); 236 237 /* Unmap zone */ 238 iounmap(gpio); 239 240 } 241 242 /* list of the supported boards */ 243 static const char *board[] __initdata = { 244 "fsl,media5200", 245 NULL 246 }; 247 248 /* 249 * Called very early, MMU is off, device-tree isn't unflattened 250 */ 251 static int __init media5200_probe(void) 252 { 253 return of_flat_dt_match(of_get_flat_dt_root(), board); 254 } 255 256 define_machine(media5200_platform) { 257 .name = "media5200-platform", 258 .probe = media5200_probe, 259 .setup_arch = media5200_setup_arch, 260 .init = mpc52xx_declare_of_platform_devices, 261 .init_IRQ = media5200_init_irq, 262 .get_irq = mpc52xx_get_irq, 263 .restart = mpc52xx_restart, 264 .calibrate_decr = generic_calibrate_decr, 265 }; 266