1bfee95bbSGrant Likely /* 2bfee95bbSGrant Likely * Support for 'media5200-platform' compatible boards. 3bfee95bbSGrant Likely * 4bfee95bbSGrant Likely * Copyright (C) 2008 Secret Lab Technologies Ltd. 5bfee95bbSGrant Likely * 6bfee95bbSGrant Likely * This program is free software; you can redistribute it and/or modify it 7bfee95bbSGrant Likely * under the terms of the GNU General Public License as published by the 8bfee95bbSGrant Likely * Free Software Foundation; either version 2 of the License, or (at your 9bfee95bbSGrant Likely * option) any later version. 10bfee95bbSGrant Likely * 11bfee95bbSGrant Likely * Description: 12bfee95bbSGrant Likely * This code implements support for the Freescape Media5200 platform 13bfee95bbSGrant Likely * (built around the MPC5200 SoC). 14bfee95bbSGrant Likely * 15bfee95bbSGrant Likely * Notable characteristic of the Media5200 is the presence of an FPGA 16bfee95bbSGrant Likely * that has all external IRQ lines routed through it. This file implements 17bfee95bbSGrant Likely * a cascaded interrupt controller driver which attaches itself to the 18bfee95bbSGrant Likely * Virtual IRQ subsystem after the primary mpc5200 interrupt controller 19bfee95bbSGrant Likely * is initialized. 20bfee95bbSGrant Likely * 21bfee95bbSGrant Likely */ 22bfee95bbSGrant Likely 23bfee95bbSGrant Likely #undef DEBUG 24bfee95bbSGrant Likely 25bfee95bbSGrant Likely #include <linux/irq.h> 26bfee95bbSGrant Likely #include <linux/interrupt.h> 27bfee95bbSGrant Likely #include <linux/io.h> 28bfee95bbSGrant Likely #include <asm/time.h> 29bfee95bbSGrant Likely #include <asm/prom.h> 30bfee95bbSGrant Likely #include <asm/machdep.h> 31bfee95bbSGrant Likely #include <asm/mpc52xx.h> 32bfee95bbSGrant Likely 33bfee95bbSGrant Likely static struct of_device_id mpc5200_gpio_ids[] __initdata = { 34bfee95bbSGrant Likely { .compatible = "fsl,mpc5200-gpio", }, 35bfee95bbSGrant Likely { .compatible = "mpc5200-gpio", }, 36bfee95bbSGrant Likely {} 37bfee95bbSGrant Likely }; 38bfee95bbSGrant Likely 39bfee95bbSGrant Likely /* FPGA register set */ 40bfee95bbSGrant Likely #define MEDIA5200_IRQ_ENABLE (0x40c) 41bfee95bbSGrant Likely #define MEDIA5200_IRQ_STATUS (0x410) 42bfee95bbSGrant Likely #define MEDIA5200_NUM_IRQS (6) 43bfee95bbSGrant Likely #define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS) 44bfee95bbSGrant Likely 45bfee95bbSGrant Likely struct media5200_irq { 46bfee95bbSGrant Likely void __iomem *regs; 47bfee95bbSGrant Likely spinlock_t lock; 48bfee95bbSGrant Likely struct irq_host *irqhost; 49bfee95bbSGrant Likely }; 50bfee95bbSGrant Likely struct media5200_irq media5200_irq; 51bfee95bbSGrant Likely 52bfee95bbSGrant Likely static void media5200_irq_unmask(unsigned int virq) 53bfee95bbSGrant Likely { 54bfee95bbSGrant Likely unsigned long flags; 55bfee95bbSGrant Likely u32 val; 56bfee95bbSGrant Likely 57bfee95bbSGrant Likely spin_lock_irqsave(&media5200_irq.lock, flags); 58bfee95bbSGrant Likely val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); 59bfee95bbSGrant Likely val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq); 60bfee95bbSGrant Likely out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); 61bfee95bbSGrant Likely spin_unlock_irqrestore(&media5200_irq.lock, flags); 62bfee95bbSGrant Likely } 63bfee95bbSGrant Likely 64bfee95bbSGrant Likely static void media5200_irq_mask(unsigned int virq) 65bfee95bbSGrant Likely { 66bfee95bbSGrant Likely unsigned long flags; 67bfee95bbSGrant Likely u32 val; 68bfee95bbSGrant Likely 69bfee95bbSGrant Likely spin_lock_irqsave(&media5200_irq.lock, flags); 70bfee95bbSGrant Likely val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); 71bfee95bbSGrant Likely val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq)); 72bfee95bbSGrant Likely out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); 73bfee95bbSGrant Likely spin_unlock_irqrestore(&media5200_irq.lock, flags); 74bfee95bbSGrant Likely } 75bfee95bbSGrant Likely 76bfee95bbSGrant Likely static struct irq_chip media5200_irq_chip = { 77b27df672SThomas Gleixner .name = "Media5200 FPGA", 78bfee95bbSGrant Likely .unmask = media5200_irq_unmask, 79bfee95bbSGrant Likely .mask = media5200_irq_mask, 80bfee95bbSGrant Likely .mask_ack = media5200_irq_mask, 81bfee95bbSGrant Likely }; 82bfee95bbSGrant Likely 83bfee95bbSGrant Likely void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc) 84bfee95bbSGrant Likely { 85bfee95bbSGrant Likely int sub_virq, val; 86bfee95bbSGrant Likely u32 status, enable; 87bfee95bbSGrant Likely 88bfee95bbSGrant Likely /* Mask off the cascaded IRQ */ 89239007b8SThomas Gleixner raw_spin_lock(&desc->lock); 90bfee95bbSGrant Likely desc->chip->mask(virq); 91239007b8SThomas Gleixner raw_spin_unlock(&desc->lock); 92bfee95bbSGrant Likely 93bfee95bbSGrant Likely /* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs 94bfee95bbSGrant Likely * are pending. 'ffs()' is 1 based */ 95bfee95bbSGrant Likely status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); 96bfee95bbSGrant Likely enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS); 97bfee95bbSGrant Likely val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT); 98bfee95bbSGrant Likely if (val) { 99bfee95bbSGrant Likely sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1); 100bfee95bbSGrant Likely /* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n", 101bfee95bbSGrant Likely * __func__, virq, status, enable, val - 1, sub_virq); 102bfee95bbSGrant Likely */ 103bfee95bbSGrant Likely generic_handle_irq(sub_virq); 104bfee95bbSGrant Likely } 105bfee95bbSGrant Likely 106bfee95bbSGrant Likely /* Processing done; can reenable the cascade now */ 107239007b8SThomas Gleixner raw_spin_lock(&desc->lock); 108bfee95bbSGrant Likely desc->chip->ack(virq); 109bfee95bbSGrant Likely if (!(desc->status & IRQ_DISABLED)) 110bfee95bbSGrant Likely desc->chip->unmask(virq); 111239007b8SThomas Gleixner raw_spin_unlock(&desc->lock); 112bfee95bbSGrant Likely } 113bfee95bbSGrant Likely 114bfee95bbSGrant Likely static int media5200_irq_map(struct irq_host *h, unsigned int virq, 115bfee95bbSGrant Likely irq_hw_number_t hw) 116bfee95bbSGrant Likely { 1176cff46f4SMichael Ellerman struct irq_desc *desc = irq_to_desc(virq); 118bfee95bbSGrant Likely 119bfee95bbSGrant Likely pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw); 120bfee95bbSGrant Likely set_irq_chip_data(virq, &media5200_irq); 121bfee95bbSGrant Likely set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq); 122bfee95bbSGrant Likely set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 123bfee95bbSGrant Likely desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 124bfee95bbSGrant Likely desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL; 125bfee95bbSGrant Likely 126bfee95bbSGrant Likely return 0; 127bfee95bbSGrant Likely } 128bfee95bbSGrant Likely 129bfee95bbSGrant Likely static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct, 13040d50cf7SRoman Fietze const u32 *intspec, unsigned int intsize, 131bfee95bbSGrant Likely irq_hw_number_t *out_hwirq, 132bfee95bbSGrant Likely unsigned int *out_flags) 133bfee95bbSGrant Likely { 134bfee95bbSGrant Likely if (intsize != 2) 135bfee95bbSGrant Likely return -1; 136bfee95bbSGrant Likely 137bfee95bbSGrant Likely pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]); 138bfee95bbSGrant Likely *out_hwirq = intspec[1]; 139bfee95bbSGrant Likely *out_flags = IRQ_TYPE_NONE; 140bfee95bbSGrant Likely return 0; 141bfee95bbSGrant Likely } 142bfee95bbSGrant Likely 143bfee95bbSGrant Likely static struct irq_host_ops media5200_irq_ops = { 144bfee95bbSGrant Likely .map = media5200_irq_map, 145bfee95bbSGrant Likely .xlate = media5200_irq_xlate, 146bfee95bbSGrant Likely }; 147bfee95bbSGrant Likely 148bfee95bbSGrant Likely /* 149bfee95bbSGrant Likely * Setup Media5200 IRQ mapping 150bfee95bbSGrant Likely */ 151bfee95bbSGrant Likely static void __init media5200_init_irq(void) 152bfee95bbSGrant Likely { 153bfee95bbSGrant Likely struct device_node *fpga_np; 154bfee95bbSGrant Likely int cascade_virq; 155bfee95bbSGrant Likely 156bfee95bbSGrant Likely /* First setup the regular MPC5200 interrupt controller */ 157bfee95bbSGrant Likely mpc52xx_init_irq(); 158bfee95bbSGrant Likely 159bfee95bbSGrant Likely /* Now find the FPGA IRQ */ 160bfee95bbSGrant Likely fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga"); 161bfee95bbSGrant Likely if (!fpga_np) 162bfee95bbSGrant Likely goto out; 163bfee95bbSGrant Likely pr_debug("%s: found fpga node: %s\n", __func__, fpga_np->full_name); 164bfee95bbSGrant Likely 165bfee95bbSGrant Likely media5200_irq.regs = of_iomap(fpga_np, 0); 166bfee95bbSGrant Likely if (!media5200_irq.regs) 167bfee95bbSGrant Likely goto out; 168bfee95bbSGrant Likely pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs); 169bfee95bbSGrant Likely 170bfee95bbSGrant Likely cascade_virq = irq_of_parse_and_map(fpga_np, 0); 171bfee95bbSGrant Likely if (!cascade_virq) 172bfee95bbSGrant Likely goto out; 173bfee95bbSGrant Likely pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq); 174bfee95bbSGrant Likely 175bfee95bbSGrant Likely /* Disable all FPGA IRQs */ 176bfee95bbSGrant Likely out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0); 177bfee95bbSGrant Likely 178bfee95bbSGrant Likely spin_lock_init(&media5200_irq.lock); 179bfee95bbSGrant Likely 180bfee95bbSGrant Likely media5200_irq.irqhost = irq_alloc_host(fpga_np, IRQ_HOST_MAP_LINEAR, 181bfee95bbSGrant Likely MEDIA5200_NUM_IRQS, 182bfee95bbSGrant Likely &media5200_irq_ops, -1); 183bfee95bbSGrant Likely if (!media5200_irq.irqhost) 184bfee95bbSGrant Likely goto out; 185bfee95bbSGrant Likely pr_debug("%s: allocated irqhost\n", __func__); 186bfee95bbSGrant Likely 187bfee95bbSGrant Likely media5200_irq.irqhost->host_data = &media5200_irq; 188bfee95bbSGrant Likely 189bfee95bbSGrant Likely set_irq_data(cascade_virq, &media5200_irq); 190bfee95bbSGrant Likely set_irq_chained_handler(cascade_virq, media5200_irq_cascade); 191bfee95bbSGrant Likely 192bfee95bbSGrant Likely return; 193bfee95bbSGrant Likely 194bfee95bbSGrant Likely out: 195bfee95bbSGrant Likely pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n"); 196bfee95bbSGrant Likely } 197bfee95bbSGrant Likely 198bfee95bbSGrant Likely /* 199bfee95bbSGrant Likely * Setup the architecture 200bfee95bbSGrant Likely */ 201bfee95bbSGrant Likely static void __init media5200_setup_arch(void) 202bfee95bbSGrant Likely { 203bfee95bbSGrant Likely 204bfee95bbSGrant Likely struct device_node *np; 205bfee95bbSGrant Likely struct mpc52xx_gpio __iomem *gpio; 206bfee95bbSGrant Likely u32 port_config; 207bfee95bbSGrant Likely 208bfee95bbSGrant Likely if (ppc_md.progress) 209bfee95bbSGrant Likely ppc_md.progress("media5200_setup_arch()", 0); 210bfee95bbSGrant Likely 211bfee95bbSGrant Likely /* Map important registers from the internal memory map */ 212bfee95bbSGrant Likely mpc52xx_map_common_devices(); 213bfee95bbSGrant Likely 214bfee95bbSGrant Likely /* Some mpc5200 & mpc5200b related configuration */ 215bfee95bbSGrant Likely mpc5200_setup_xlb_arbiter(); 216bfee95bbSGrant Likely 217bfee95bbSGrant Likely mpc52xx_setup_pci(); 218bfee95bbSGrant Likely 219bfee95bbSGrant Likely np = of_find_matching_node(NULL, mpc5200_gpio_ids); 220bfee95bbSGrant Likely gpio = of_iomap(np, 0); 221bfee95bbSGrant Likely of_node_put(np); 222bfee95bbSGrant Likely if (!gpio) { 223bfee95bbSGrant Likely printk(KERN_ERR "%s() failed. expect abnormal behavior\n", 224bfee95bbSGrant Likely __func__); 225bfee95bbSGrant Likely return; 226bfee95bbSGrant Likely } 227bfee95bbSGrant Likely 228bfee95bbSGrant Likely /* Set port config */ 229bfee95bbSGrant Likely port_config = in_be32(&gpio->port_config); 230bfee95bbSGrant Likely 231bfee95bbSGrant Likely port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */ 232bfee95bbSGrant Likely port_config |= 0x01000000; 233bfee95bbSGrant Likely 234bfee95bbSGrant Likely out_be32(&gpio->port_config, port_config); 235bfee95bbSGrant Likely 236bfee95bbSGrant Likely /* Unmap zone */ 237bfee95bbSGrant Likely iounmap(gpio); 238bfee95bbSGrant Likely 239bfee95bbSGrant Likely } 240bfee95bbSGrant Likely 241bfee95bbSGrant Likely /* list of the supported boards */ 242a4f740cfSGrant Likely static const char *board[] __initdata = { 243bfee95bbSGrant Likely "fsl,media5200", 244bfee95bbSGrant Likely NULL 245bfee95bbSGrant Likely }; 246bfee95bbSGrant Likely 247bfee95bbSGrant Likely /* 248bfee95bbSGrant Likely * Called very early, MMU is off, device-tree isn't unflattened 249bfee95bbSGrant Likely */ 250bfee95bbSGrant Likely static int __init media5200_probe(void) 251bfee95bbSGrant Likely { 252a4f740cfSGrant Likely return of_flat_dt_match(of_get_flat_dt_root(), board); 253bfee95bbSGrant Likely } 254bfee95bbSGrant Likely 255bfee95bbSGrant Likely define_machine(media5200_platform) { 256bfee95bbSGrant Likely .name = "media5200-platform", 257bfee95bbSGrant Likely .probe = media5200_probe, 258bfee95bbSGrant Likely .setup_arch = media5200_setup_arch, 259bfee95bbSGrant Likely .init = mpc52xx_declare_of_platform_devices, 260bfee95bbSGrant Likely .init_IRQ = media5200_init_irq, 261bfee95bbSGrant Likely .get_irq = mpc52xx_get_irq, 262bfee95bbSGrant Likely .restart = mpc52xx_restart, 263bfee95bbSGrant Likely .calibrate_decr = generic_calibrate_decr, 264bfee95bbSGrant Likely }; 265